WP_Term Object
(
    [term_id] => 34
    [name] => ANSYS, Inc.
    [slug] => ansys-inc
    [term_group] => 0
    [term_taxonomy_id] => 34
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 189
    [filter] => raw
    [cat_ID] => 34
    [category_count] => 189
    [category_description] => 
    [cat_name] => ANSYS, Inc.
    [category_nicename] => ansys-inc
    [category_parent] => 157
)

Noise & Reliability of FinFET Designs – Success Stories!

Noise & Reliability of FinFET Designs – Success Stories!
by Pawan Fangaria on 11-01-2014 at 7:00 am

I think by now there has been good level of discussion on FinFET technology at sub-20 nm process nodes and this is an answer to ultra dense, high performance, low power, and billion+ gate SoC designs within the same area. However, it comes with some of the key challenges with respect to power, noise and reliability of the design. A FinFET typically operating at lower supply voltage and higher drive strength reduces noise margin and increases transient noise. The higher current density (~25% more with a typical FinFET transistor) in smaller fragile interconnects of a dense design severely impacts electro migration (EM) making EM sign-off critical. Additionally the fin structure of FinFET provides little space for heat to escape, thus leading to heat accumulation and further impacting EM and ESD (Electrostatic Discharge). Also, higher gate count and additional metal layers significantly increase simulation runtime and memory requirements, especially for full-chip analyses (with package and PCB data for better accuracy). In order to tackle these issues, multiple methods / engines with silicon level accuracy (involving multi physics simulations) along with smart computational algorithms to tackle large sizes of designs (including package and system information) must be used.

Upholding these requirements, ANSYShas added new capabilities in its production proven (with thousands of designs into successful silicon) RedHawk platform to include FinFETs and 2.5D/3D ICs with TSVs (through-silicon vias).

To tackle high capacity and high performance, RedHawk’s DMP (Distributed Machine Processing) technology smartly distributes a design database across a network of machines where each machine analyzes a portion of the design within the context of the entire chip including package, thus providing flat sign-off accuracy at enhanced performance and reduced memory per machine for full-chip voltage drop, EM and ESD analyses.

RedHawk employs state-of-the-science engines to meet these challenges of next generation SoCs; an integrated solver as transient simulation engine that can handle 2 B+ node of RLC network matrices along with distributed and cross-coupled package models; a high performance ALP3D solver for power up (rush current) analysis in complex power gate architectures. An engine to support stacked-die structures allows simulation of heterogeneous designs where each die and interposer can be based on different process technologies. Apache Power Library (APL) remains a fundamental underlying technology through its ability to capture nonlinear behaviour of circuit elements into compact, linear models that enable full-chip simulations while achieving sign-off quality results comparable to Spice. RedHawk handles ever increasing complex EM rules and quickly identifies EM hotspots related to power and signal wires as well as ESD failures.

RedHawk uses APL and Custom Macro Model (CMM) to incorporate device-level RC parasitics and switching current waveforms for full-chip transient simulation at pico-second resolution that provides Spice level sign-off accuracy. It simulates all power and ground domains simultaneously to accurately predict the current drawn and voltage seen at every cell in the design, and noise coupling that can happen inside the chip. At sub-20nm, for FinFET based designs, the modeling, extraction and analysis capabilities are expanded to support special metal layers, complex via structures, dummy devices, vertical resistances and double patterning.

RedHawk-CPA (in RedHawk 2014 release) accurately analyzes the effect of package parasitics on dynamic voltage drop which takes into account the current flow inside the package and bumps, necessary for increasing accuracy levels at advanced nodes and FinFET based designs. It provides comprehensive chip-package sign-off through its integrated extraction, model hook-up, and co-simulation capabilities. Its 3D FEM solver uses package layout and material property to generate a detailed per-bump parasitic network model that is appropriate for time-domain simulations. RedHawk-CPA enables seamless merging of fully distributed package parasitic network (that provides increased granularity and accuracy) with the on-die PDN. It displays both the chip and the package layouts and analysis results, enabling co-analysis, debug and simultaneous optimization.

RedHawk’s current flow-aware extraction techniques help in achieving sign-off quality results for every wire and via that enable in accurate analysis of EM violations on power/ground and signal lines. PathFinder supports IP and SoC level ESD integrity analysis by providing connectivity as well as interconnects failure checks for all current flow pathways from an ESD event (HBM or CDM).

As discussed earlier, heat generation and trapping in a FinFET based design can significantly impact lifetime of the device. ANSYS’s comprehensive chip-package-system thermal analysis flow takes in chip data along with package and system to generate accurate on-chip thermal profiles which are used by RedHawk to enable thermal-aware EM and ESD analysis. A Chip Thermal Model (CTM) created using temperature-aware power density and package thermal boundary conditions from a system simulation enables required thermal integrity for FinFET and 3D ICs.

ANSYS solution provides best coverage of power integrity and reliability verification for RTL to GDS power noise closure with and without input vectors. PowerArtist enables a physical-aware RTL design for power methodology that creates RPM (RTL Power Model) of a given design. RedHawk’s VectorLessengine along with logic simulation (using RTL VCD), state propagation (using activity) and gate level VCD simulation engines enable a comprehensive analysis toolkit for dynamic power noise. It can work in mixed-mode, for example with one block having gate level VCD, another having RTL vectors and rest of the design using VectorLess engine to generate the overall switching scenario. RedHawk provides enhanced capabilities to accurately simulate an on-chip LDO (low-dropout regulator) during full-chip static and dynamic simulations enabling sign-off confidence.

For easy and flexible analysis of results and comprehensive debugging (identifying design weaknesses and their fixes), RedHawk provides multi-tab, multi-pane GUI which allows simultaneous display of multiple results and tables, and multiple chip layouts with their own power densities and impact on each other.

Ansys’s power noise and reliability solution also includes production proven system-level simulation solutions: SIWave for signal integrity, Icepak for thermal integrity and HFSS for EMI and high frequency analysis.

ANSYS provides most comprehensive platform for system-aware chip simulation as well as chip-package-aware system simulation. Read the whitepaperposted at ANSYS website to know more details about each of these capabilities.

RedHawk is certified for 16 nm FinFET based design sign-off by TSMCand Tri-Gate based design reference flow at 14nm by Intel. These foundry certifications along with substantial successful production with ANSYS solutions provide increased confidence in these advanced technologies. Read more on the certifications here –
Intel & ANSYS Enable 14nm Chip Production
ANSYS Tools Shine at FinFET Nodes!

A recent success story of chip production with ANSYS power, noise and reliability solution was at NXPwhere a complex RF-CMOS IC has shown very good correlation with simulation results. To know more about how they have used ANSYS tools for this IC, attend a free webinarto be presented by NXP, here is the schedule –

Webinar: Noise coupling analysis for advanced mixed-signal IC’s
Date: Tuesday, November 4, 2014 – 8:00am – 9:00am PST
Location: Online
Register here

More Articles by PawanFangaria…..


Comments

There are no comments yet.

You must register or log in to view/post comments.