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Shift Left with S2C Prodigy: From RTL Verification to Real-World Software Validation

Shift Left with S2C Prodigy: From RTL Verification to Real-World Software Validation
by Daniel Nenni on 08-04-2026 at 10:00 am

HAV

For modern SoC teams, “shift left” no longer means finding a few more RTL bugs before tape-out. It means moving meaningful system validation earlier—far enough left that firmware, operating systems, drivers, applications, and external interfaces can be exercised before first silicon arrives. This change is essential as software… Read More


ASIC-to-FPGA Turnkey Prototyping Bundle: A Practical Path to Earlier Hardware Validation

ASIC-to-FPGA Turnkey Prototyping Bundle: A Practical Path to Earlier Hardware Validation
by Daniel Nenni on 07-29-2026 at 6:00 am

S2C FPGA Prototyping

For ASIC design teams, the gap between RTL simulation and first silicon remains one of the most consequential stages of the development cycle. Simulation provides controllability and visibility, but it cannot always reproduce the software workloads, interface behavior, clock interactions, and sustained system activity… Read More


COMPUTEX 2026: S2C and Andes Technology Showcase Hardcore “EDA+IP” Synergy for the AI Era

COMPUTEX 2026: S2C and Andes Technology Showcase Hardcore “EDA+IP” Synergy for the AI Era
by Daniel Nenni on 06-25-2026 at 6:00 am

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COMPUTEX 2026 officially concluded under the theme “AI Together,” bringing the global semiconductor and computing ecosystem together to showcase the latest advances in artificial intelligence, HPC, and intelligent systems. While AI accelerators and advanced computing platforms dominated the exhibition floor, one collaboration… Read More


Technical Paper: FPGA Prototyping That Creates Useful PreSilicon Evidence

Technical Paper: FPGA Prototyping That Creates Useful PreSilicon Evidence
by Daniel Nenni on 06-11-2026 at 6:00 am

FPGA Prototyping Beyond RTL Fit Building Useful Pre Silicon Evidence

As semiconductor designs continue to grow in complexity, FPGA prototyping has become an essential component of modern pre-silicon validation strategies. While FPGA capacity and gate-count equivalence often dominate discussions around prototyping platforms, the true value of an FPGA prototype lies elsewhere: its ability… Read More


The “New Shift-Left”: Why FPGA Prototyping is the Ultimate RISC-V IP Sandbox

The “New Shift-Left”: Why FPGA Prototyping is the Ultimate RISC-V IP Sandbox
by Daniel Nenni on 05-14-2026 at 10:00 am

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In the EDA world, “Shift-Left” has traditionally been a mantra for early software development—booting the OS before the silicon even leaves the fab. But as the RISC-V revolution accelerates, the goalposts have moved. We are seeing the emergence of a “New Shift-Left”, one that focuses on critical architectural… Read More


2026 Outlook with Ying J Chen of S2C

2026 Outlook with Ying J Chen of S2C
by Daniel Nenni on 01-22-2026 at 6:00 am

Ying J Chen of S2C

I’m Ying J Chen, VP of S2C. S2C is a leading global supplier of FPGA prototyping solutions for advanced SoC and ASIC designs, holding the second largest share of the global prototyping market. Founded in 2003, the company has supported more than 600 customers, including 11 of the top 25 semiconductor companies worldwide, with teams… Read More


Accelerating Advanced FPGA-Based SoC Prototyping With S2C

Accelerating Advanced FPGA-Based SoC Prototyping With S2C
by Daniel Nenni on 01-18-2026 at 12:00 pm

Prodigy S8 100 Logic Systems

Having spent a significant amount of my career in EDA and IP I can tell you first hand how important picking the right prototyping partner is. I have known S2C since my interview with CEO Toshio Nakama in 2017. It has been a pleasure working with them and I look forward to seeing an S2C update at DVCon the first week of March here in Silicon… Read More


There is more to prototyping than just FPGA: See how S2C accelerates SoC Bring-Up with high productivity toolchain?

There is more to prototyping than just FPGA: See how S2C accelerates SoC Bring-Up with high productivity toolchain?
by Daniel Nenni on 01-15-2026 at 10:00 am

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System-on-Chip designs continue to grow in scale and interface diversity, placing greater demands on prototype capacity, interconnect planning, and bring-up efficiency. These challenges arise not only in large multi-FPGA programs but also in smaller designs implemented on a single device or a small FPGA cluster. In all cases,… Read More


S2C, MachineWare, and Andes Introduce RISC-V Co-Emulation Solution to Accelerate Chip Development

S2C, MachineWare, and Andes Introduce RISC-V Co-Emulation Solution to Accelerate Chip Development
by Daniel Nenni on 12-16-2025 at 10:00 am

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MachineWare, and Andes Technology today announced a collaborative co-emulation solution designed to address the increasing complexity of RISC-V-based chip design. The solution integrates MachineWare’s SIM-V virtual platform, S2C’s Genesis Architect and Prodigy FPGA Prototyping Systems, and Andes’ high-performance… Read More


FPGA Prototyping in Practice: Addressing Peripheral Connectivity Challenges

FPGA Prototyping in Practice: Addressing Peripheral Connectivity Challenges
by Daniel Nenni on 11-19-2025 at 10:00 am

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Modern chip design verification often encounters challenges when connecting peripherals, primarily due to drastic differences in operating speed or hardware limitations. Designs running on hardware emulators or FPGA prototyping platforms typically operate at clock frequencies of tens of megahertz, and in some cases even… Read More