WP_Term Object
(
    [term_id] => 14325
    [name] => Accellera
    [slug] => accellera
    [term_group] => 0
    [term_taxonomy_id] => 14325
    [taxonomy] => category
    [description] => 
    [parent] => 386
    [count] => 9
    [filter] => raw
    [cat_ID] => 14325
    [category_count] => 9
    [category_description] => 
    [cat_name] => Accellera
    [category_nicename] => accellera
    [category_parent] => 386
    [is_post] => 
)
            
DVCon Banner 2020 SemiWiki
WP_Term Object
(
    [term_id] => 14325
    [name] => Accellera
    [slug] => accellera
    [term_group] => 0
    [term_taxonomy_id] => 14325
    [taxonomy] => category
    [description] => 
    [parent] => 386
    [count] => 9
    [filter] => raw
    [cat_ID] => 14325
    [category_count] => 9
    [category_description] => 
    [cat_name] => Accellera
    [category_nicename] => accellera
    [category_parent] => 386
    [is_post] => 
)

Functional Safety Comes to EDA and IP

Functional Safety Comes to EDA and IP
by Daniel Payne on 11-13-2019 at 10:00 am

Every week I read headlines about the progress of autonomous vehicles, and the inevitable questions began to arise, like, “Just how safe is this AV?”, or “Is this new ADAS feature trustworthy?” The automotive industry has already setup the ISO 26262 functional safety standard, and we’ve bloggedRead More


Accellera IP Security Standard: A Start

Accellera IP Security Standard: A Start
by Bernard Murphy on 10-10-2019 at 5:00 am

IPSA Workflow

I mentioned some time ago (a DVCon or two ago) that Accellera had started working on a standard to quantify IP security. At the time I talked about some of the challenges in the task but nevertheless applauded the effort. You’ve got to start somewhere and some way to quantify this is better than none, as long as it doesn’t deliver misleading… Read More


Semiconductor IP Security Issues

Semiconductor IP Security Issues
by Daniel Payne on 05-26-2019 at 4:46 pm

Accellera

Every morning I read the headlines from SemiWiki, CNN, LinkedIn and my Twitter feed, and it seems like every week that I read about another security breach that makes me wonder if anything online is secure. Companies try to harden their web sites, IT infrastructure and even their electronic products from being exploited or tampered… Read More


Accellera Tackles IP Security

Accellera Tackles IP Security
by Bernard Murphy on 10-04-2018 at 7:00 am

I recently learned that Accellera has formed an IP security working group. My first reaction was “Great, we really need that!”. My second reaction was “But I have so many questions.” Security in the systems world is still very much a topic in its infancy. I don’t mean to imply that there isn’t good work being done in both software and… Read More


Lu Dai: Incoming Accellera Chair

Lu Dai: Incoming Accellera Chair
by Bernard Murphy on 03-11-2017 at 7:00 am

One of the fun things about what I do is getting to meet some of the movers and shakers in the industry. You might not think of Accellera as a spot to find movers and shakers, but when you consider the impact they have had on what we do (OVL, SystemVerilog, UVM, UPF, SystemC, IP-XACT and others), design today would be unrecognizable without… Read More


Accellera and Portable Stimulus

Accellera and Portable Stimulus
by Bernard Murphy on 03-08-2016 at 7:00 am

I’ll start with a quick note on DVCon. This seems to be gaining momentum each year. In addition to the events in the US, Europe and India, a DVCon event is now planned for China, kicking off in Shanghai in 2017. At a time when we’re all bemoaning the future of EDA and EDA conferences, DVCon is booming internationally, no doubt reflecting… Read More


Coming to a Workstation Near You: Accellera’s Portable Stimulus Standard

Coming to a Workstation Near You: Accellera’s Portable Stimulus Standard
by Ellie Burns on 11-29-2015 at 7:00 am

Portable Stimulus has become such a popular standards topic of late that I thought it would be good to take a break this month from my low power series to bring you, my valued readers, more information about it from one of my colleagues, Dennis Brophy, who is working to help drive development of this standard within Accellera. I’ll Read More


UVM/SystemVerilog: Verification and Debugging

UVM/SystemVerilog: Verification and Debugging
by Daniel Payne on 05-13-2013 at 2:45 pm

At DAC in just three weeks you can learn about which EDA vendors are supporting the latest UVM 1.1d (Universal Verification Methodology) standard as defined by Accellera. One of those EDA vendors is Aldec, and they have a 45 minute technical session that you can register for online. Space will fill up quickly, so get signed up sooner… Read More


Accelera Technical Excellence Award

Accelera Technical Excellence Award
by Paul McLellan on 11-30-2012 at 3:46 pm

The Accellera Systems Initiative, most well-known for driving the standardization of various aspects of Verilog and SystemVerilog before handing the standards off to the IEEE, has announced that nominations are open for the 2013 Technical Excellence Award. This recognizes outstanding contributions in the creation of EDA… Read More