In a major announcement at the 2025 Design Automation Conference (DAC), Siemens EDA introduced a significant expansion to its electronic design automation (EDA) portfolio, aimed at transforming how engineers design, validate, and manage the complexity of next-generation three-dimensional integrated circuits (3D ICs).… Read More
Webinar – Power is the New Performance: Scaling Power & Performance for Next Generation SoCs
What if you could reduce power and extend chip lifetime, without compromising performance? We all know the importance of power optimization for advanced SoCs. Thanks to the massive build out of AI workloads, power consumption has gone from a cost or cooling headache to an existential threat to the planet, if current power consumptions… Read More
proteanTecs at the 2025 Design Automation Conference #62DAC
Discover how proteanTecs is transforming health and performance monitoring across the semiconductor lifecycle to meet the growing demands of AI and Next-Gen SoCs.
Stop by DAC booth #1616 to experience our latest technologies in action, including interactive live demos and explore our full suite of solutions — designed to boost… Read More
Leveraging Common Weakness Enumeration (CWEs) for Enhanced RISC-V CPU Security
As RISC-V adoption accelerates across the semiconductor industry, so do the concerns about hardware security vulnerabilities that arise from its open and highly customizable nature. From hardware to firmware and operating systems, every layer of a system-on-chip (SoC) design must be scrutinized for security risks. Unlike… Read More
The Growing Importance of PVT Monitoring for Silicon Lifecycle Management
In an era defined by complex chip architectures, ever-shrinking technology nodes and very demanding applications, Silicon Lifecycle Management (SLM) has become a foundational strategy for optimizing performance, reliability, and efficiency across the lifespan of a semiconductor device. Central to effective SLM are Process,… Read More
Podcast EP279: Guy Gozlan on how proteanTecs is Revolutionizing Real-Time ML Testing
Dan is joined by Guy Gozlan, proteanTecs director of machine learning and algorithms, overseeing research, implementation, and infrastructure of machine learning solutions. Prior to proteanTecs he was project lead at Apple, focusing on ATE optimizations using embedded software and machine learning and embedded software… Read More
Cut Defects, Not Yield: Outlier Detection with ML Precision
How much perfectly good silicon is being discarded in the quest for reliability? During high-volume chip manufacturing, aggressive testing with strict thresholds may ensure quality but reduces yield, discarding marginal chips that could function flawlessly. On the other hand, prioritizing yield risks allowing defective… Read More
2025 Outlook with Uzi Baruch of proteanTecs
Tell us a little bit about yourself and your company.
I am the Chief Strategy Officer at proteanTecs where I oversee our organic and inorganic growth strategies, as well as our go-to-market. This includes collaboration with ecosystem partners, defining our business model, and creating value for our customers through a targeted… Read More
Enhancing System Reliability with Digital Twins and Silicon Lifecycle Management (SLM)
As industries become more reliant on advanced technologies, the importance of ensuring the reliability and longevity of critical systems grows. Failures in components, whether in autonomous vehicles, high performance computing (HPC), healthcare devices, or industrial automation, can have far-reaching consequences.… Read More
Datacenter Chipmaker Achieves Power Reduction With proteanTecs AVS Pro
As semiconductor technology advances and nodes continue to shrink, designers are faced with increasing challenges related to device complexity, power consumption, and reliability. The delicate balance between high performance, low power usage, and long-term reliability is more critical than ever. This growing demand … Read More
Facing the Quantum Nature of EUV Lithography