Let’s face it, powerful, highly trained AI is making it easier to find security flaws in many systems. When the attack surface becomes the underlying hardware, the risks grow exponentially. Unlike software, hardware can’t easily be “patched”. Early, advanced security verification is the way to mitigate these risks, but doing… Read More
Podcast EP347: Agentic Workflows from Caspia Technologies for Advanced Chip Security Verification with Stuart Audley
Daniel is joined by Stuart Audley, vice president and general manager of product management at Caspia Technologies, where he focuses on agentic security workflows. He has decades of experience designing and deploying cryptographic hardware and security IP for top defense and leading semiconductor companies. He previously… Read More
PQShield unveils ultra-small PQC embedded security breakthroughs at Embedded World 2026
As the threat of quantum computing to modern cybersecurity becomes increasingly real, the technology industry is accelerating efforts to develop cryptographic systems capable of resisting quantum attacks. One of the most significant developments in this field was presented at Embedded World 2026 in Nuremberg, Germany, … Read More
Effective Defense Against Hacks at the Edge
IoT permeates every aspect of our lives, in payment systems, access authorization, vehicles, utilities, factories, hospitals, and in so many other fields. Which makes these systems attractive targets for hacking and social disruption while also challenging to protect given the highly constrained resources that many such… Read More
Capability Hardware Enhanced RISC Instructions CHERI Alliance
The CHERI Alliance is a non-profit organization dedicated to accelerating the global adoption of CHERI (Capability Hardware Enhanced RISC Instructions), a technology designed to improve computer security at the hardware level. Established as an independent entity, the Alliance brings together industry leaders, researchers,… Read More
CHERI: Hardware-Enforced Capability Architecture for Systematic Memory Safety
The rapid escalation of cyberattacks over the past two decades has exposed a fundamental weakness at the core of modern computing systems: the lack of memory safety. Industry data consistently shows that the majority of critical software vulnerabilities stem from memory corruption issues such as buffer overflows, use-after-free… Read More
Securing RISC-V Third-Party IP: Enabling Comprehensive CWE-Based Assurance Across the Design Supply Chain
by Jagadish Nayak
RISC-V adoption continues to accelerate across commercial and government microelectronics programs. Whether open-source or commercially licensed, most RISC-V processor cores are integrated as third-party IP (3PIP), potentially introducing supply chain security challenges that demand structured,… Read More
Caspia Technologies Unveils A Breakthrough in RTL Security Verification Paving the Way for Agentic Silicon Security
In a significant advancement for the semiconductor industry, Caspia Technologies announced the broad availability of CODAx V2026.1, its flagship RTL security analyzer. The new release strengthens early-stage hardware security verification and positions the company to deliver fully agentic workflows that automate vulnerability… Read More
PQShield on Preparing for Q-Day
Following my series on quantum computing (QC), it is timely to look again at what is still the most prominent real-world concern around this technology: its ability to hack classical security methods for encryption and related tasks. Given what I have written on the topic, an understandable counter would be that QC is still in development… Read More
2026 Outlook with Richard Hegberg of Caspia Technologies
Tell us a little bit about yourself and your company
I’m Rick Hegberg and I’ve been CEO of Caspia Technologies since 2024. I have a deep semiconductor background, including CEO roles at three semiconductor start-ups and executive roles at SanDisk/WD, Qualcomm, Atheros, Numonyx/Micron, ATI/AMD, and VLSI Technology.
Throughout… Read More


Intel: Pushing EMIB Forward: Design Methodology Insights with Synopsys Tools