CAST Compression IP Webinar 800x100 (2)
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Podcast EP297: An Overview of sureCore’s New Silicon Services with Paul Wells

Podcast EP297: An Overview of sureCore’s New Silicon Services with Paul Wells
by Daniel Nenni on 07-11-2025 at 10:00 am

Dan is joined by sureCore CEO Paul Wells. Paul has worked in the semiconductor industry for over 25 years including two years as director of engineering for Pace Networks, where he led a multidisciplinary, 70 strong product development team creating a broadcast quality video & data mini-headend. Before that, he worked for… Read More


AI Booming is Fueling Interface IP 23.5% YoY Growth

AI Booming is Fueling Interface IP 23.5% YoY Growth
by Eric Esteve on 07-10-2025 at 6:00 am

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AI explosion is clearly driving semi-industry since 2020. AI processing, based on GPU, need to be as powerful as possible, but a system will reach optimum only if it can rely on top interconnects. The various sub-system need to be interconnected with ever more bandwidth and lower latency, creating the need for ever advanced protocol… Read More


Arteris Simplifies Design Reuse with Magillem Packaging

Arteris Simplifies Design Reuse with Magillem Packaging
by Mike Gianfagna on 07-08-2025 at 6:00 am

Arteris Simplifies Design Reuse with Magillem Packaging

Many know Arteris as the “network-on-chip”, or NoC, company. Through acquisitions and forward-looking development, the footprint for Arteris has grown beyond smart interconnect IP. At DAC this year, Arteris highlighted its latest expansion with a new SoC integration automation product called Magillem Packaging. The announcement… Read More


MEMS Technology – From Fringe to Mainstream

MEMS Technology – From Fringe to Mainstream
by Daniel Nenni on 07-07-2025 at 10:00 am

MEMs 2025 SemiWiki

Last month, Lj Ristic delivered an invited talk on MEMS technology as a driving force at the Laser Display and Lighting Conference 2025, held at Trinity College Dublin.  His talk included a review of some major successes of MEMS industry. We used that occasion to talk to him and discuss some major achievements and the status of MEMS… Read More


WEBINAR: Edge AI Optimization: How to Design Future-Proof Architectures for Next-Gen Intelligent Devices

WEBINAR: Edge AI Optimization: How to Design Future-Proof Architectures for Next-Gen Intelligent Devices
by Daniel Nenni on 07-03-2025 at 10:00 am

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Edge AI is rapidly transforming how intelligent solutions are designed, from smart home devices to autonomous vehicles, healthcare gadgets, and industrial IoT. Yet, architects, chip designers, and product managers frequently grapple with a common and daunting challenge: creating efficient, high-performance AI solutions… Read More


WEBINAR Unpacking System Performance: Supercharge Your Systems with Lossless Compression IPs

WEBINAR Unpacking System Performance: Supercharge Your Systems with Lossless Compression IPs
by Daniel Nenni on 07-03-2025 at 6:00 am

CAST Compression IP Webinar 400x400

In today’s data-driven systems—from cloud storage and AI accelerators to automotive logging and edge computing—every byte counts. The exponential growth in data volumes, real-time processing demands, and constrained bandwidth has made efficient, lossless data compression a mission-critical requirement. Software-based… Read More


Siemens EDA Unveils Groundbreaking Tools to Simplify 3D IC Design and Analysis

Siemens EDA Unveils Groundbreaking Tools to Simplify 3D IC Design and Analysis
by Kalar Rajendiran on 07-01-2025 at 10:00 am

Innovator3D IC Solution Suite

In a major announcement at the 2025 Design Automation Conference (DAC), Siemens EDA introduced a significant expansion to its electronic design automation (EDA) portfolio, aimed at transforming how engineers design, validate, and manage the complexity of next-generation three-dimensional integrated circuits (3D ICs).… Read More


Podcast EP294: An Overview of the Momentum and Breadth of the RISC-V Movement with Andrea Gallo

Podcast EP294: An Overview of the Momentum and Breadth of the RISC-V Movement with Andrea Gallo
by Daniel Nenni on 06-27-2025 at 10:00 am

Dan is joined by Andrea Gallo, CEO of RISC-V International, the non-profit home of the RISC-V instruction set architecture standard, related specifications, and stakeholder community. Prior to joining RISC-V International, Gallo worked in leadership roles at Linaro for over a decade. He built Linaro’s server engineering… Read More


Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot

Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot
by Jonah McLeod on 06-24-2025 at 10:00 am

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In 2003, legendary computer architect Michael J. Flynn issued a warning that most of the industry wasn’t ready to hear. The relentless march toward more complex CPUs—with speculative execution, deep pipelines, and bloated instruction handling—was becoming unsustainable. In a paper titled “Computer Architecture … Read More


Enabling RISC-V & AI Innovations with Andes AX45MPV Running Live on S2C Prodigy S8-100 Prototyping System

Enabling RISC-V & AI Innovations with Andes AX45MPV Running Live on S2C Prodigy S8-100 Prototyping System
by Daniel Nenni on 06-24-2025 at 6:00 am

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Qualifying an AI-class RISC-V SoC demands proving that wide vectors, deep caches, and high-speed I/O operate flawlessly long before tape-out. At the recent Andes RISC-V Conference, Andes Technology and S2C showcased this by successfully booting a lightweight large language model (LLM) inference on a single S2C Prodigy™ S8-100… Read More