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Changing RISC-V Verification Requirements, Standardization, Infrastructure

Changing RISC-V Verification Requirements, Standardization, Infrastructure
by Daniel Nenni on 11-07-2024 at 10:00 am

Abstract,Futuristic,Infographic,With,Visual,Data,Complexity,,,Represent,Big

A lively panel discussion about RISC-V and open-source functional verification highlighted this year’s Design Automation Conference. Part One looked at selecting a RISC-V IP block from a third-party vendor and investigating its functional verification process.

In Part Two, moderator Ron Wilson and Contributing Editor … Read More


Semidynamics: A Single-Software-Stack, Configurable and Customizable RISC-V Solution

Semidynamics: A Single-Software-Stack, Configurable and Customizable RISC-V Solution
by Kalar Rajendiran on 11-07-2024 at 6:00 am

Risc V CPU

Founded with a vision to create transformative, customizable IP solutions, Semidynamics has emerged as a significant player in the AI hardware industry. Initially operating as a design engineering company, Semidynamics spent its early years exploring various pathways before pivoting to develop proprietary intellectual… Read More


Arteris Empowering Advances in Inference Accelerators

Arteris Empowering Advances in Inference Accelerators
by Bernard Murphy on 11-06-2024 at 6:00 am

NoC Tiling min

Systolic arrays, with their ability to highly parallelize matrix operations, are at the heart of many modern AI accelerators. Their regular structure is ideally suited to matrix/matrix multiplication, a repetitive sequence of row-by-column multiply-accumulate operations. But that regular structure is less than ideal … Read More


MIPI solutions for driving dual-display foldable devices

MIPI solutions for driving dual-display foldable devices
by Don Dingee on 11-04-2024 at 10:00 am

H3 FPGA with MIPI for driving dual display folding devices

Flexible LCD technology has spurred a wave of creativity in device design, including a new class of foldable phones and an update to the venerable flip phone. Besides the primary display inside the fold – sometimes taking the entire inside area – a smaller secondary display is often found outside the fold. Introducing the secondary… Read More


Notes from DVCon Europe 2024

Notes from DVCon Europe 2024
by Jakob Engblom on 11-04-2024 at 6:00 am

semiwiki 1 dvcon europe 2024 cookie

The 2024 DVCon (Design and Verification) Europe conference took place on October 15 and 16, in its traditional location at the Holiday Inn Munich City Centre. Artificial intelligence and software were prominent topics, along with the traditional DVCon topics like virtual platforms, RTL verification, and validation.

Keynotes:

Read More

Datacenter Chipmaker Achieves Power Reduction With proteanTecs AVS Pro

Datacenter Chipmaker Achieves Power Reduction With proteanTecs AVS Pro
by Kalar Rajendiran on 10-30-2024 at 10:00 am

Alphawave Using proTeanTechs

As semiconductor technology advances and nodes continue to shrink, designers are faced with increasing challenges related to device complexity, power consumption, and reliability. The delicate balance between high performance, low power usage, and long-term reliability is more critical than ever. This growing demand … Read More


Overcoming obstacles with mixed-signal and analog design integration

Overcoming obstacles with mixed-signal and analog design integration
by Chris Morrison on 10-28-2024 at 10:00 am

Central,Computer,Processors,Cpu,Concept.,3d,Rendering,conceptual,Image.

Mixed-signal and analog design are key aspects of modern electronics. Every chip incorporates some form of analog IP, as even digital logic is dependent on analog signals for critical functions. Many digital design engineers are known to be uncomfortable with the prospect of integrating analog components. However, the current… Read More


The RISC-V and Open-Source Functional Verification Challenge

The RISC-V and Open-Source Functional Verification Challenge
by Daniel Nenni on 10-24-2024 at 10:00 am

Semiwiki Blog Post #1 Image #1

Most of the RISC-V action at the end of June was at the RISC-V Summit Europe, but not all. In fact, a group of well-informed and opinionated experts took over the Pavilion stage at the Design Automation Conference to discuss functional verification challenges for RISC-V and open-source IP.

Technology Journalist Ron Wilson and … Read More


Analog Bits Builds a Road to the Future at TSMC OIP

Analog Bits Builds a Road to the Future at TSMC OIP
by Mike Gianfagna on 10-21-2024 at 6:00 am

Analog Bits Builds a Road to the Future at TSMC OIP

The TSMC Open Innovation Platform (OIP) Ecosystem Forum has become the industry benchmark when it comes to showcasing industry-wide collaboration. The extreme design, integration and packaging demands presented by multi-die, chiplet-based design have raised the bar in terms of required collaboration across the entire … Read More


Mobile LLMs Aren’t Just About Technology. Realistic Use Cases Matter

Mobile LLMs Aren’t Just About Technology. Realistic Use Cases Matter
by Bernard Murphy on 10-16-2024 at 6:00 am

chatbot list of suggestions min

Arm has been making noise about running large language models (LLMs) on mobile platforms. At first glance that sounds wildly impractical, other than Arm acting as an intermediary between a phone and a cloud-based LLM. However Arm are partnered with Meta to run Llama 3.2 on-device or in the cloud, apparently seamlessly. Running… Read More