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The Evolution of RISC-V and the Role of Andes Technology in Building a Global Ecosystem

The Evolution of RISC-V and the Role of Andes Technology in Building a Global Ecosystem
by Daniel Nenni on 03-09-2026 at 10:00 am

RISC V Now Andes Conference

During my frequent trips to Taiwan as a foundry relationship professional I remember meeting Frankwell Lin, CEO of Andes, in Taiwan 15+ years ago. As I walked to TSMC HQ from the Hotel Royal (my second home for many years) Andes was about mid point and Frankwell’s door was always open. Sometimes just tea, sometimes technology,… Read More


Keynote: On-Package Chiplet Innovations with UCIe

Keynote: On-Package Chiplet Innovations with UCIe
by Daniel Nenni on 03-08-2026 at 4:00 pm

Chiplet Summit Keynote UCIe 2026

In the rapidly evolving landscape of semiconductor technology, the Universal Chiplet Interconnect Express (UCIe) emerges as a groundbreaking open standard designed to revolutionize on-package chiplet integrations. Presented by Dr. Debendra Das Sharma, Chair of the UCIe Consortium and Intel Senior Fellow, at the ChipletRead More


From Satellites to 5G: Ceva’s PentaG-NTN™ Lowers Barriers for Terminal Innovators

From Satellites to 5G: Ceva’s PentaG-NTN™ Lowers Barriers for Terminal Innovators
by Daniel Nenni on 03-05-2026 at 8:00 am

unnamed (3)

Ceva, Inc., a leading provider of silicon and software IP for the Smart Edge, has unveiled PentaG-NTN™, its groundbreaking 5G Advanced modem IP subsystem tailored for satellite user terminals in Low Earth Orbit (LEO) and Medium Earth Orbit (MEO) constellations. Announced at Mobile World Congress 2026 in Barcelona on March 3,… Read More


RVA23 Ends Speculation’s Monopoly in RISC-V CPUs

RVA23 Ends Speculation’s Monopoly in RISC-V CPUs
by Jonah McLeod on 03-04-2026 at 8:00 am

RVA23 Image

RVA23 marks a turning point in how mainstream CPUs are expected to scale performance. By making the RISC-V Vector Extension (RVV) mandatory, it elevates structured, explicit parallelism to the same architectural status as scalar execution. Vectors are no longer optional accelerators bolted onto speculation-heavy cores.… Read More


Securing RISC-V Third-Party IP: Enabling Comprehensive CWE-Based Assurance Across the Design Supply Chain

Securing RISC-V Third-Party IP: Enabling Comprehensive CWE-Based Assurance Across the Design Supply Chain
by Admin on 03-02-2026 at 10:00 am

RISC V 3PIP CWE Workflow BR 022626

by Jagadish Nayak

RISC-V adoption continues to accelerate across commercial and government microelectronics programs. Whether open-source or commercially licensed, most RISC-V processor cores are integrated as third-party IP (3PIP), potentially introducing supply chain security challenges that demand structured,… Read More


Advancing Automotive Memory: Development of an 8nm 128Mb Embedded STT-MRAM with Sub-ppm Reliability

Advancing Automotive Memory: Development of an 8nm 128Mb Embedded STT-MRAM with Sub-ppm Reliability
by Daniel Nenni on 03-01-2026 at 6:00 pm

World First 8nm 128Mb Embedded STT MRAM for Automotive

The rapid evolution of automotive technology has intensified the demand for highly reliable, high-performance semiconductor memory solutions. Modern vehicles increasingly rely ADAS driving features, and complex infotainment platforms, all of which require memory that can operate flawlessly under extreme environmental… Read More


Memory Matters: Signals from the 2025 NVM Survey

Memory Matters: Signals from the 2025 NVM Survey
by Daniel Nenni on 02-27-2026 at 6:00 am

when do you expect to choose

Non-volatile memory choices are becoming more complex as SoC designs push into advanced nodes, and new requirements driven by AI, new sensor technologies and stringent quality standards.

The second annual 2025 NVM Survey, completed in December, captures a market that still hangs on established technologies but is increasingly… Read More


How Customized Foundation IP Is Redefining Power Efficiency and Semiconductor ROI

How Customized Foundation IP Is Redefining Power Efficiency and Semiconductor ROI
by Kalar Rajendiran on 02-26-2026 at 10:00 am

chip design for blog

As computing expands from data centers to edge devices, semiconductor designers face increasing pressure to optimize both performance and energy efficiency. Advanced process nodes continue to provide transistor-level improvements, but scaling alone cannot meet the demands of hyperscale AI infrastructure or ultra-low-power… Read More


Akeana Partners with Axiomise for Formal Verification of Its Super-Scalar RISC-V Cores

Akeana Partners with Axiomise for Formal Verification of Its Super-Scalar RISC-V Cores
by Daniel Nenni on 02-26-2026 at 8:00 am

Akeana Partners with Axiomise

Akeana Inc. announced a key milestone in the development of its advanced RISC-V technology: a successful partnership with Axiomise Limited to formally verify its super-scalar test chip, Alpine. The collaboration highlights the growing importance of formal verification in ensuring correctness, performance, and efficiency

Read More

Reimagining Compute in the Age of Dispersed Intelligence

Reimagining Compute in the Age of Dispersed Intelligence
by Jonah McLeod on 02-24-2026 at 10:00 am

Yuning(lr) copy

At the 2025 RISC-V Summit, amid debates over cloud scaling and AI cost, DeepComputing CEO Yuning Liang offered a radical view: the future of intelligence isn’t in the cloud at all — it’s already in your pocket. His lunchtime conversation began with iPhones and ended with the death of the operating system. In between, he sketched … Read More