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TSMC Ups CAPEX Again!

TSMC Ups CAPEX Again!
by Daniel Nenni on 04-16-2021 at 6:00 am

TSMC 1Q21 Revenue by Platform

We were all pleasantly surprised when TSMC increased 2021 Capex to a record $28 billion. To me this validated the talk inside the ecosystem that Intel would be coming to TSMC at 3nm. We were again surprised when TSMC announced a $100B investment over the next three years which belittled Intel’s announcement that they would spend … Read More


SPIE 2021 – Applied Materials – DRAM Scaling

SPIE 2021 – Applied Materials – DRAM Scaling
by Scotten Jones on 04-08-2021 at 10:00 am

Slide1

At the SPIE Advanced Lithography Conference in February 2021, Regina Freed of Applied Materials gave a paper: “Module-Level Material Engineering for Continued DRAM Scaling”. Applied Materials provided me with the presentation and was kind enough to set up an interview for me with Regina Freed.

I also spoke to Regina Freed last… Read More


Webinar: Annapurna Labs and Altair Team up for Rapid Chip Design in the Cloud

Webinar: Annapurna Labs and Altair Team up for Rapid Chip Design in the Cloud
by Mike Gianfagna on 04-07-2021 at 6:00 am

Annapurna Labs and Altair Team up for Rapid Chip Design in the Cloud

This is a story of strategic recursion. Yes, a fancy term. I just made up. If you’re not into algorithm development you can Google recursion, but the simple explanation is we’re talking about using the cloud to design the cloud. The story begins with Annapurna Labs, a fabless chip company focused on bringing innovation to cloud infrastructure,… Read More


AUGER, the First User Group Meeting for Agnisys

AUGER, the First User Group Meeting for Agnisys
by Daniel Nenni on 04-01-2021 at 10:00 am

website banner with date 1

As a long-time member of the EDA community, I really believe in user groups. EDA tools are complicated beasts, with many options and different ways to use them, and they are constantly evolving. Users interact with their local field applications engineers (FAEs) and sometimes corporate AEs (product specialists) as well on a regular… Read More


WEBINAR: Pulsic’s Animate Makes Automated Analog Layout a Reality

WEBINAR: Pulsic’s Animate Makes Automated Analog Layout a Reality
by Tom Simon on 03-30-2021 at 10:00 am

Pulsic Webinar

Many years ago, digital and analog design flows diverged, with digital design benefiting from increasing levels of automation and more importantly separation between the front-end design process and the back-end design process. While digital design still requires linkages between the front and back end, they are well defined… Read More


Webinar: Rapid Exploration of Advanced Materials (for Ferroelectric Memory)

Webinar: Rapid Exploration of Advanced Materials (for Ferroelectric Memory)
by Tom Dillinger on 03-30-2021 at 6:00 am

polarization

There are many unsung heroes in our industry – companies that provide unique services and expertise that enable the rapid advances in fabrication process development that we’ve come to rely upon.  Some of these companies offer “back-end” services, assisting semiconductor fabs with yield diagnostic engineering and failure… Read More


Upcoming Webinar on Resistive RAM (ReRAM) Technology

Upcoming Webinar on Resistive RAM (ReRAM) Technology
by Kalar Rajendiran on 03-21-2021 at 10:00 am

eMemory RRAM Webinar Semiwiki

On-chip memory (embedded memory) makes computing applications run faster. In the early days of the semiconductor industry, the desire to utilize large amount of on-chip memory was limited by cost, manufacturing difficulties and technology mismatches between logic and memory circuit implementations. Since then, advancements… Read More


Resistive RAM (ReRAM) Computing-in-Memory IP Macro for Machine Learning

Resistive RAM (ReRAM) Computing-in-Memory IP Macro for Machine Learning
by Tom Dillinger on 03-18-2021 at 6:00 am

testsite

The term von Neumann bottleneck is used to denote the issue with the efficiency of the architecture that separates computational resources from data memory.   The transfer of data from memory to the CPU contributes substantially to the latency, and dissipates a significant percentage of the overall energy associated with … Read More


SPIE 2021 – ASML DUV and EUV Updates

SPIE 2021 – ASML DUV and EUV Updates
by Scotten Jones on 03-17-2021 at 10:00 am

SPIE DUV 2021 ASML NXT4 DryWet Presentation final noWPD2 Page 42

At the SPIE Advanced Lithography Conference held in February, ASML presented the latest information on their Deep Ultraviolet (DUV) and Extreme Ultraviolet (EUV) exposure systems. I recently got to interview Mike Lercel of ASML to discuss the presentations.

DUV

Despite all the attention EUV is getting, most layers are still… Read More


All-Digital In-Memory Computing

All-Digital In-Memory Computing
by Tom Dillinger on 03-15-2021 at 6:00 am

NOR gate

Research pursuing in-memory computing architectures is extremely active.  At the recent International Solid State Circuits conference (ISSCC 2021), multiple technical sessions were dedicated to novel memory array technologies to support the computational demand of machine learning algorithms.

The inefficiencies associated… Read More