Semiwiki Ansys SimWorld
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Webinar: Hyperscale SoC Validation with Cloud-based Hardware Simulation Framework

Webinar: Hyperscale SoC Validation with Cloud-based Hardware Simulation Framework
by Daniel Nenni on 06-05-2020 at 6:00 am

Slide1

S2C has been developing FPGA prototyping platforms since 2003, and, over time, their FPGA prototyping platforms have supported increasingly larger more sophisticated FPGA prototyping projects with three key attributes; 1) scalable prototyping gate capacities, 2) a high-speed interface between the FPGA prototype and software… Read More


Free Webinar on Verifying On-Chip ESD Protection

Free Webinar on Verifying On-Chip ESD Protection
by Tom Simon on 06-03-2020 at 6:00 am

Promo Ad 400x400 1

Walking across a carpet can generate up to 35,000 volts of static charge, which is tens of thousands of times higher than the operating voltages of most integrated circuits. When charge build up from static electricity is exposed to the pins of an IC, the electrostatic discharge (ESD) protection network on the chip is intended to… Read More


The Largest Engineering Simulation Virtual Event in the World!

The Largest Engineering Simulation Virtual Event in the World!
by Daniel Nenni on 05-22-2020 at 10:00 am

ANSYS Simulation World

ANSYS is the world leader in engineering simulation across multiple markets. One of those markets just happens to be semiconductor which is why ANSYS is on SemiWiki.com. Due to the pandemic ANSYS has transformed their popular live regional events to one broad virtual event “Simulation World”.

“Simulation World is world’s largestRead More


Atos Crafts NoC, Pad Ring, More Using Defacto

Atos Crafts NoC, Pad Ring, More Using Defacto
by Bernard Murphy on 05-21-2020 at 6:00 am

Mont Blanc

I’ve talked before about how Defacto provides a platform for scripted RTL assembly. Kind of a rethink of the IP-XACT concept but without need to get into XML (it works directly with SV), and with a more relaxed approach in which you decide what you want to automate and how you want to script it.

They’re hosting a webinar on May 28th 10-11am… Read More


WEBINAR: Moving UVM Verification Up To The Next Level

WEBINAR: Moving UVM Verification Up To The Next Level
by Daniel Nenni on 05-15-2020 at 9:00 am

PSS

Tom Fitzpatrick, a Strategic Verification Architect at Mentor, a Siemens Business, has worked on IEEE and Accellera standards like Verilog 1364, System Verilog 1800, UVM 1800.2 and is Vice Chair of the Portable Stimulus working group, so when I heard that he was doing a webinar on how PSS can be used to create better stimulus for … Read More


SEMI Takes the Jim Hogan and Simon Butler Conversation Virtual

SEMI Takes the Jim Hogan and Simon Butler Conversation Virtual
by Mike Gianfagna on 05-13-2020 at 10:00 am

Jim Simon

As I originally reported a few weeks ago, the Jim Hogan fireside chat with Methodic’s CEO and founder Simon Butler was moved to a virtual event on May 1. The event was produced by the Electronic System Design (ESD) Alliance, a SEMI Strategic Technology Community. Bob Smith, executive director of ESDA, moderated the event. I am happy… Read More


How to Modify, Release and Update IP in 30 Minutes or Less

How to Modify, Release and Update IP in 30 Minutes or Less
by Mike Gianfagna on 05-08-2020 at 6:00 am

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I had the opportunity to attend a ClioSoft webinar recently on the topic of IP traceability. ClioSoft provides a broad range of tools for design data management and IP reuse. Entitled The New Trend in IP Traceability that IP Developers and Design Managers Rely On, the webinar was presented by Karim Khalfan, director of applications… Read More


Webinar: Build Your Next HBM2/2E Chip with SiFive

Webinar: Build Your Next HBM2/2E Chip with SiFive
by Mike Gianfagna on 05-04-2020 at 10:00 am

Screen Shot 2020 05 03 at 12.09.58 PM

I have been watching the trend for quite some time now that many advanced FinFET designs today are actually 2.5D systems in package. All of these 2.5D silicon interposer-based designs have high-bandwidth memory (HBM) stacks on board.  Often there are multiple memory stacks in both 4-high and 8-high configurations. If you follow… Read More


SiFive’s Approach to Embedding Intelligence Everywhere

SiFive’s Approach to Embedding Intelligence Everywhere
by Tom Simon on 04-27-2020 at 6:00 am

SiFive Embedding Intelligence

Before the advent of RISC-V, designers looking for embedded processors were effectively limited to a handful of proprietary processors using ISAs from decades ago. While the major ISAs are being updated and enhanced, they also are facing limitations from many decisions made over many years.  RISC-V was conceived with a clean… Read More


Using ML Acceleration Hardware for Improved DSP Performance

Using ML Acceleration Hardware for Improved DSP Performance
by Tom Simon on 04-24-2020 at 6:00 am

nnMAX Flex Logix Tile

Some amazing hardware is being designed to accelerate AI/ML, most of which features large numbers of MAC units. Given that MAC units are like the lego blocks of digital math, they are also useful for a number of other applications. System designers are waking up to the idea of repurposing AI accelerators for DSP functions such as … Read More