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If the thought of a silicon respin keeps you awake at night, you’re not alone. Re-fabricating a chip can cost tens of millions of dollars. An unplanned respin also risks a delay in getting a product to market, which adds tremendous costs in terms of lost business.
Undoubtedly, adding to your sleep loss is the recent rise in respins.… Read More
Unlock the full potential of your semiconductor designs with Primarius’ cutting-edge solutions, designed to enhance accuracy, performance, and efficiency across various applications. Join us for a series of four exclusive webinars where we will dive deep into how our advanced tools can revolutionize workflows for… Read More
Even though this is the 16th OIP event please remember that TSMC has been working closely with EDA and IP companies for 20+ years with reference flows and other design enablement and silicon verification activities. The father of OIP officially is Dr. Morris Chang who named it the Grand Alliance. However, Dr. Cliff Hou is the one … Read More
The 2024 live conferences have been well attended thus far and there are many more to come. The next big event in Silicon Valley is the TSMC Global OIP Ecosystem Forum on September 25th at the Santa Clara Convention Center. I expect a big crowd filled with both customers and partners.
This is the 16th year of OIP and it has been an honor… Read More
You don’t know you’re at a peak until you start to descend, and Hot Chips 2024 is proof that AI hype is still climbing among semiconductor vendors. Juggernaut Nvidia, startups, hyperscalers, and major companies presented their AI accelerators (GPUs and neural-processing units—NPUs) and touched on the challenges of software,… Read More
If you think my 40 years of semiconductor experience is impressive, Malcolm Penn has been at it for 55 years starting with the first commercial integrated circuit. Malcolm’s company Future Horizons has been providing legendary semiconductor industry forecasts since 1989. I have attended dozens of these both live and … Read More
The semiconductor industry is undergoing an unprecedented inflection—not in its technology, but in its very structure. This transformation is happening at a time of phenomenal growth, presenting both opportunity and crisis. The ingredient most critical to meeting the growth demands, but which also poses the greatest risk,… Read More
Entering the exhibit area of DAC on the first floor I was immediately faced with the Keysight EDA booth, and it was even larger than either the Synopsys or Cadence booths. They had a complete schedule of partners presenting in their theatre that included: Microsoft Azure, Riscure, Fermi Labs, BAE Systems, Alphawave, Intel Foundry,… Read More
Analog IC layout is a demanding endeavor as it entails conforming to complex layout design rules, interpreting design intentions from the schematics and understanding arcane topics like transistor matching, noise tolerance, parasitics and latch up. These skills are often handed down from one generation to the next, one on … Read More
Analog Bits is aggressively moving to advanced nodes. On SemiWiki, Dan Nenni covered new IP in 3nm at DAC here. I covered the new Analog Bits 3nm IP presented at the TSMC Technology Symposium here. And now, there’s buzz about 2nm IP to be announced at the upcoming TSMC OIP event in September. I was able to get a briefing from the master… Read More
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TSMC 16th OIP Ecosystem Forum First Thoughts