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ESD Alliance Executive Outlook Features View of How Multi-Physics is Reshaping Chip Design and EDA Tools

ESD Alliance Executive Outlook Features View of How Multi-Physics is Reshaping Chip Design and EDA Tools
by Bob Smith on 04-24-2025 at 6:00 am

CEO Outlook #2 (1)

Every spring, the ESD Alliance, a SEMI Technology Community, organizes a get together where industry executives and experts gather to network and talk about trends in the electronic design automation industry.

The theme of this year’s event, once again co-hosted by Keysight, is “How Multi-Physics is Reshaping Chip Design and… Read More


TSMC Brings Packaging Center Stage with Silicon

TSMC Brings Packaging Center Stage with Silicon
by Mike Gianfagna on 04-23-2025 at 11:45 am

TSMC Brings Packaging Center Stage with Silicon

The worldwide TSMC 2025 Technology Symposium recently kicked off with the first event in Santa Clara, California. These events typically focus on TSMC’s process technology and vast ecosystem. These items were certainly a focus for this year’s event as well. But there is now an additional item that shares the spotlight – packaging… Read More


TSMC 2025 Technical Symposium Briefing

TSMC 2025 Technical Symposium Briefing
by Daniel Nenni on 04-23-2025 at 11:40 am

TSMC Advanced Tecnology RoadMap 2025 SemiWiki

At the pre-conference briefing, Dr. Kevin Zhang gave quite a few of us media types an overview of what will be highlighted at the 2025 TSMC Technical Symposium here in Silicon Valley. Since most of the semiconductor media are not local this was a very nice thing to do. I will be at the conference and will write more tomorrow after the … Read More


Andes RISC-V CON in Silicon Valley Overview

Andes RISC-V CON in Silicon Valley Overview
by Daniel Nenni on 04-18-2025 at 6:00 am

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RISC-V conferences have been at full capacity and I expect this one will be well attended as well. Andes is the biggest name in RSIC-V. The most notable thing about RISC-V conferences is the content. Not only is the content deep, it is international from the top companies in the industry. It is hard to find a design win these days without… Read More


Achieving Seamless 1.6 Tbps Interoperability for High BW HPC AI/ML SoCs: A Technical Webinar with Samtec and Synopsys

Achieving Seamless 1.6 Tbps Interoperability for High BW HPC AI/ML SoCs: A Technical Webinar with Samtec and Synopsys
by Daniel Nenni on 04-17-2025 at 10:00 am

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HPC Bandwidth Explosion and 1.6T Ecosystem Interop Need

The exponential growth in data bandwidth requirements driven by HPC systems, AI, and ML applications has set the stage for an ever-increasing need for 1.6Tbps Ethernet. As data centers strive to manage vast data transfers with maximum efficiency, the urgency for interoperability… Read More


SNUG 2025: A Watershed Moment for EDA – Part 1

SNUG 2025: A Watershed Moment for EDA – Part 1
by Lauro Rizzatti on 04-15-2025 at 6:00 am

SNUG 2025 A Watershed Moment for EDA Figure 1

Hot on the heels of DVConUS 2025, the 35th annual Synopsys User Group (SNUG) Conference made its mark as a defining moment in the evolution of Synopsys—and the broader electronic design automation (EDA) industry. This year’s milestone event not only underscored Synopsys’ continued innovation but also affirmed the vision… Read More


Synopsys Webinar: The Importance of Security in Multi-Die Designs – Navigating the Complex Landscape

Synopsys Webinar: The Importance of Security in Multi-Die Designs – Navigating the Complex Landscape
by Daniel Nenni on 04-11-2025 at 6:00 am

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In today’s rapidly evolving digital landscape, the security of electronic systems is of the highest priority. This importance is underscored by technological advancements and increasing regulatory demands. Multi-die designs which integrate multiple dies (also called chiplets) into a single package, introduce … Read More


A Synopsys Webinar Detailing IP Requirements for Advanced AI Chips

A Synopsys Webinar Detailing IP Requirements for Advanced AI Chips
by Mike Gianfagna on 04-03-2025 at 10:00 am

A Synopsys Webinar Detailing IP Requirements for Advanced AI Chips

Generative AI is dramatically changing the compute power that must be delivered by advanced designs. This demand has risen by more than 10,000 times in the past five to six years.  This increased demand has impacted the entire SoC design flow. We are now faced with going beyond 1 trillion transistors per chip, and systems now consist… Read More


Webinar: RF board design flow examples for co-simulating active circuits

Webinar: RF board design flow examples for co-simulating active circuits
by Don Dingee on 03-25-2025 at 10:00 am

Mesh domain optimization

In part one of this webinar series, Keysight and Modelithics looked at the use of 3D passive vendor component models supporting highly accurate, automated 3D EM-circuit co-simulation of high-frequency RF board designs. Part two continues the exploration of RF board design flows for simulating active circuits on boards, again… Read More


DVCon 2025: AI and the Future of Verification Take Center Stage

DVCon 2025: AI and the Future of Verification Take Center Stage
by Lauro Rizzatti on 03-06-2025 at 10:00 am

DVCon 2025

The 2025 Design and Verification Conference (DVCon) was a four-day event packed with insightful discussions, cutting-edge technology showcases, and thought-provoking debates. The conference agenda included a rich mix of tutorial sessions, a keynote presentation, a panel discussion, and an exhibit hall with Electronic… Read More