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WP_Term Object
(
    [term_id] => 50
    [name] => Events
    [slug] => events
    [term_group] => 0
    [term_taxonomy_id] => 50
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 881
    [filter] => raw
    [cat_ID] => 50
    [category_count] => 881
    [category_description] => 
    [cat_name] => Events
    [category_nicename] => events
    [category_parent] => 0
    [is_post] => 
)

WEBINAR: 5 Reasons Why a High Performance Reconfigurable SmartNIC Demands a 2D NoC

WEBINAR: 5 Reasons Why a High Performance Reconfigurable SmartNIC Demands a 2D NoC
by Mike Gianfagna on 06-10-2021 at 6:00 am

WEBINAR 5 Reasons Why a High Performance Reconfigurable SmartNIC Demands a 2D NoC

If you are involved in designing systems that process data, you’re going to want to attend this webinar. Practically speaking, this should include a large percentage of the SemiWiki readership. Since data is the new oil there are a lot of applications drawn to data and information processing. Before we explore this webinar, let’s… Read More


Silicon Catalyst is Bringing Its Unique Startup Platform to the UK

Silicon Catalyst is Bringing Its Unique Startup Platform to the UK
by Mike Gianfagna on 06-08-2021 at 10:00 am

Silicon Catalyst is Bringing Its Unique Startup Platform to the UK

Silicon Catalyst is a unique startup incubator / accelerator that focuses exclusively on accelerating solutions in silicon (including chips, IP, MEMS & sensors). The organization has an extensive support infrastructure that includes preferred access to IP, design tools, business infrastructure and fab/assembly. … Read More


WEBINAR: Using Design Porting as a Method to Access Foundry Capacity

WEBINAR: Using Design Porting as a Method to Access Foundry Capacity
by Tom Simon on 06-08-2021 at 6:00 am

Schematic Porting the NanoBeacon

There have always been good reasons to port designs to new foundries or processes. These reasons have included reusing IP in new projects, moving an entire design to a smaller node to improve PPA, or second sourcing manufacturing. While there can be many potential business motivations for any of the above, in today’s environment… Read More


Analog Sensing Now Essential for Boosting SOC Performance

Analog Sensing Now Essential for Boosting SOC Performance
by Tom Simon on 06-03-2021 at 6:00 am

analog sensing

In today’s System-on-Chip (SOC), analog blocks are used in many places such as I/O cells for communication, PLLs for generating clocks, LDO’s for converting supply voltage to internal rail voltage, Sensors for qualifying external characteristics such as temperature, light, motion, etc. However new advanced designs now require… Read More


TSMC 2021 Technical Symposium Actions Speak Louder Than Words

TSMC 2021 Technical Symposium Actions Speak Louder Than Words
by Daniel Nenni on 06-01-2021 at 1:00 pm

TSMC Symposium 2021

The TSMC Symposium kicked of today. I will share my general thoughts while Tom Dillinger will do deep dives on the technology side. The event started with a keynote by TSMC CEO CC Wei followed by technology presentations by the TSMC executive staff.

C.C. Wei introduced a new sound bite this year that really resonated with me and that… Read More


Upcoming Webinar: PUFiot, A NeoPUF-based Secure Co-Processor

Upcoming Webinar: PUFiot, A NeoPUF-based Secure Co-Processor
by Kalar Rajendiran on 05-30-2021 at 10:00 am

PUFiot Applications

Throughout history, people have sought after security as a basic right and expectation within a civilized society. Even as recent as a few centuries ago, things were very simple. Subjects looked to their rulers to provide security for their lives and assets. Assets were mostly hard assets such as jewelry, coins or real estate. … Read More


Machine Learning Applied to Increase Fab Yield

Machine Learning Applied to Increase Fab Yield
by Tom Dillinger on 05-25-2021 at 8:00 am

enhanced defect images

Machine learning applications have become pervasive and increasingly complex, from recommendation agents in online interactions to personal assistants for command response to (ultimately) autonomous vehicle control.  Yet, an often overlooked facet of machine learning technology is the deployment in industrial process… Read More


WEBINAR: What Makes SoC Compiler The Shortest Path from SoC Design Specification to Logic Synthesis?

WEBINAR: What Makes SoC Compiler The Shortest Path from SoC Design Specification to Logic Synthesis?
by Daniel Nenni on 05-24-2021 at 6:00 am

SoC compiler puzzle

Defacto SoC Compiler whose 9.0 release was announced recently automates the SoC design creation from the first project specifications. It covers register handling, IP and connectivity insertion at RTL, UPF and SDC file generation right to logic synthesis. As part of the generation process of RTL and design collaterals, basic… Read More


Chip Design in the Cloud – Annapurna Labs and Altair

Chip Design in the Cloud – Annapurna Labs and Altair
by Kalar Rajendiran on 05-19-2021 at 10:00 am

Compute Farm Growth

The above title refers to a webinar that was hosted by Altair on April 28th. Chip design in the cloud is not a new idea. So, what is the big deal with the above title. Sometimes titles don’t reveal the full story. Annapurna Labs happens to be an Amazon company. It used to be an independent semiconductor company that was acquired by Amazon… Read More


Extending Moore’s Law with 3D Heterogeneous Materials Integration

Extending Moore’s Law with 3D Heterogeneous Materials Integration
by Tom Dillinger on 05-18-2021 at 10:00 am

nFET Si pFET Ge

A great deal has been written of late about the demise of Moore’s Law.  The increase in field-effect transistor density with successive process nodes has slowed from the 2X every 2 1/2 years pace of earlier generations.  The economic nature of Moore’s comments 50 years ago has also been scrutinized – the reduction in cost per transistorRead More