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Achronix is known for its high-performance FPGA solutions. In this post, I’ll explore the Speedster7T FPGA. This FPGA family is optimized for high-bandwidth workloads and eliminates performance bottlenecks with an innovative architecture. Built on TSMC’s 7nm FinFET process, the family delivers ASIC-level performance … Read More
Anyone who has read my previous articles about IEDM knows I consider it the premier conference on process technology.
Last year due to COVID IEDM was virtual and although virtual offers some advantages the hallway conversations that can be such an important part of the conference are lost. This year IEDM is returning as a live event… Read More
We all know that project planning and tracking are critical for any complex undertaking, especially a complex SoC design project. We also know that IP management is critical for these same kinds of projects – there is lots of IP from many sources being integrated in any SoC these days. If you don’t keep track of what you’re using and… Read More
I have attended several past Synopsys verification events which I remember as engineering conference room, all-engineer pitches and debates. Effective but aiming for content rather than polish. This year’s event was different. First it was virtual, like most events these days, which certainly made the whole event feel more… Read More
During his keynote address at the CadenceLIVE 2021 conference, CEO Lip-Bu Tan made some market trend comments. He observed that most of the data nowadays is generated at the edge but only 20% is processed there. He predicted that by 2030, 80% of data is expected to be processed at the edge. And most of this 80% will be processed on edge… Read More
The subject of this webinar is focused on the new COM-HPC standard from PICMG, a nonprofit consortium of companies and organizations that collaboratively develop open standards for high performance telecommunications, military, industrial, and general-purpose embedded computing applications. A computer-on-module … Read More
My career started out by designing DRAM circuits at Intel, and we manually sized every transistor in the entire design to get the optimum performance, power and area. Yes, it was time consuming, required lots of SPICE iterations and was a bit error prone. Thank goodness that times have changed, and circuit designers can work smarter… Read More
Originally containing a handful of commands to help with common layout tasks, SkillCAD has evolved into the industry standard for analog, RF and mixed signal design for customers using Cadence Virtuoso. With over 85 customers worldwide and over 120 functions including the powerful, patented V-editor, metal routing and pin… Read More
The GF Technology Summit was last week. It was virtual again this year but with a different format. It was a mix of live and recorded events which did include some cringe worthy moments but all-in-all it was well worth my time.
One of the biggest changes you will notice is the messaging. GF is no longer down in the technology trenches … Read More
I’ve attended the DAC conference and trade show since the late 1980s, and every visit has been a continuing learning experience about the EDA, IP and semiconductor industry. I first started attended as an EDA vendor in 1987, and since 2004 as a freelance marketing professional. There’s a significant amount of preparation… Read More
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Its all about the Transistors- 57 Billion reasons why Apple/TSMC are crushing it