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eFPGA – What a great idea! But I have no idea how I’d use it!

eFPGA – What a great idea! But I have no idea how I’d use it!
by Daniel Nenni on 08-05-2019 at 10:00 am

eFPGA stands for embedded Field Programmable Grid Arrays.  An eFPGA is a programmable device like an FPGA but rather than being sold as a completed chip it is licensed as a semiconductor IP block. ASIC designers can license this IP and embed it into their own chips adding the flexibility of programmability at an incremental cost.… Read More


GPU-Powered SPICE – Understanding the Cost

GPU-Powered SPICE – Understanding the Cost
by Daniel Nenni on 08-01-2019 at 10:00 am

To deploy a GPU-based SPICE solution, you need to understand the costs involved. To get your hands on this new report analyzing this specific issue, all you need to do is attend Empyrean’s upcoming webinar, “GPU-Powered SPICE:  The Way Forward for Analog Simulation,” which will be held on Thursday, August 8, 2019, at 10:00 am (PDT).… Read More


56th DAC – In Depth Look at Analog IP Migration from MunEDA

56th DAC – In Depth Look at Analog IP Migration from MunEDA
by Tom Simon on 07-31-2019 at 10:00 am

Every year at DAC, in addition to the hubbub of the exhibit floor and the relatively short technical sessions, there are a number of tutorials that dive in depth into interesting topics. At the 56th DAC in Las Vegas this year, MunEDA offered an interesting tutorial on Analog IP migration and optimization. This is a key issue for large… Read More


Semicon West 2019 – Day 3 – Global Foundries

Semicon West 2019 – Day 3 – Global Foundries
by Scotten Jones on 07-30-2019 at 10:00 am

On Wednesday, July 10th I got to sit down with Gary Patton, CTO and SVP of worldwide research and development of Global Foundries and get an update on how the company is doing.

We started with a discussion of Global Foundries (GF) general business health. Revenue for the year is expected to be around $6 billion dollars. They are focused… Read More


Taking the pain out of UVM

Taking the pain out of UVM
by Daniel Nenni on 07-29-2019 at 5:00 am

If you are interested in gaining a deeper understanding of the many ways you can leverage the Universal Verification Methodology (UVM), Breker Verification Systems has gone to a lot of effort to put that information at your fingertips.

A technical subcommittee of Accellera voted to establish the UVM in December 2009. UVM was based… Read More


SiFive Fosters RISC-V Collaboration and Education in India and Bangladesh Via Symposiums, Tutorials and Workshops

SiFive Fosters RISC-V Collaboration and Education in India and Bangladesh Via Symposiums, Tutorials and Workshops
by Swamy Irrinki on 07-27-2019 at 4:00 am

Last year we hosted several SiFive Tech Symposiums in India to help promulgate the RISC-V ecosystem in the region. The enthusiastic reception from those in industry as well as students and faculty at India’s most esteemed universities was inspiring. This July and August, we’re bringing the SiFive Tech Symposium back to India,… Read More


SemiWiki Webinar Series: Who Wants to do a Webinar?

SemiWiki Webinar Series: Who Wants to do a Webinar?
by Daniel Nenni on 07-26-2019 at 10:00 am

Webinars have been a popular form of communication since even before SemiWiki existed and they are a mainstay in today’s fast-moving semiconductor ecosystem.

In the past, SemiWiki has assisted with more than a hundred webinars. Today SemiWiki can do a complete webinar from start to finish using the GotoWebinar software. SemiWiki… Read More


The Wild, Wild SEMICON West TechTALK – Joe Costello Speaks Out

The Wild, Wild SEMICON West TechTALK – Joe Costello Speaks Out
by Randy Smith on 07-25-2019 at 10:00 am

On July 9, 2019, I attended the TechTALK session hosted by Dave Kelf of Breker Systems, Inc. titled, “Applied AI in Design-to-Manufacturing.” I was happy to hear what Dave had put together for this since it is a topic I am keenly interested in and because I have known Dave personally through music and charitable activities we have … Read More


#DAC56 – Optimizing Verification Throughput for Advanced Designs in a Connected World

#DAC56 – Optimizing Verification Throughput for Advanced Designs in a Connected World
by Daniel Payne on 07-24-2019 at 10:00 am

It was the final day of DAC56 and my head was already spinning from information overload after meeting so many people and hearing so many presentations, but I knew that IC functional verification was a huge topic and looming bottleneck for many SoC design teams, so I made a last-minute email request to attend a luncheon panel discussion… Read More


The Flash and the Taiwan ESD Seminar!

The Flash and the Taiwan ESD Seminar!
by Daniel Nenni on 07-24-2019 at 6:00 am

During my trip through Asia last week I attended the Taiwan ESD Workshop. Hsinchu is densely populated with some of the smartest semiconductor people in the world so it is well worth the trip, absolutely.  As it turns out ESD is one of the top concerns in semiconductor design and manufacture. The current rule based and simulation … Read More