Contrary to the popular press, ASML High-NA EUV is not ready for logic production yet—and it may never be, at least not in the form originally envisioned. If you remember how long it took conventional EUV to become production-worthy—arguably 5–10 years—this should not come as a surprise. More importantly, this is no longer just a technical decision. It is now a value proposition decision.
As things stand today, the answer appears to be no: the benefits of High-NA EUV do not justify the cost and risk at 1.4nm.
One of the biggest industry shifts is that foundry customers now have a stronger voice in process technology decisions, and you can thank TSMC for that. TSMC’s collaborative business model gives major customers direct input on manufacturing roadmaps. The top TSMC customers I have spoken with are not ready to embrace High-NA EUV given the current economics and manufacturing risks.
TSMC has said as much publicly during the last two Technology Symposiums. In briefings at both the 2025 Symposium and last month’s event, Dr. Kevin Zhang, Senior Vice President and Deputy Co-COO, made it clear that High-NA EUV is simply too expensive relative to the expected benefit.
Intel had planned to introduce High-NA EUV at the 14A node under former CEO Pat Gelsinger. That was a classic IDM-style decision made largely without customer feedback. Under Lip-Bu Tan, however, customers are expected to have far greater influence over technology choices—which likely means Intel will move closer to the TSMC customer-first model. Samsung may not have much choice either. Foundry customers have spoken.
To be clear, ASML’s High-NA EUV technology works. The question is not technical feasibility. The real question is whether it can achieve the yield, uptime, and economics required for profitable high-volume manufacturing.
The core technical challenge is that High-NA EUV dramatically reduces process margins. Standard EUV tools operate at a numerical aperture (NA) of 0.33, while High-NA increases this to 0.55. The higher NA improves resolution and enables smaller transistor features, but it also significantly reduces depth of focus. In practical terms, wafers must remain almost perfectly flat during exposure. Even tiny variations in wafer topography, thermal distortion, or vibration can create pattern defects that reduce yield.
Photoresists are another major obstacle. High-NA systems require thinner resist films because thicker films exceed the narrow focus window. However, thinner resists absorb fewer EUV photons, increasing stochastic defects such as broken lines, missing holes, and edge roughness. These defects occur randomly and are extremely difficult to eliminate through standard process optimization. At advanced nodes, even a very small number of stochastic defects can make chips unusable.
EUV also faces a fundamental photon problem. Unlike deep ultraviolet lithography, EUV operates with relatively low photon counts. At High-NA dimensions, statistical fluctuations in photon absorption become significant enough to impact pattern fidelity. Electron blur following photon absorption further reduces precision. As the industry approaches the angstrom era, these random physical effects become increasingly difficult to control.
Mask technology introduces another layer of complexity. High-NA EUV uses anamorphic optics, meaning image scaling differs between horizontal and vertical directions. This requires entirely new mask architectures and correction algorithms. EUV masks are already among the most complex manufactured objects in the semiconductor industry, and High-NA masks push defect tolerances even further. Some defects are only visible under EUV illumination, making inspection extraordinarily difficult.
Pellicles remain another unresolved issue. These thin protective membranes shield masks from contamination, but High-NA systems require much higher source power levels, creating severe thermal stress. Existing pellicle materials can warp or degrade under sustained exposure. New materials are under development, but they are not yet fully qualified for continuous high-volume manufacturing.
Throughput and uptime are equally critical. Semiconductor fabs depend on extremely high utilization rates because downtime directly impacts profitability. High-NA tools are still early-generation systems and have not demonstrated the long-term reliability of mature EUV platforms. Even relatively small interruptions can create major economic consequences in leading-edge fabs operating 24/7.
Cost may ultimately be the largest barrier of all. Each High-NA EUV scanner costs approximately $350 million to $400 million, making it the most expensive manufacturing tool ever built. Beyond the scanner itself, fabs require major infrastructure upgrades involving power delivery, cooling, vibration isolation, and cleanroom redesign. The total investment required for High-NA production is enormous, and foundries must determine whether the incremental scaling benefits justify the expense.
TSMC appears to have already made that calculation. Rather than rushing into High-NA deployment, the company is extending existing 0.33 NA EUV systems through multipatterning and process optimization. That decision reflects concerns not only about technical maturity, but also about economic return.
The broader ecosystem is another issue. Lithography does not operate in isolation. Etch, deposition, metrology, inspection, design software, packaging, and yield-learning infrastructure must all evolve together. High-NA EUV introduces new interactions throughout the manufacturing flow, meaning the entire semiconductor ecosystem must mature before stable high-volume yields become realistic.
Bottom line: High-NA EUV is stuck in the difficult transition between laboratory success and industrial maturity. The technology has clearly demonstrated capability in research environments and pilot production, but successful semiconductor manufacturing requires much more than technical proof points. Yield stability, uptime, defect reduction, ecosystem readiness, infrastructure investment, and economic viability must all improve before High-NA EUV can become mainstream production technology.
Also Read:
Beyond Moore’s Law: High NA EUV Lithography Redefines Advanced Chip Manufacturing
Accelerating Computational Lithography Using Massively Parallel GPU Rasterizer
TSMC Process Simplification for Advanced Nodes
Share this post via:
Crossing the Yield Cliff: IDP V6 and the Future of Manufacturing Forecasting