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The Complexities of the Resolution Limits of Advanced Lithography

The Complexities of the Resolution Limits of Advanced Lithography
by Fred Chen on 01-10-2021 at 6:00 am

The Complexities of the Resolution Limits of Advanced Lithography

For advanced lithography used to shrink semiconductor device features according to Moore’s Law, resolution limits are an obvious consideration. It is often perceived that the resolution limit is simply derived from a well-defined equation, but nothing can be further from the truth.

Optical Lithography: the fine print

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Advanced Process Development is Much More than just Litho

Advanced Process Development is Much More than just Litho
by Tom Dillinger on 12-16-2020 at 10:00 am

Vt distribution

The vast majority of the attention given to the introduction of each new advanced process node focuses on lithographic updates.  The common metrics quoted are the transistors per mm**2 or the (high-density) SRAM bit cell area.  Alternatively, detailed decomposition analysis may be applied using transmission electron microscopy… Read More


How Line Cuts Became Necessarily Separate Steps in Lithography

How Line Cuts Became Necessarily Separate Steps in Lithography
by Fred Chen on 12-08-2020 at 10:00 am

How Line Cuts Became Necessarily Separate Steps in Lithography

Pretty much all the semiconductor nodes in the last two decades have had at least one layer where the minimum pitch pushes the limitation of the state-of-the-art lithography tool, with a k1 factor < 0.5, i.e., the half-pitch is less than 0.5*wavelength/numerical aperture. A number of published reports [1-4] have touched upon… Read More


Applied Materials Will Regain Semiconductor Equipment Lead From ASML in 2020

Applied Materials Will Regain Semiconductor Equipment Lead From ASML in 2020
by Robert Castellano on 11-29-2020 at 10:00 am

2020 WFE Share

On December 2, 2019, I posted a SemiWiki article entitled “ASML Will Take Semiconductor Equipment Lead from Applied Materials in 2019.”Since losing its dominance for the first time since 1990 in 2019, Applied Materials is poised to lose its retake the 2020 lead in the semiconductor equipment market. ASML led the… Read More


CD-Pitch Combinations Disfavored by EUV Stochastics

CD-Pitch Combinations Disfavored by EUV Stochastics
by Fred Chen on 11-29-2020 at 6:00 am

CD Pitch Combinations Disfavored by EUV Stochastics

Ongoing investigations of EUV stochastics [1-3] have allowed us to map combinations of critical dimension (CD) and pitch which are expected to pose a severe risk of stochastic defects impacting the use of EUV lithography. Figure 1 shows a typical set of contours of fixed PNOK (i.e., the probability of a feature being Not OK due… Read More


Impact of Defocus and Illumination on Imaging of Pitch

Impact of Defocus and Illumination on Imaging of Pitch
by Fred Chen on 10-26-2020 at 10:00 am

Impact of Defocus

In an earlier article [1], the resolution limit for the space between paired features was described by the Rayleigh criterion of ~0.6 wavelength/numerical aperture, where the numerical aperture (NA) represented the sine of the largest angle for a ray focused from the lens to a point. It is also given by the radius of the lens divided… Read More


Toshiba Cost Model for 3D NAND

Toshiba Cost Model for 3D NAND
by Fred Chen on 10-11-2020 at 8:00 am

Toshiba Cost Model for 3D NAND

Toshiba (now known as Kioxia) was the first company to propose a 3D stacked version of NAND Flash memory called BICS [1]. BICS (BICost Scalable) Flash used explicit process cost reduction based on depositing and etching multiple layers at once, avoiding multiple lithography steps. This strategy replaced the usual approach… Read More


Smartphone Processor Trends and​ Process Differences down through 7nm

Smartphone Processor Trends and​ Process Differences down through 7nm
by Fred Chen on 08-30-2020 at 6:00 am

Transistor density process for Huawei and Apple

This comparison of smartphone processors from different companies and fab processes was originally going to be a post, but with the growing information content, I had to put it into an article. Here, due to information availability, Apple, Huawei, and Samsung Exynos processors will get the most coverage, but a few Qualcomm Snapdragon

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Fully Self-Aligned 6-Track and 7-Track Cell Process Integration

Fully Self-Aligned 6-Track and 7-Track Cell Process Integration
by Fred Chen on 08-23-2020 at 6:00 am

Fully Self Aligned 6 Track and 7 Track Cell Process Integration

For the 10nm – 5nm nodes, the leading-edge foundries are designing cells which utilize 6 or 7 metal tracks, entailing a wide metal line for every 4 or 5 minimum width lines, respectively (Figure 1).

Figure 1. Left: a 7-track cell. Right: a 6-track cell.

This is a fundamental vulnerability for lithography, as defocus can change… Read More


SEMICON West – Applied Materials Selective Gap Fill Announcement

SEMICON West – Applied Materials Selective Gap Fill Announcement
by Scotten Jones on 08-17-2020 at 5:00 pm

Applied Materials Selective Gapfill July 2020 Page 02

At SEMICON West, Applied Materials announced a new selective gap fill tool to address the growing resistance issues in interconnect at small dimensions. I had the opportunity to discuss this new tool and the applications for it with Zhebo Chen global product manager in the Metal Deposition Products group at Applied Materials.… Read More