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Why NA is Not Relevant to Resolution in EUV Lithography

Why NA is Not Relevant to Resolution in EUV Lithography
by Fred Chen on 05-05-2024 at 8:00 am

Why NA is Not Relevant to Resolution in EUV Lithography

The latest significant development in EUV lithography technology is the arrival of High-NA systems. Theoretically, by increasing the numerical aperture, or NA, from 0.33 to 0.55, the absolute minimum half-pitch is reduced by 40%, from 10 nm to 6 nm. However, for EUV systems, we need to recognize that the EUV light (consisting … Read More


Intel High NA Adoption

Intel High NA Adoption
by Scotten Jones on 04-24-2024 at 6:00 pm

High NA EUV Final Pre Briefing Deck 4.15.24 embargoed til 4.18 at 7am PT (1) Page 07

On Friday April 12th Intel held a press briefing on their adoption of High NA EUV with Intel fellow and director of lithography Mark Phillips.

In 1976 Intel built Fab 4 in Oregon, the first Intel fab outside of California. With the introduction of 300mm Oregon became the only development site for Intel with large manufacturing, development,… Read More


Huawei’s and SMIC’s Requirement for 5nm Production: Improving Multipatterning Productivity

Huawei’s and SMIC’s Requirement for 5nm Production: Improving Multipatterning Productivity
by Fred Chen on 04-23-2024 at 10:00 am

Self aligned blocking scheme

There has been much interest in Huawei’s and SMIC’s plans for 5nm production in the near future. Since there is no use of EUV in China, immersion DUV lithography (with a 76 nm pitch resolution) is expected to be used along with pitch quartering to achieve pitches in the 20-30 nm range expected for the 5nm and 3nm nodes [1].… Read More


ASML- Soft revenues & Orders – But…China 49% – Memory Improving

ASML- Soft revenues & Orders – But…China 49% – Memory Improving
by Robert Maire on 04-19-2024 at 8:00 am

Fully assembled TWINSCAN EXE 5000

ASML- better EPS but weaker revenues- 2024 recovery on track
China jumps 10% to 49%- Memory looking better @59% of orders
Order lumpiness increases with ASP- EUV will be up-DUV down
“Passing Bottom” of what has been a long down cycle

Weak revenues & orders but OK EPS

Reported revenue was Euro5.3B and EPS of Euro3.11… Read More


TSMC and Synopsys Bring Breakthrough NVIDIA Computational Lithography Platform to Production

TSMC and Synopsys Bring Breakthrough NVIDIA Computational Lithography Platform to Production
by Daniel Nenni on 04-02-2024 at 6:00 am

nvidia culitho

NVIDIA cuLitho Accelerates Semiconductor Manufacturing’s Most Compute-Intensive Workload by 40-60x, Opens Industry to New Generative AI Algorithms.

An incredible example of semiconductor industry partnerships was revealed during the Synopsys User Group (SNUG) last month. It started with a press release but there is much… Read More


Measuring Local EUV Resist Blur with Machine Learning

Measuring Local EUV Resist Blur with Machine Learning
by Fred Chen on 03-17-2024 at 10:00 am

Measuring Local EUV Resist Blur with Machine Learning

Resist blur remains a topic that is relatively unexplored in lithography. Blur has the effect of reducing the difference between the maximum and minimum doses in the local region containing the feature. Blur is particularly important for EUV lithography since EUV lithography is prone to stochastic fluctuations and also driven… Read More


Pinning Down an EUV Resist’s Resolution vs. Throughput

Pinning Down an EUV Resist’s Resolution vs. Throughput
by Fred Chen on 02-21-2024 at 8:00 am

Pinning Down an EUV Resist's Resolution

The majority of EUV production is on 5nm and 3nm node, implemented by late 2022. Metal oxide resists have not been brought into volume production yet [1,2], meaning that only organic chemically amplified resists (CARs) have been used instead until now. These resists have a typical absorption coefficient of 5/um [3,4], which means

Read More

Application-Specific Lithography: Avoiding Stochastic Defects and Image Imbalance in 6-Track Cells

Application-Specific Lithography: Avoiding Stochastic Defects and Image Imbalance in 6-Track Cells
by Fred Chen on 02-07-2024 at 6:00 am

Application Specific Lithography

The discussion of any particular lithographic application often refers to imaging a single pitch, e.g., 30 nm pitch for a 5nm-family track metal scenario. However, it is always necessary to confirm the selected patterning techniques on the actual use case. The 7nm, 5nm, or 3nm 6-track cell has four minimum pitch tracks, flanked… Read More


Non-EUV Exposures in EUV Lithography Systems Provide the Floor for Stochastic Defects in EUV Lithography

Non-EUV Exposures in EUV Lithography Systems Provide the Floor for Stochastic Defects in EUV Lithography
by Fred Chen on 01-18-2024 at 10:00 am

Defocus flare (small)

EUV lithography is a complicated process with many factors affecting the production of the final image. The EUV light itself doesn’t directly generate the images, but acts through secondary electrons which are released as a result of ionization by incoming EUV photons. Consequently, we need to be aware of the fluctuations… Read More


Application-Specific Lithography: Sense Amplifier and Sub-Wordline Driver Metal Patterning in DRAM

Application-Specific Lithography: Sense Amplifier and Sub-Wordline Driver Metal Patterning in DRAM
by Fred Chen on 12-25-2023 at 10:00 am

Varying pitch in metal lines in DRAM periphery

On a DRAM chip, the patterning of features outside the cell array can be just as challenging as those within the array itself. While the array contains features which are the most densely packed, at least they are regularly arranged. On the other hand, outside the array, the regularity is lost, but the in the most difficult cases, … Read More