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Measuring Local EUV Resist Blur with Machine Learning

Measuring Local EUV Resist Blur with Machine Learning
by Fred Chen on 03-17-2024 at 10:00 am

Measuring Local EUV Resist Blur with Machine Learning

Resist blur remains a topic that is relatively unexplored in lithography. Blur has the effect of reducing the difference between the maximum and minimum doses in the local region containing the feature. Blur is particularly important for EUV lithography since EUV lithography is prone to stochastic fluctuations and also driven… Read More


Pinning Down an EUV Resist’s Resolution vs. Throughput

Pinning Down an EUV Resist’s Resolution vs. Throughput
by Fred Chen on 02-21-2024 at 8:00 am

Pinning Down an EUV Resist's Resolution

The majority of EUV production is on 5nm and 3nm node, implemented by late 2022. Metal oxide resists have not been brought into volume production yet [1,2], meaning that only organic chemically amplified resists (CARs) have been used instead until now. These resists have a typical absorption coefficient of 5/um [3,4], which means

Read More

Application-Specific Lithography: Avoiding Stochastic Defects and Image Imbalance in 6-Track Cells

Application-Specific Lithography: Avoiding Stochastic Defects and Image Imbalance in 6-Track Cells
by Fred Chen on 02-07-2024 at 6:00 am

Application Specific Lithography

The discussion of any particular lithographic application often refers to imaging a single pitch, e.g., 30 nm pitch for a 5nm-family track metal scenario. However, it is always necessary to confirm the selected patterning techniques on the actual use case. The 7nm, 5nm, or 3nm 6-track cell has four minimum pitch tracks, flanked… Read More


Non-EUV Exposures in EUV Lithography Systems Provide the Floor for Stochastic Defects in EUV Lithography

Non-EUV Exposures in EUV Lithography Systems Provide the Floor for Stochastic Defects in EUV Lithography
by Fred Chen on 01-18-2024 at 10:00 am

Defocus flare (small)

EUV lithography is a complicated process with many factors affecting the production of the final image. The EUV light itself doesn’t directly generate the images, but acts through secondary electrons which are released as a result of ionization by incoming EUV photons. Consequently, we need to be aware of the fluctuations… Read More


Application-Specific Lithography: Sense Amplifier and Sub-Wordline Driver Metal Patterning in DRAM

Application-Specific Lithography: Sense Amplifier and Sub-Wordline Driver Metal Patterning in DRAM
by Fred Chen on 12-25-2023 at 10:00 am

Varying pitch in metal lines in DRAM periphery

On a DRAM chip, the patterning of features outside the cell array can be just as challenging as those within the array itself. While the array contains features which are the most densely packed, at least they are regularly arranged. On the other hand, outside the array, the regularity is lost, but the in the most difficult cases, … Read More


Is Intel cornering the market in ASML High NA tools? Not repeating EUV mistake

Is Intel cornering the market in ASML High NA tools? Not repeating EUV mistake
by Robert Maire on 12-24-2023 at 9:00 am

High NA EUV
  • Reports suggest Intel will get 6 of 10 ASML High NA tools in 2024
  • Would give Intel a huge head start over TSMC & Samsung
  • A big gamble but a potentially huge pay off
  • Does this mean $4B in High NA tool sales for ASML in 2024?

News suggests Intel will get 6 of first 10 High NA tools made by ASML in 2024

An industry news source, Trendforce, reports… Read More


BEOL Mask Reduction Using Spacer-Defined Vias and Cuts

BEOL Mask Reduction Using Spacer-Defined Vias and Cuts
by Fred Chen on 12-06-2023 at 6:00 am

BEOL Mask Reduction Using Spacer Defined Vias and Cuts

In recent advanced nodes, via and cut patterning have constituted a larger and larger portion of the overall BEOL mask count. The advent of SALELE [1,2] caused mask count to increase for EUV as well, resulting in costs no longer being competitive with DUV down to 3nm [3]. Further development by TEL [4] has shown the possibility for… Read More


Predicting Stochastic Defectivity from Intel’s EUV Resist Electron Scattering Model

Predicting Stochastic Defectivity from Intel’s EUV Resist Electron Scattering Model
by Fred Chen on 11-22-2023 at 6:00 am

Predicting Stochastic Defectivity from Intel's EUV Resist Electron Scattering Model

The release and scattering of photoelectrons and secondary electrons in EUV resists has often been glossed over in most studies in EUV lithography, despite being a fundamental factor in the image formation. Fortunately, Intel has provided us with a laboriously simulated electron release and scattering model, using the GEANT4… Read More


China’s hoard of chip-making tools: national treasures or expensive spare parts?

China’s hoard of chip-making tools: national treasures or expensive spare parts?
by Craig Addison on 11-20-2023 at 10:00 am

Raiders of the Lost Ark warehouse photo courtesy Paramount Pictures

In the closing scene of Steven Spielberg’s Raiders of the Lost Ark (1981), the camera pulls back to reveal an enormous warehouse stacked with crates of artifacts hidden away by the US government. 

One could imagine a similar warehouse in China today. The crates would hold a different kind of treasure – semiconductor production … Read More


The Significance of Point Spread Functions with Stochastic Behavior in Electron-Beam Lithography

The Significance of Point Spread Functions with Stochastic Behavior in Electron-Beam Lithography
by Fred Chen on 10-31-2023 at 10:00 am

Electron Beam Lithography

Electron beam lithography is commercially used to directly write submicron patterns onto advanced node masks. With the advent of EUV masks and nanometer-scale NIL (nanoimprint lithography), multi-beam writers are now being used, compensating the ultralow throughput of a single high-resolution electron beam with the use… Read More