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On Wednesday afternoon investigators, acting on a search warrant, searched two of Lo's homes, seizing computers, USB drives and other evidence, prosecutors said.
A court also approved a petition to seize his shares and real estate, the statement added...
Intel lays off 669 more Oregon workers as local headcount dwindles
Updated: Nov. 13, 2025, 5:07 p.m.
|Published: Nov. 13, 2025, 4:08 p.m.
By Mike Rogoway | The Oregonian/OregonLive
Intel laid off another 669 Oregon workers Thursday on top of 2,400 Washington County jobs the chipmaker cut in...
Such a big workload difference, if true, could correlate to the amount of business the respective companies are handling. Or else, one company is simply slacking 😏.
How could this happen without raising suspicions? So actually, the mention of the boxes kind of surprised me. If true, some staff at TSMC would also be in trouble for it. I am surprised that the boxes were not or would not be inspected. The procedures must be changed now for sure. But if there...
"Compared with TSMC, Intel is reportedly offering salaries that are 20–30% higher while providing a workload that is roughly half as heavy, successfully attracting some U.S. engineers to switch over."
The mention of workload difference caught my eye. If it's true, it says more about the...
Former TSMC senior vice president Wei-Jen Lo’s move to Intel—along with allegations that he took sub-2nm documents—has now sparked reports that Intel is also trying to recruit TSMC engineers in Arizona. According to Liberty Times, sources say Intel has recently been aggressively poaching...
The transistor density uses the standard cell height. For a 6-track cell, it means the cell height is 6 track metal pitches, although the rails occur after every four tracks. The rails would be 3 times the signal track metal width.
If the gate pitch is 54 nm, at 125 MTr/mm2, the cell height...
This is the X post I referred to:
定焦数码 mentioned it's between TSMC N6 and Samsung 5LPE. 5LPE pitches are given here: https://fuse.wikichip.org/news/2823/samsung-5-nm-and-4-nm-update/. 54 nm gate pitch and 36 nm M2 track pitch, giving 126 MTr/mm2.
The 125 MTr/mm2 came from a Weibo post on March 24 this year by 定焦数码, later reposted on X the same day by @Jukanlosreve.
If the SMIC N+3 125 MTr/mm2 density is real, then we can project some pitches, using calibration from https://www.angstronomics.com/p/the-truth-of-tsmc-5nm.
If the gate...
Huawei's upcoming Mate 80 Pro Max has shown up on Geekbench with a new Kirin 9030 SoC. It is the first smartphone chip to be manufactured on the SMIC N+3 node.
Anil Ganti, Published 11/25/2025 🇪🇸 🇵🇹
SMIC had achieved a significant breakthrough in its semiconductor manufacturing prowess. It has...
No, it is targeted at ASML staff, although customers can pay for their own staff training. High-NA only covered in the Netherlands.
https://www.reuters.com/world/asia-pacific/asml-launches-technical-academy-phoenix-train-in-demand-engineers-2025-11-20/
In publications (CSTIC, CN patents) they often do use 28 nm pitch or 30 nm pitch as examples. But whether that actually pans out, we'll have to see. TSMC N5 is in fact 28 nm MMP (35 nm track M2P).
I remember the X90 teardown now. I hadn't known it had been promoted by the state as 5nm the month before. The teardown must have truly caused some embarrassment, TechInsights now blacklisted in China. But what's more significant is whether Huawei itself had considered X90 any generation beyond...
