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  1. F

    Darth Vader in Semiconductor Industry?How the Turncoat and the Loyalist of TSMC Shaped the Global Chip War

    TSMC had done it better than Intel. Not sure if it's the same way SMC does it.
  2. F

    Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

    FWIW, NA is not figuring into EUV practical resolution. It's resist-limited at this point. https://www.spiedigitallibrary.org/conference-proceedings-of-spie/13424/1342403/NA033-EUV-extension-for-HVM-testing-single-patterning-limits/10.1117/12.3052244.full
  3. F

    Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

    Yes, direct print meant single exposure instead of multipatterning, in their context.
  4. F

    TSMC vs Intel track pitch scaling trend

    Tracks are conventionally M2, but Intel uses M0 apparently, at least for Intel 3/4.
  5. F

    Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

    So the oft-mentioned 40 steps is for the no High-NA contingency at 14A, then?
  6. F

    EUV productivity not the same across the field

    TSMC and ASML both reported that source power upgrades were not trivial, as pellicle damage tolerances need to be considered.
  7. F

    EUV productivity not the same across the field

    Not all EUV machines in use are equally productive. Old/new mix. Abstract ASML has been making steady advances in Extreme Ultraviolet (EUV) light source capability for more than 15 years. Since introduction of the 250W EUV light source in 2018, which ushered in the era of EUV High Volume...
  8. F

    Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

    I thought they presented SALELE with one block mask. Actually, it is usually presented with two block masks, one for each of the two metal line sub-patterns. I suppose it depends what they count as a "step". 24-32 nm pitch on 0.33 NA is just like 24-30 nm pitch on 0.55 NA. I don't know if the...
  9. F

    Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

    With a direct print at this pitch they won't be able to shrink this layer lengthwise, also due to the tip-to-tip distance.
  10. F

    TSMC vs Intel track pitch scaling trend

    6-track cell height scaling trend shows an interesting comparison between TSMC and Intel. PowerVia gave opportunity to relax the track pitch at Intel 18A. In the meantime, the track pitch scaling slowed down dramatically for TSMC. Perhaps it's coincidental with nanosheet introduction?
  11. F

    Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

    3 exposures with many more steps is an odd process integration. This is for 18A node?
  12. F

    Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

    In my recollection, it was merely from the drawing of the HD and HP cells, both appeared to be 5 tracks, and the cell heights are 160 and 180 respectively. Both size and spacing matter for the pitch dependent best focus.
  13. F

    Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

    They missed AWS? Faraday? Others?
  14. F

    Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

    This is P32 HD P36 HP IIRC, the two pitches don't focus the same in direct print.
  15. F

    Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

    Just viewing it as a kind of disclaimer, looked like fine print to me.
  16. F

    TSMC Is Reportedly Skipping High-NA EUV For The A14 (1.4nm) Process; Prioritizing Cost-Efficiency Over Performance

    Our knowledge of EUV is always growing. Earlier on much less was known, so we can expect a fast buildup of an EUV fleet without knowing any better, and using them maximally, at least to get as much key data as possible. But now I expect people to be more careful. Especially with the newly...
  17. F

    Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

    "Results may vary." :ROFLMAO: They talk about enabling direct print, but at the same time the 40-step multipatterning (3 masks) was broadcast widely as well.
  18. F

    TSMC Is Reportedly Skipping High-NA EUV For The A14 (1.4nm) Process; Prioritizing Cost-Efficiency Over Performance

    Yes, inversely proportional to (NA)^2.
  19. F

    TSMC Is Reportedly Skipping High-NA EUV For The A14 (1.4nm) Process; Prioritizing Cost-Efficiency Over Performance

    LELELELE was mainly shown by Samsung at 8nm if I recall correctly. The difficult with more than two LEs is the CD/pitch ratio is too low, so NILS (normalized image log-slope) is bad. This I doubt, since the fin pitch is so small. EUV DP still too expensive and more issues than DUV SAPQ. DUV...
  20. F

    TSMC Is Reportedly Skipping High-NA EUV For The A14 (1.4nm) Process; Prioritizing Cost-Efficiency Over Performance

    So far High-NA still gives bad images even at 28 nm pitch. To be fair low-NA should be the same. High-NA has less depth of focus so needs thinner resist, which tends to be more defective.
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