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That's funny, since they brought up the necessity of double patterning EUV at 5nm, triple patterning at 3nm, and quadruple patterning at 2nm. With 0.55 NA, stitching also forces loosening of minimum pitch, entailing multipatterning.
Rapidus plans to focus on smaller clients who can't afford the new 2nm technology.
https://www.trendforce.com/news/2024/04/26/news-rapidus-focuses-on-small-clients-diversifies-into-japan-to-mitigate-us-geopolitical-risks/
Without thinking too much about it, the cost is easily a top reason. TSMC 7nm is likely (still) cheaper than SMIC 7nm at this point, although SMIC N+2 probably is better than where it started a few years ago.
I suppose the teardowns would have to confirm it one way or the other, but the use of...
According to the PMT:
"The award amounts are subject to due diligence and negotiation of a long-form term sheet and award documents and are conditional on the achievement of certain milestones and remain subject to availability of funds. After the PMT is signed, the Department begins a...
"TSMC carefully evaluates technology innovations such as new transistor structures and new tools and considers their maturity, cost, and benefit to customers before deploying them to volume production," the chipmaker told The Reg.
"As we disclosed at our 2024 Technology Symposiums earlier this...
Power is next challenge for EUV lithography
November 3, 2024
By Nick Flaherty
The rollout of extreme ultraviolet (EUV) lithography could be hit by the increasing power requirements of the technology.
EUV is a key technology for the latest chip-making process technology, and Europe has been at...
Do (at least some) smartphone chips count as "AI chips"? Like Snapdragon advertises "on-chip AI". Maybe it is a design necessity now. In that case, the revenue loss to TSMC could be larger than expected for just server-targeted chips.
The bit cell size is not mentioned in the press sheet, it doesn't look like it's supposed to be the inverse of the macro density.
TSMC’s New, Industry-Leading 2nm CMOS Logic Platform: In a late-news paper, TSMC researchers will unveil the world’s most advanced logic technology. It is the...
The M0 and M1 of Intel 7 are a good example of processes which are essentially dropped.
They went from pure Co to Cu/Co, and the M0 and M1 pitches trended oppositely, M1 going back to almost the same as 14nm. Obviously, Intel 3 reused Intel 4 in this part.
At the same time, we haven't heard of a similar charge for TSMC's N7 when they went to N5. But we did hear of "margin dilution" when going to a new node. 90% node-to-node reuse is something to shoot for, but of course won't be possible with a fresh fab for a new node. Maybe the key difference...
It looks like the Intel 7 related charges are because there isn't enough reuse for Intel 4/3 and Intel 20A/18A. IIRC, TSMC shoots for at least 90% reuse.
I'm sorry this was not HBM but simply DDR5 comparison.
HBM3E is the most recent HBM to come out: https://www.trendforce.com/presscenter/news/20240930-12319.html/ 1ß figures directly into Micron's rollout: https://www.micron.com/products/memory/hbm/hbm3e whereas SK Hynix didn't focus on the node...
