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Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/search/292887/?c[users]=Fred+Chen&o=date
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021770
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

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  1. F

    Intel 18A Process Node Offers 25% Higher Frequency At ISO & 36% Lower Power At Same Frequency Versus Intel 3, Over 30% Density

    Yes, with Intel 3 M2 being much looser, seems Intel 3 should have been less, if not the same. On the other hand, if 32 nm pitch vs. 30 nm pitch makes that much of a difference, then 32 nm pitch is still on a cliff.
  2. F

    Intel 18A Process Node Offers 25% Higher Frequency At ISO & 36% Lower Power At Same Frequency Versus Intel 3, Over 30% Density

    I read this finally as less single exposure EUV for M0-M2 layers for 18A compared to Intel 3 (?) Power rail pitch should be cell height (160 nm?) so dry DUV could even do that.
  3. F

    Intel 18A Process Node Offers 25% Higher Frequency At ISO & 36% Lower Power At Same Frequency Versus Intel 3, Over 30% Density

    The TH article completely misparsed Ericsson's announcement.
  4. F

    Samsung and SK hynix advance 4F² DRAM as gateway to 3D memory

    The South Korean chipmakers accelerate shift to vertical DRAM architecture By Chun Byung-soo, Kim Mi-geon Published 2025.06.18. 11:35Updated 2025.06.18. 14:42 Samsung Electronics and SK hynix are accelerating the development of next-generation three-dimensional (3D) dynamic random-access...
  5. F

    EUVL and Source Workshop 21-26 June 2025

    They should have invited the Russian 11.2 nm group: https://semiwiki.com/forum/threads/russian-11-2-nm-euv-light-source-deliberately-uses-shorter-than-asmls-euv-wavelength.22347/
  6. F

    Intel 18A Process Node Offers 25% Higher Frequency At ISO & 36% Lower Power At Same Frequency Versus Intel 3, Over 30% Density

    Back in Jan 2023, PG had said that Intel 3 had a "leading cloud, edge, and datacenter solutions provider" as a customer. https://www.tomshardware.com/news/intel-ifs-lands-3nm-to-make-3nm-chips-for-major-customer That did not happen apparently as it was not mentioned in 2024...
  7. F

    TSMC Manages to Maintain the Crown in the Foundry Market as Samsung Is On Track to Be Replaced by China’s SMIC in Chip Market Share

    SMIC's rise is basically a testament that mature nodes still matter.
  8. F

    TSMC Manages to Maintain the Crown in the Foundry Market as Samsung Is On Track to Be Replaced by China’s SMIC in Chip Market Share

    Muhammad Zuhair Jun 10, 2025 at 12:58pm EDT The dynamics of the chip market have evolved rapidly in the past few quarters. While TSMC has maintained its dominance, Samsung Foundry seems to be struggling to maintain its hold. Samsung Foundry Struggles With Momentum In The Chip Industry as...
  9. F

    TSMC Crosses 90% 2nm Yields, Arizona US Plant Close To 100% Capacity With NVIDIA’s AI Chip Slated For Production – Reports

    "Memory products" => they mean SRAM?
  10. F

    Intel and SoftBank Launch Saimemory Joint Venture Targeting High-Bandwidth Memory Alternatives for AI and Revitalizing Japan's Chip Industry

    The packaging technology co-developed with DARPA doesn't look like it can easily be licensed to any partners.
  11. F

    Hitachi Electron Microscope View of a 5nm FinFET

    @Kazkek, thanks very much for the reference!
  12. F

    Hitachi Electron Microscope View of a 5nm FinFET

    Incredible image. What's the "2 kV finishing" to reduce the FIB damage?
  13. F

    Intel needs external foundry customers to make 14A process node pay off

    Ailing chip giant targets 2027 break-even as costly EUV tools raise stakes Dan Robinson Wed 14 May 2025 // 17:20 UTC Intel is wooing external chip customers for its 14A process node to justify the high costs involved, and aims for the foundry division to break even by 2027 - as part of ongoing...
  14. F

    How ASML Makes Chips Faster With Its New $400 Million High NA Machine

    I don't know that it has been proven in volumes anywhere close to production yet. Of course, a limiting factor is that it only fits regular grids of features, so maybe some DRAM layers may be immediately relevant for now. Actually, I had the impression Intel had dabbled with it, not sure where...
  15. F

    How ASML Makes Chips Faster With Its New $400 Million High NA Machine

    A large part of it is also the NA made a big jump this time (67%), which is different from prior generations (10-20%). Depth of focus dropped a lot. Resist is supposed to be thinner than it, so it will be too thin (<30 nm). The wavelength jump can also be said to be too drastic, becoming...
  16. F

    Nvidia announces Taiwan HQ in Taipei

    The chips fabbed in the US should be targeted for US customers.
  17. F

    Nvidia announces Taiwan HQ in Taipei

    Nvidia’s decision to establish its international headquarters in Taiwan is expected to bolster its China export strategy, according to industry analysts. The move, announced during CEO Jensen Huang’s keynote at Computex 2025, positions Taiwan as a critical hub for Nvidia’s AI and semiconductor...
  18. F

    Underlayer electron contamination in EUV lithography

    The secondary electrons from below the resist are obviously a very random, stochastic input image source in addition to the EUV input. But the image inputs do not stop there. The plasma environment above the resist generates plenty of exposing non-EUV, non-confined energy (VUV, electrons...
  19. F

    Underlayer electron contamination in EUV lithography

    During the EUV lithography process, a significant fraction of EUV photons is absorbed by the underlayer (UL), potentially leading to the emission of electrons that can alter the chemistry of the overlying resist. In this study, we address the challenge of understanding how such electrons...
  20. F

    How ASML Makes Chips Faster With Its New $400 Million High NA Machine

    Certain die heights may be (quietly) prohibited or at least discouraged. Specifically, those that fit an odd number of times into 33 mm.
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