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It hasn't been clear if it's SMIC doing the fabbing for Huawei or Huawei has their own fab. Either way, any subsidy for low yield must go to Huawei, it seems. SiCarrier is just another vying vendor.
Another thought I had on this was that Huawei is prioritizing AI chip development over foundry...
If this low yield is not an excursion, then it looks like it has been subsidized by the Chinese government for a while. So there has been no incentive for optimization or improvement of the process.
With the subsidy, in principle nothing would be "impossible" it seems.
I discussed a little...
Both SMIC and Huawei each have SAQP patents, e.g., CN110739210, CN112309838, CN117751427, but the techniques they describe are not as efficient as the one from SiCarrier CN117080054. Not-Invented-Here syndrome could make getting to 5nm much harder. It could explain the two-year delay.
The second group affected consists of technicians working in what is known as the ROC (Remote Operations Center), according to employees at the ROC who spoke to Calcalist. These operations staff remotely control, monitor, and manage production processes. ROC technicians do not physically work on...
Probably 38 nm minimum metal pitch makes most sense (6 tracks 228 nm height). Intel shouldn't have to resort to pitch quartering. Pitch halving should be sufficient.
Since taking the company's helm in March, CEO Lip-Bu Tan has moved fast to cut costs and find a new path to revive the ailing U.S. chipmaker. By June, he started voicing that a manufacturing process that prior CEO Pat Gelsinger bet heavily on, known as 18A, was losing its appeal to new...
Recent poll shows support for Taiwan, though I'm not sure about respondent selection.
https://www.taipeitimes.com/News/taiwan/archives/2025/06/30/2003839503
Yes, with Intel 3 M2 being much looser, seems Intel 3 should have been less, if not the same.
On the other hand, if 32 nm pitch vs. 30 nm pitch makes that much of a difference, then 32 nm pitch is still on a cliff.
I read this finally as less single exposure EUV for M0-M2 layers for 18A compared to Intel 3 (?) Power rail pitch should be cell height (160 nm?) so dry DUV could even do that.
The South Korean chipmakers accelerate shift to vertical DRAM architecture
By Chun Byung-soo,
Kim Mi-geon
Published 2025.06.18. 11:35Updated 2025.06.18. 14:42
Samsung Electronics and SK hynix are accelerating the development of next-generation three-dimensional (3D) dynamic random-access...
They should have invited the Russian 11.2 nm group: https://semiwiki.com/forum/threads/russian-11-2-nm-euv-light-source-deliberately-uses-shorter-than-asmls-euv-wavelength.22347/
Back in Jan 2023, PG had said that Intel 3 had a "leading cloud, edge, and datacenter solutions provider" as a customer. https://www.tomshardware.com/news/intel-ifs-lands-3nm-to-make-3nm-chips-for-major-customer That did not happen apparently as it was not mentioned in 2024...
Muhammad Zuhair Jun 10, 2025 at 12:58pm EDT
The dynamics of the chip market have evolved rapidly in the past few quarters. While TSMC has maintained its dominance, Samsung Foundry seems to be struggling to maintain its hold.
Samsung Foundry Struggles With Momentum In The Chip Industry as...
