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  1. F

    How does the HBF vs Xpoint technology

    I think a fair comparison would have the 3DXPoint dies linked by TSVs just like HBF and HBM (for 3D NAND and DRAM dies, respectively). The cost and performance were already not good enough for the 3D XPoint by itself to support a large enough market. The DRAM and NAND prices have gone up, but I...
  2. F

    LIVE: Intel CEO Lip-Bu Tan speaks at COMPUTEX

    Ok, by "untapped" capacity you mean room to improve. But the wafer cost is the same, so their margins need the yield.
  3. F

    Rapidus Completes 150 Billion Yen Funding Round from Japan Government

    If it's in R&D now, full-scale 2nm manufacturing by 2027 is definitely too soon.
  4. F

    LIVE: Intel CEO Lip-Bu Tan speaks at COMPUTEX

    You mean low volume (not yield)?
  5. F

    Rapidus Completes 150 Billion Yen Funding Round from Japan Government

    Intel Fab 52 construction alone cost over 5 billion: https://www.enr.com/articles/62647-offsite-assembly-high-velocity-design-help-deliver-arizona-intel-fab-plant
  6. F

    TSMC CEO sends blunt message to memory chip rivals

    AI demand, particularly HBM demand, has gone up more than fab capacity can handle. Normally, higher prices would reduce demand from consumers, which in turn, would lead prices down. But consumers' demand no longer seems to matter compared to the hyperscalers, who are willing to pay more. Since...
  7. F

    Intel bit off more than it could chew with 18A process node

    CFO Zinsner insists the troubled node was a one-off as 14A stays on track Published Wed 03 Jun 2026 // 16:20 UTC Intel is keen to reassure investors that its troubles with the 18A manufacturing process were a one-off, and that it is better positioned to capitalize on what it expects will be...
  8. F

    Monolithic three-dimensional integration of silicon transistors

    Published: 27 May 2026 Monolithic three-dimensional integration of silicon transistors Monolithic, three-dimensional (3D) integrated circuits promise advantages in packing density, energy consumption and interconnectivity bandwidth but require forming high-performance semiconductors and...
  9. F

    Samsung GAA SF2, Exynos 2600, cross-section images

    This teardown by Kurnal was posted on X yesterday: https://x.com/i/status/2062125652288131276 Pitches are listed there, but the really interesting finding to me was that the number of M2P tracks in the cell height went from 6 to 5. Still 6 M0 pitches within the cell height though. No buried rails.
  10. F

    If Taiwan Falls, the Fabs Burn: Why TSMC's Destruction Is the Inevitable Outcome of a China Invasion

    Douglas C. Youvan doug@youvan.com www.youvan.ai January 16, 2026 The question of whether Taiwan Semiconductor Manufacturing Company (TSMC) would be destroyed in a Chinese invasion of Taiwan is often framed as speculative, controversial, or hypothetical. In reality, the accumulated logic of...
  11. F

    Morgan Stanley reports Intel 18A yield at 50%

    Interesting comment from CFO here at Morgan Stanley conference back in March: https://ca.investing.com/news/transcripts/intel-at-morgan-stanley-conference-strategic-shifts-and-challenges-93CH-4495199 "As you might imagine, you know, when you’re, when you’re trying to like lock yields down and...
  12. F

    Morgan Stanley reports Intel 18A yield at 50%

    It was the same with the 7%/month. Probably safest to assume yield dominated by Panther Lake (~114 mm2).
  13. F

    Morgan Stanley reports Intel 18A yield at 50%

    Technology analyst Jukan pointed out on social media that, according to a report issued by Morgan Stanley, Intel's 18A process (compared to TSMC's 2nm) has a yield rate of only 50%, and the company is currently working hard to improve its yield level. The report indicates that customers have a...
  14. F

    Samsung SF2 transistor density benchmark against 18A and N3P

    Also brought up that's very interesting: 1. Intel 18A nanosheet vertical uniformity is better than SF2. 2. Samsung added a Heat Path Block (HPB), basically a heat sink above the CPU/GPU, sitting right next to the DRAM.
  15. F

    Samsung SF2 transistor density benchmark against 18A and N3P

    (coverage starts at 5:00)
  16. F

    Huawei plans 1.4-nm chips by 2031, Kirin 2026 Chip: 238 MTr/mm2 transistor density rivaling TSMC’s 3nm

    The metric 2/(CPP*Cell height) itself is not an issue since that information can be pulled for all the competitors; in fact, it might offer more clarity independent from layout utilization. The issue here is the formula should explicitly and unambiguously mention the use of stacking vertical...
  17. F

    Huawei plans 1.4-nm chips by 2031, Kirin 2026 Chip: 238 MTr/mm2 transistor density rivaling TSMC’s 3nm

    They shouldn't list the formula as 2/(CPP*Cell height) but maybe something like 2/(CPP*Cell height/# of vertical tiers), if that's their point.
  18. F

    Samsung GAA SF2, Exynos 2600, cross-section images

    So like CGP, we're seeing M2P leveling off around 28 nm?
  19. F

    Huawei plans 1.4-nm chips by 2031, Kirin 2026 Chip: 238 MTr/mm2 transistor density rivaling TSMC’s 3nm

    I see now, they plotted 2/(CPP*Cell Height). So this corresponds to ~114 MTr/mm2 if using the D_design formula, as expected for N+3. So then, to get to 238 from 155, LogicFolding is effectively reducing cell height and/or gate pitch? Arguably, making M2 the same pitch as M0 even by SAQP would...
  20. F

    China's Huawei reveals chip design breakthrough amid US sanctions

    Currently there is a report or rumor that Samsung is testing its 1.4nm on the next Exynos: https://wccftech.com/next-generation-exynos-tested-on-1-4nm-process-reveals-96mb-slc-cache-and-more/ but this soon suggests more likely not High-NA.
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