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Low Energy Electrons Set the Limits for EUV Lithography

Low Energy Electrons Set the Limits for EUV Lithography
by Fred Chen on 03-25-2020 at 6:00 am

Low Energy Electrons Set the Limits for EUV Lithography

EUV lithography is widely perceived to be the obvious choice to replace DUV lithography due to the shorter wavelength(s) used. However, there’s a devil in the details, or a catch if you will.

Electrons have the last word
The resist exposure is completed by the release of electrons following the absorption of the EUV photon.… Read More


TSMC 32Mb Embedded STT-MRAM at ISSCC2020

TSMC 32Mb Embedded STT-MRAM at ISSCC2020
by Don Draper on 03-20-2020 at 6:00 am

Fig. 1. Cross section of the STT MRAM bit cell in BEOL metallization layers between M1 and M5.

32Mb Embedded STT-MRAM in ULL 22nm CMOS Achieves 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150C and High Immunity to Magnetic Field Interference presented at ISSCC2020

1.  Motivation for STT-MRAM in Ultra-Low-Leakage 22nm Process

TSMC’s embedded Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM)… Read More


The Need for Low Pupil Fill in EUV Lithography

The Need for Low Pupil Fill in EUV Lithography
by Fred Chen on 03-15-2020 at 10:00 am

The Need for Low Pupil Fill in EUV Lithography 1

Extreme ultraviolet (EUV) lithography targets sub-20 nm resolution using a wavelength range of ~13.3-13.7 nm (with some light including DUV outside this band as well) and a reflective ring-field optics system. ASML has been refining the EUV tool platform, starting with the NXE:3300B, the very first platform with a numerical

Read More

A Forbidden Pitch Combination at Advanced Lithography Nodes

A Forbidden Pitch Combination at Advanced Lithography Nodes
by Fred Chen on 03-06-2020 at 10:00 am

A Forbidden Pitch Combination at Advanced Lithography Nodes

The current leading edge of advanced lithography nodes (e.g., “7nm” or “1Z nm”) features pitches (center-center distances between lines) in the range of 30-40 nm. Whether EUV (13.5 nm wavelength) or ArF (193 nm wavelength) lithography is used, one thing for certain is that the minimum imaged pitch … Read More


TSMC’s 5nm 0.021um2 SRAM Cell Using EUV and High Mobility Channel with Write Assist at ISSCC2020

TSMC’s 5nm 0.021um2 SRAM Cell Using EUV and High Mobility Channel with Write Assist at ISSCC2020
by Don Draper on 03-06-2020 at 6:00 am

Fig. 1 Semiconductor Technology Application Evolution

Technological leadership has long been key to TSMC’s success and they are following up their leadership development of 5nm with the world’s smallest SRAM cell at 0.021um 2 with circuit design details of their write assist techniques necessary to achieve the full potential of this revolutionary technology. In addition to their… Read More


GLOBALFOUNDRIES Sets a New Bar for Advanced Non-Volatile Memory Technology

GLOBALFOUNDRIES Sets a New Bar for Advanced Non-Volatile Memory Technology
by Mike Gianfagna on 03-02-2020 at 6:00 am

eNVM applications


Whether it’s the solid-state disk in your laptop, IoT/automotive hardware or  edge-based AI, embedded non-volatile memory (eNVM) is a critical building block for these and many other applications. The workhorse technology for this capability has typically been NOR flash (eFlash), but a problem looms as eFlash presents challenges… Read More


System Level Flows for SoC Architecture Analysis and Design – DVCON 2020

System Level Flows for SoC Architecture Analysis and Design – DVCON 2020
by Daniel Nenni on 02-21-2020 at 6:00 am

CST Header FF SL

As a professional conference attendee I look for the most meaningful way to spend my time and workshops is one of the best. Especially when a customer is involved and there is no bigger EDA customer than Intel, absolutely.

System Level Flows for SoC Architecture Analysis and Design

Speakers:
Swaminathan Ramachandran – … Read More


TSMC Unveils Details of 5nm CMOS Production Technology Platform Featuring EUV and High Mobility Channel FinFETs at IEDM2019

TSMC Unveils Details of 5nm CMOS Production Technology Platform Featuring EUV and High Mobility Channel FinFETs at IEDM2019
by Don Draper on 02-05-2020 at 10:00 am

Diagram of BEOL metallization comparing EUV vs. immersion photolithography

Back in April, 2019, TSMC announced that they were introducing their 5 nm technology in risk production and now at IEDM 2019 they brought forth a detailed description of the process which has passed 1000 hour HTOL and will be in high volume production in 1H 2020.  This 5nm technology is a full node scaling from 7nm using smart scaling… Read More


Intel vs AMD Q4 2019 Conference Calls

Intel vs AMD Q4 2019 Conference Calls
by Daniel Nenni on 02-04-2020 at 6:00 am

Intel 10nm Roadmap

Now that the dust has settled and I’m out of cronovirus quarantine let’s talk about the Intel and AMD conference calls. Unfortunately, the Intel and AMD marketing teams are still outpacing engineering so it is difficult to write something serious but I will do my best.

Spoiler Alert: Both CEOs disappoint.

First an Intel 10nm update:… Read More


WEBINAR: Prototyping With Intel’s New 80M Gate FPGA

WEBINAR: Prototyping With Intel’s New 80M Gate FPGA
by Daniel Nenni on 01-29-2020 at 10:00 am

The next generation FPGAs have been announced, and they are BIG!  Intel is shipping its Stratix 10 GX 10M FPGA, and Xilinx has announced its VU19P FPGA for general availability in the Fall of next year.  The former is expected to support about 80M ASIC gates, and the latter about 50M ASIC gates.  And, to bring this mind-boggling gate… Read More