3DIC Design from Concept to Silicon 800X100
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ASML Too Much Demand Plus Intel and High NA

ASML Too Much Demand Plus Intel and High NA
by Robert Maire on 01-23-2022 at 6:00 am

ASML High NA Intel

Too much demand- A “good” problem-Managing supply & capacity-Intel & Hi NA

-ASML great Q4 results-Demand off charts-Supply constrained
-Dealing with chain issues, putting out fires, expediting
-Looking forward to next gen High NA in 2024/2025
-Intel’s order doesn’t give advantage, just… Read More


TSMC Earnings – The Handoff from Mobile to HPC

TSMC Earnings – The Handoff from Mobile to HPC
by Doug O'Laughlin on 01-20-2022 at 10:00 am

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Hello! The most important semiconductor company in the world reported earnings last night. It’s been something of a tradition to post Taiwan Semiconductor Company (TSMC) earnings posts not behind my paywall, and I think that I’m going to continue that to kickoff each earnings season.

There are so many threads in the TSMC call that… Read More


Forty Four Billion Reasons Why TSMC Remains Dominant

Forty Four Billion Reasons Why TSMC Remains Dominant
by Robert Maire on 01-20-2022 at 6:00 am

Forty Four Billion Reasons Why TSMC Remains Dominant

-Chips for America is better than nothing, but not much
TSMC $40-44B Capex crushes competition (Intel & Samsung)
-Additional efforts other than handouts are necessary
-Could/should TSMC be “adopted” as a US company?

Competition can’t keep up with $40-$44B of Capex

TSMC’s recent announcement… Read More


Self-Aligned Via Process Development for Beyond the 3nm Node

Self-Aligned Via Process Development for Beyond the 3nm Node
by Tom Dillinger on 01-05-2022 at 6:00 am

TEM DoD

The further scaling of interconnect and via lithography for advanced nodes is challenged by the requirement to provide a process window that supports post-patterning critical dimension variations and mask overlay tolerances.  At the recent international Electron Devices Meeting (IEDM) in San Francisco, TSMC presented … Read More


Technology Design Co-Optimization for STT-MRAM

Technology Design Co-Optimization for STT-MRAM
by Tom Dillinger on 01-04-2022 at 6:00 am

sense amplifier

Previous SemiWiki articles have described the evolution of embedded non-volatile memory (eNVM) IP from (charge-based) eFlash technology to alternative (resistive) bitcell devices.  (link, link)

The applications for eNVM are vast, and growing.  For example, microcontrollers (MCUs) integrate non-volatile memory for … Read More


Advanced 2.5D/3D Packaging Roadmap

Advanced 2.5D/3D Packaging Roadmap
by Tom Dillinger on 01-03-2022 at 6:00 am

SoIC futures

Frequent SemiWiki readers are no doubt familiar with the advances in packaging technology introduced over the past decade.  At the recent International Electron Devices Meeting (IEDM) in San Francisco, TSMC gave an insightful presentation sharing their vision for packaging roadmap goals and challenges, to address the growing… Read More


Intel Discusses Scaling Innovations at IEDM

Intel Discusses Scaling Innovations at IEDM
by Scotten Jones on 12-14-2021 at 6:00 am

Intel at IEDM Slides Page 1

Standard Cell Scaling

Complex logic designs are built up from standard cells, in order to continue to scale logic we need to continually shrink the size of standard cells.

Figure 1 illustrates the dimensions of a standard cell.

 Figure 1. Standard Cell Dimensions.

 From figure 1 we can see that shrinking standard cell sizes requires… Read More


Ansys CEO Ajei Gopal’s Keynote on 3D-IC at Samsung SAFE Forum

Ansys CEO Ajei Gopal’s Keynote on 3D-IC at Samsung SAFE Forum
by Tom Simon on 12-09-2021 at 10:00 am

Ajei Gopal talks about 3D IC

System on chip (SoC) based design has long been recognized as a powerful method to offer product differentiation through higher performance and expanded functionality. Yet, it comes with a number of limitations, such as high cost of development.  Also, SoCs are monolithic, which can inhibit rapid adaptation in the face of changing… Read More


Low Power High Performance PCIe SerDes IP for Samsung Silicon

Low Power High Performance PCIe SerDes IP for Samsung Silicon
by Tom Simon on 12-02-2021 at 10:00 am

SerDes IP for PCIe

No matter how impressive the specifications are for an SoC, the power performance and area of the finished design all depend on the IP selected for the IO blocks. In particular, most SOCs designed for consumer and enterprise applications rely heavily on PCI Express. Because PCIe analog IP is critical to design success, Samsung … Read More


US Supply Chain Data Request Elicits a Range of Responses, from Tight-Lipped to Uptight

US Supply Chain Data Request Elicits a Range of Responses, from Tight-Lipped to Uptight
by Craig Addison on 11-14-2021 at 6:00 am

China TSMC Supply chain woes 2021

TSMC drew the ire of Chinese state media last week after it complied with the US Department of Commerce request to submit supply chain data by the November 8 deadline.

The Chinese reports, which called it an act of “surrender” to US hegemony, were careful in laying blame on Taipei for caving in to Washington, rather than pointing fingers… Read More