Synopsys made significant announcements during the recent TSMC OIP Ecosystem Forum, showcasing a range of cutting-edge solutions designed to address the growing complexities in semiconductor design. With a strong emphasis on enabling next-generation chip architectures, Synopsys introduced both new technologies and … Read More
TSMC 16th OIP Ecosystem Forum First Thoughts
Even though this is the 16th OIP event please remember that TSMC has been working closely with EDA and IP companies for 20+ years with reference flows and other design enablement and silicon verification activities. The father of OIP officially is Dr. Morris Chang who named it the Grand Alliance. However, Dr. Cliff Hou is the one … Read More
TSMC OIP Ecosystem Forum Preview 2024
The 2024 live conferences have been well attended thus far and there are many more to come. The next big event in Silicon Valley is the TSMC Global OIP Ecosystem Forum on September 25th at the Santa Clara Convention Center. I expect a big crowd filled with both customers and partners.
This is the 16th year of OIP and it has been an honor… Read More
Intel and Cadence Collaborate to Advance the All-Important UCIe Standard
The Universal Chiplet Interconnect Express™ (UCIe™) 1.0 specification was announced in early 2022 and a UCIe 1.1 update was released on August 8, 2023. This open standard facilitates the heterogeneous integration of die-to-die link interconnects within the same package. This is a fancy way of saying the standard opens the door… Read More
The Chip 4: A Semiconductor Elite
Can a 4-member alliance reshape the semiconductor industry?
Semiconductors are ubiquitous in electronics and computing devices, making them essential to developments in AI, advanced military, and the world economy. As such, it is unquestionable that nations attain considerable … Read More
The State of The Foundry Market Insights from the Q2-24 Results
If you work in the Semiconductor or related industry, you know that industry cycles can profoundly impact your business. It is crucial for strategic development to invest at the appropriate time and to rope the sails when necessary.
As a semiconductor investor, you’re accustomed to the ebb and flow of industry cycles. It’s… Read More
Application-Specific Lithography: Patterning 5nm 5.5-Track Metal by DUV
At IEDM 2019, TSMC revealed two versions of 5nm standard cell layouts: a 5.5-track DUV-patterned version and a 6-track EUV-patterned version [1]. Although the metal pitches were not explicitly stated, later analyses of a 5nm product, namely, Apple’s A15 Bionic chip, revealed a cell height of 210 nm [2]. For the 6-track … Read More
3D IC Design Ecosystem Panel at #61DAC
At #61DAC our very own Daniel Nenni from SemiWiki moderated an informative panel discussion on the topic of 3D IC Design Ecosystem. Panelists included: Deepak Kulkarni – AMD, Lalitha Immaneni – Intel Foundry, Trupti Deshpande – Qualcomm, Rob Aitken – CHIPS, Puneet Gupta – UCLA, Dragomir Milojevic – imec. Each panelist had a brief… Read More
Intel’s Death Spiral Took Another Turn
Does this justify the widespread Intel bashing?
The latest Intel earnings release was another sharp and deeper turn into the company’s death spiral. On the surface, it is just a whole load of bad news, and the web has been vibrating with Intel bashing since the release.
So what are the facts?
From a revenue perspective, Intel was inside… Read More
TSMC’s Business Update and Launch of a New Strategy
What looks like a modest market expansion strategy is all but modest.
Insights into the Semiconductor Industry and the Semiconductor Supply Chain.
As usual, when TSMC reports, the Semiconductor industry gets a spray of insights that help understand what goes on in other areas of the industry. This time, TSMC gave more insight … Read More
5 Expectations for the Memory Markets in 2025