Its all about the Transistors- 57 Billion reasons why Apple/TSMC are crushing itThe Apple event today was essentially a reveal…Read More
Neural Network Growth Requires Unprecedented Semiconductor ScalingThe truth is that we are just at…Read More
Take the Achronix Speedster7t FPGA for a Test Drive in the LabAchronix is known for its high-performance FPGA solutions.…Read More
APR Tool Gets a Speed Boost and Uses Less RAMAutomatic Place and Route (APR) tools have been…Read More
Analysts missed all warning signs until Intel spelled it out
12% stock drop shows disconnect and misunderstanding
No quick fix, this is a long term, uncertain problem & solution
Everyone ignored the obvious until it ran them over
A 12% stock drop is fault of investors/analysts not Intel
Whenever a stock drops 12% in one day there… Read More
There are certain tasks that have been the holy grail of EDA for some time. A real silicon compiler – high level language as input and an optimal, correct layout as output is one. Fully automated analog design – objectives as input, optimal circuit as output is another. With the increased layout times, due to the ever-increasing design… Read More
This is another level-up story, a direction I am finding increasingly appealing. This is when a critical supplier in the electronics value chain moves beyond islands of design automation to provide an integrated solution for the front-to-back design for capabilities now essential for automotive and industrial automation … Read More
Standards help our EDA and IP industry grow more quickly and with less CAD integration efforts, and IP-XACT is another one of those Accellera standards (1685-2009) that is coming of age, and enabling IP reuse for SoC design teams. Here at SemiWik, we’ve been writing about Defacto Technologies and their prominent use of IP-XACT… Read More
We used to be comfortable with the idea that the worlds of logical design and physical implementation could be largely separated. Toss the logical design over the wall, and the synthesis and P&R teams would take care of the rest. That idea took a bit of a hit when we realized that synthesis had to become physically aware. The synthesis… Read More
Recently, a patent application from TSMC [1] revealed target EUV doses used in the range of 30-45 mJ/cm2. However, it was also acknowledged in the same application that such doses were too low to prevent defects and roughness. Recent studies [2,3] have shown that by considering photon density along with blur, the associated shot… Read More
Verification is a complex task that takes the majority of time and effort in chip design. At Veriest, as an ASIC services company, we have the opportunity to work on multiple projects and methodologies, interfacing with different experts.
In this “Verification Talks” series of articles, we aim to leverage this unique… Read More
Frequent SemiWiki readers are aware of the growing significance of heterogeneous multi-die packaging technologies, offering a unique opportunity to optimize system-level architectures and implementations. The system performance, power dissipation, and area/volume (PPA/V) characteristics of a multi-die… Read More
Lam- good quarter but supply chain headwinds limit upside
Memory seems OK for now but watch pricing
China will also weaken which may add caution
Performance remains solid as does technology prowess
The yellow caution flag in the Semi race impacts Lam as well
As we suggested two weeks ago and saw with ASML this morning, supply chain… Read More
ASML great QTR but supply chain will limit acceleration
Products are most complex with most extensive supply chain
Long term position fantastic but investors will be nervous
300M pushouts in DUV with EUV still on track
Good quarter but yellow caution flag is out for supply chain concerns
ASML reported great revenues of Euro5.2B… Read More
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Its all about the Transistors- 57 Billion reasons why Apple/TSMC are crushing it