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Intel- Analysts/Investor flub shows disconnect on Intel, Industry & challenges

Intel- Analysts/Investor flub shows disconnect on Intel, Industry & challenges
by Robert Maire on 10-27-2021 at 2:00 pm

Pat Gelsinger Triple Spend

Analysts missed all warning signs until Intel spelled it out
12% stock drop shows disconnect and misunderstanding
No quick fix, this is a long term, uncertain problem & solution
Everyone ignored the obvious until it ran them over

A 12% stock drop is fault of investors/analysts not Intel

Whenever a stock drops 12% in one day there… Read More


Webinar: A Practical Approach to FinFET Layout Automation That Really Works

Webinar: A Practical Approach to FinFET Layout Automation That Really Works
by Mike Gianfagna on 10-27-2021 at 10:00 am

Webina A Practical Approach to FinFET Layout Automation That Really Works

There are certain tasks that have been the holy grail of EDA for some time. A real silicon compiler – high level language as input and an optimal, correct layout as output is one. Fully automated analog design – objectives as input, optimal circuit as output is another. With the increased layout times, due to the ever-increasing design… Read More


Cadence Reveals Front-to-Back Safety

Cadence Reveals Front-to-Back Safety
by Bernard Murphy on 10-27-2021 at 6:00 am

J897 Functional Safety Press Image small min

This is another level-up story, a direction I am finding increasingly appealing. This is when a critical supplier in the electronics value chain moves beyond islands of design automation to provide an integrated solution for the front-to-back design for capabilities now essential for automotive and industrial automation … Read More


Webinar – How to manage IP-XACT complexity in conjunction with RTL implementation flow

Webinar – How to manage IP-XACT complexity in conjunction with RTL implementation flow
by Daniel Payne on 10-26-2021 at 10:00 am

RTL Integration

Standards help our EDA and IP industry grow more quickly and with less CAD integration efforts, and IP-XACT is another one of those Accellera standards (1685-2009) that is coming of age, and enabling IP reuse for SoC design teams. Here at SemiWik, we’ve been writing about Defacto Technologies and their prominent use of IP-XACT… Read More


Physically Aware SoC Assembly

Physically Aware SoC Assembly
by Bernard Murphy on 10-26-2021 at 6:00 am

SoC Assembly min 1

We used to be comfortable with the idea that the worlds of logical design and physical implementation could be largely separated. Toss the logical design over the wall, and the synthesis and P&R teams would take care of the rest. That idea took a bit of a hit when we realized that synthesis had to become physically aware. The synthesis… Read More


The Challenge of Working with EUV Doses

The Challenge of Working with EUV Doses
by Fred Chen on 10-25-2021 at 2:00 pm

The Challenge of Working with EUV Doses

Recently, a patent application from TSMC [1] revealed target EUV doses used in the range of 30-45 mJ/cm2. However, it was also acknowledged in the same application that such doses were too low to prevent defects and roughness. Recent studies [2,3] have shown that by considering photon density along with blur, the associated shot… Read More


Verification Completion: When is Enough Enough?  Part II

Verification Completion: When is Enough Enough?  Part II
by Dusica Glisic on 10-25-2021 at 10:00 am

Tunnel min

Verification is a complex task that takes the majority of time and effort in chip design. At Veriest, as an ASIC services company, we have the opportunity to work on multiple projects and methodologies, interfacing with different experts.

In this “Verification Talks” series of articles, we aim to leverage this unique… Read More


Design Planning and Optimization for 3D and 2.5D Packaging

Design Planning and Optimization for 3D and 2.5D Packaging
by Tom Dillinger on 10-25-2021 at 6:00 am

platform

Introduction

Frequent SemiWiki readers are aware of the growing significance of heterogeneous multi-die packaging technologies, offering a unique opportunity to optimize system-level architectures and implementations. The system performance, power dissipation, and area/volume (PPA/V) characteristics of a multi-die… Read More


LRCX- Good Results Despite Supply Chain “Headwinds”- Is Memory Market OK?

LRCX- Good Results Despite Supply Chain “Headwinds”- Is Memory Market OK?
by Robert Maire on 10-24-2021 at 10:00 am

Lam Research Report 2021 SemiWiki

Lam- good quarter but supply chain headwinds limit upside
Memory seems OK for now but watch pricing
China will also weaken which may add caution
Performance remains solid as does technology prowess

The yellow caution flag in the Semi race impacts Lam as well

As we suggested two weeks ago and saw with ASML this morning, supply chain… Read More


ASML- Speed Limits in an Overheated Market- Supply Chain Kinks- Long Term Intact

ASML- Speed Limits in an Overheated Market- Supply Chain Kinks- Long Term Intact
by Robert Maire on 10-24-2021 at 6:00 am

ASML Report 2021

ASML great QTR but supply chain will limit acceleration
Products are most complex with most extensive supply chain
Long term position fantastic but investors will be nervous
300M pushouts in DUV with EUV still on track

Good quarter but yellow caution flag is out for supply chain concerns

ASML reported great revenues of Euro5.2B… Read More