SIC 2020 Forum 800x100

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                    [post_date] => 2020-11-25 10:00:46
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                    [post_content] => - Tsinghua $198M Bond Bust
- Good for memory: Samsung Micron LG Toshiba -
- Not good for chip equipment
- Could China Credit Crunch hit more than foundry embargo?
- Damage to China memory positive for other memory makers
- Not good for chip equip if customers can't get money

China Semiconductor Bond Bust

China's most prestigious leader of the effort to become dominant in semiconductors suffered an embarrassment of defaulting on $198M in bonds that were due Nov 17th. While seemingly a drop in the bucket of overall debt and the fact that they were in the midst of negotiating their way out it still sends shivers through China's debt market and sent the bonds plummeting.

Tsinghua is not the only state backed Chinese firm with bond troubles which makes the concerns all the more worrisome.

Chinese tech group joins list of companies to default on bond issue

NAND in Wuhan and DRAM in Chongqing Tsinghua already has a NAND factory in otherwise famous Wuhan and is planning a DRAM fab in Chongqing. They are a spinoff subsidiary of the prestigious Bejing University. They are perhaps the shining star of China's semiconductor aspirations. Though SMIC has been around a long time it seemed Tsinghua had more potential. Tsinghua Unigroup default tests China's chipmaking ambitions

Good for non Chinese memory makers like Samsung & Micron, LG & Toshiba

Being in the memory market and having the specter of China entering your market after watching China annihilate the LED & solar cell markets was likely quite chilling. China obviously doesn't care about profitability (at least not in the beginning) and could easily trash pricing and destroy the commodity memory market just like the commodity LED and solar markets before it. If I were in Boise I might have a little schadenfreude about the Chinese bond market right now, not unlike TSMC and SMIC. Anything that slows down China's aspirations in the memory market is likely positive for other competitors. Equipment vendors likely between a rock and a hard place in China Checking accounts receivable. Semiconductor equipment makers may not be as happy about the bond default and subsequent credit downgrades. We would bet a lot of money that the equipment makers are likely owed a whole lot more than $198M in equipment purchases and are looking at many times that in future orders and business. So their exposure far exceeds the bondholders. Unlike the bondholders, equipment makers don't want to stop shipping to their biggest, best and fastest growing market, that is China. If equipment makers stop shipping due to credit risk/downgrades or fear of not getting paid then Tsinghua will avoid doing business with them at all costs (its not like there aren't trying to avoid American equipment already given what happened to their cousins at SMIC). Equipment vendors have to keep shipping with the hope that the Chinese government will be the backstop, or the company figures it out. We can only imagine that some CFO's have to be checking their Tsinghua related accounts receivable exposure.

Credit is all about faith Too big/important to fail?

Lest anyone forget, the credit market is all about faith. Faith in getting paid back on the loan. The 2008/2009 market collapse was a collapse in the credit market. Faith in ever getting repaid went to zero. The semiconductor industry is very highly capital intensive and very fickle in cyclical profitability. In addition the would be Chinese chip makers are likely finding out that the semiconductor market is much, much harder than the LED and solar markets which were relative pushovers. The cost of an LED "fab" and complexity of process is not even a rounding error as compared to making a 128 level NAND chip. It is likely that getting to yield, meaning getting to revenue, let alone profitability will likely be a lot longer and a lot harder than many in China likely anticipated after the cakewalk in LED and solar. This means that many Chinese firms could have miscalculated when they would have been able to pay back debt and could find themselves in a cash crunch needing to extend credit terms out some more years/months. We don't know what caused Tsinghua's issue but breaking the faith was not good as their bonds fell all the way down to 68 cents on the dollar at one point. (we don't think equipment vendors would like to take 68 cents on the dollar owed them). In the end, Tsinghua, like some US financial firms in 2008/9, is too big/important to fail and the Chinese government will step in at some point. The question is when and how and who will get hurt in the collateral damage

Could the US administer a "Coup de Grace"? Part of the outgoing, "Scorched earth" policy

It is abundantly clear that the outgoing administration has embarked on a scorched earth policy for various reasons. Much of the scorched earth has been directed at international relations such as potentially attacking Iran, recalling troops and trying to make good on other campaign promises. Trade with China has been talked about as one such target. The SMIC embargo, announced shortly before the election certainly was effective at hurting China's chip ambition. Could the embargo be extended to memory, which is certainly capable of potential military "dual use technology" as a parting shot on the way out the door? Or maybe a blanket embargo? If there were a time to hurt China, the lame duck session is it.

The stocks

Most all semi stocks have been super hot as demand continues to be strong. The Tsinghua news is mildly positive for other memory makers as it will likely weaken and or slow China's memory ambitions and ability to crush memory pricing. It is likely not all that negative for equipment companies as they have even survived the SMIC embargo without so much as a scratch. If anything, it may be a hidden positive as it will likely moderate memory spending which drives the notorious boom bust cycles in memory. TSMC continues to be a huge winner. Micron seems in fine shape as well and would be happy to see Tsinghua go the way of Jinhua, even though we don't think that will happen. Equipment companies may see a hiccup or two in revenue recognition but not likely more than that unless things really go off the tracks, like the US upping the ante. While a possibility, we think the administration seems too pre-occupied with other fights with too little time left on the clock. [post_title] => China Semiconductor Bond Bust! [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => china-semiconductor-bond-bust [to_ping] => [pinged] => [post_modified] => 2020-11-25 17:38:51 [post_modified_gmt] => 2020-11-26 01:38:51 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=293363 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [1] => WP_Post Object ( [ID] => 293055 [post_author] => 11830 [post_date] => 2020-11-25 08:00:08 [post_date_gmt] => 2020-11-25 16:00:08 [post_content] => [caption id="attachment_293112" align="aligncenter" width="1106"]Cadence makes floorplanning easier by changing the rules Mixed placement floorplan[/caption]

SoC designs are getting more complex, resulting in a higher level of difficulty to get anything done. This trend is well-known. What I want to focus on here is how to deal with the issue of complexity. There are many approaches to taming this problem — faster algorithms for one, and improved algorithm efficiency or the ability to run on multiple processors are two ways to do that. There are also strategies to integrate algorithms in new ways that provide new perspectives on the problem.  And then there’s the magic of AI/ML. I recently described enhancements Cadence made to the Tempus Timing Signoff Solution that deliver faster timing signoff. This piece discussed how to deploy these last two strategies. What we will discuss here uses none of the above. It is a new approach to solving complexity. Cadence makes floorplanning easier by changing the rules.

This is a remarkable story of innovation. I had the opportunity to speak with Vinay Patwardhan, product management group director in the Digital & Signoff Group at Cadence about the details. Before moving to EDA, Vinay had a career as a design engineer at TI and Sun Microsystems, so he has a deep understanding of design complexity challenges. We started our conversation reviewing some of the basics of floorplanning. This step in the design process has substantial ramifications on downstream implementation. If you start with a good floorplan, things go relatively smoothly and power, performance and area (PPA) objectives are met. If the initial floorplan has shortcomings, which is often the case, you are faced with long iteration loops to converge on a viable design.

As a result, there is a lot of automation deployed early in the design process to try and get the best initial floorplan possible. Vinay explained the traditional approach here. First, macros for the design are placed around the periphery of the chip. Since macros are large blocks that are difficult to move later, they are placed first. Memories, register files or analog blocks are examples of macros. Following macro placement, standard cells are placed in the available area in the interior of the chip. Vinay explained that this approach has some built-in problems with new chip architectures.  Many of these designs do a lot of data acquisition, storage and processing so there are a lot of macros to place. Putting a large number of macros on the periphery creates long wire problems that, in turn, create timing and congestion problems. This makes for a lot of iterations for repair, creating a longer design cycle.

It turns out the main reasons for this macro/standard cell placement process has to do with the limitations of the placer. Vinay explained that typical algorithms use quadratic spatial approaches to divide the available area into sub-regions to solve the two-dimensional standard cell placement problem. So, a “sea of gates” continuous area in the interior of the chip is needed for this to work.

Here is where the conversation got interesting, as Vinay described a way to change the rules of floorplanning. Vinay explained that, if macros are not bound by the limitation to be anchored to the four sides of the available area and are instead allowed to “float”, there is more flexibility for placement algorithms to find an optimal location to a multi-objective optimization problem. He further explained that the new GigaPlace XL engine, within the Cadence Innovus Implementation System, is an extension of the multi-objective standard cell placement GigaPlace engine. GigaPlace XL can handle the placement of macros together with standard cells and I/Os in the same step, concurrently. So, Cadence makes floorplanning easier by changing the rules.

Vinay went on to explain that the Innovus Implementation System is already five years old. About two years ago, Cadence began looking at ways to simultaneously solve the macro/standard cell placement problem. Vinay confessed he was skeptical of this idea at first, having done a lot of complex designs himself. However, after a year of early customer engagements and another year of productization, the solution is here, and it works well. There were some patents filed along the way, too.

We got into some of the details. Macro placement is a combinatorial problem, while standard cell placement is a numerical one. The breakthrough for the GigaPlace XL engine inside Innovus is that, with its solver-based placement technology, it can solve continuous optimization and combinatorial optimization simultaneously. This offers two key benefits:

  • Standard cells can be placed on all four sides of the macros, resulting in more resources for timing and wirelength optimization, which leads to improved timing, area, and power
  • A slack-aware numerical solver looks at standard cell delays while doing a macro placement, reducing the approximation involved in combinatorial trial-and-error analysis methods, resulting in fewer iterations while delivering a feasible, working floorplan.

Vinay shared a lot of data that details the impact this approach can have. The table, below, summarizes some key metrics.

[caption id="attachment_293124" align="aligncenter" width="3456"]Cadence makes floorplanning easier by changing the rules Advanced node designs run with mixed placement showing PPA improvement[/caption]

The PPA improvements are significant. The efficiency improvements shown in the last two columns are quite impressive and really made me take notice. This new technology supports multiple design styles, including advanced node FinFET. There are also well thought out ways to add user control. Vinay stated that customers are already using this new technology to achieve and exceed their PPA targets with a shorter tapeout schedule. Vinay has written a very informative white paper on this approach entitled, Overcoming PPA and Productivity Challenges of New Age ICs with Mixed Placement Innovation”. You can download your copy here to get the details of how Cadence makes floorplanning easier by changing the rules.

[post_title] => Cadence is Making Floorplanning Easier by Changing the Rules [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => cadence-is-making-floorplanning-easier-by-changing-the-rules [to_ping] => [pinged] => [post_modified] => 2020-11-25 22:19:27 [post_modified_gmt] => 2020-11-26 06:19:27 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=293055 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [2] => WP_Post Object ( [ID] => 293309 [post_author] => 14 [post_date] => 2020-11-25 06:00:06 [post_date_gmt] => 2020-11-25 14:00:06 [post_content] => - The new M1 chip unveils previously hidden asset - Could/should Apple sell semiconductors? - Are servers next? - The M1 chip appears to be a rousing success and the beginning of a new era Apple M1 Essentially 100% of all early reports on the performance of the M1 chip have come back with stellar reviews. Great performance across the board across a multitude of applications while barely sipping power. It checks all the boxes of speed, power , memory, graphics, neural engine etc; Of course this is all enabled by TSMC's 5NM process which squeezes 16 billion transistors into the M1. The question from an investors point of view is what this does to the competition as well as what does it do for Apple. The impact cannot be underestimated and could easily extend well beyond what investors currently think and expect.

What would a stand alone "Apple Semiconductor" be worth?

"Apple Semiconductor", Intel, AMD & Nvidia etc; all seem a lot alike as they are essentially all "fabless" design houses (or will be soon in the case of Intel) that outsource manufacture to TSMC. Nvidia leads with a market cap of $325B, Intel is at $190B and AMD is $103B. Qualcomm is $163B and Broadcom is $157B. Nvidia could get even larger with an ARM acquisition. Apple didn't just get into the semiconductor business recently. It's has been in the business for many years, well over 13 years. Going back to the first iPhone introduced in 2007. Apple's history and line of of semiconductors would easily rival any current chip maker out there.

Apple's Chip History

Apple's breath and depth in semiconductor design and manufacture put it firmly in the big leagues next to any of the top chip makers today. We could easily argue that "Apple Semiconductor" would be worth more than either Intel or AMD. Both Intel and AMD's primary line of business is making X86 compatible processors for PCs and servers. The X86 architecture goes way, way back to the original 8086 which was released an astounding 41+ years ago back in 1979. Backward X86 compatibility of todays processors made by Intel and AMD is a blessing and a curse at the same time. It brings a wealth of software that will run on anything X86 compatible but can also act as a drag on overall performance based on a 40+ year old architecture compatibility. Chip design engineers at both AMD and Intel have never been able to erase the entire blackboard and literally "start with a clean slate". Apple obviously does not have quite as much history to lug around and in fact just started with a relatively clean slate for the M1 design even while maintaining IOS compatibility.

Back to the days of "Big Hair"

X86 was built in the days of desktop PCs that morphed into laptops and servers even though saddled with power hungry CPUs that were always plugged into a wall socket. The M1 is designed in the era of smart phones and cloud computing. AI & ML. Stunning graphics and a purpose built parallel architecture. In summary we think that Apple Semiconductor would be worth more than either Intel or AMD. When we compare Apple Semiconductor to Nvidia and Qualcomm, Broadcom. Apple clearly has much of the capability of Qualcomm, Broadcom in communications and other support semiconductors but perhaps more importantly has one foot, perhaps both feet firmly planted in the future of computers and semiconductors as Nvidia does with AI & graphics capabilities. Today we can say without exaggeration that Apple makes both the best smart phone chip as well as the best laptop/desktop chip versus anyone. All this implies that "Apple Semiconductor" as a standalone company would likely surpass the market cap of any and all chip companies currently out there. This is all well and fine you may say but its merely an academic exercise as "Apple Semiconductor" is inside Apple never to be let out of its "gilded cage" But what if it were free?

Could/Should Apple Attack the Server Market?

Apple's recent M1 roll out never mentioned the word server. However we think the M1 begs the question as to whether it would and could be dominant in the highly sought after and cash cow market that is the server/cloud market. Its Intel's sacred cow and obviously already in AMD's crosshairs but could Apple swoop in and clean up? We don't think that Apple really wants to crank out servers but it could do very well selling CPUs to all the server makers such as Intel does. Heck, Apple could start conversion on their own huge server farm. Maybe sell processors to Google, Amazon and Facebook etc; or all the huge Chinese server farms. Power & cooling are perhaps the biggest deals in the server world and so far the one of the biggest selling points of the M1 is its low power, fans never go on, design.

The power savings alone could be the reason to switch

We think the idea is not so far fetched as the server / cloud business is an attractive target that Apple has yet to tap and now they clearly have the ammunition to do so. Of course both Intel and AMD will improve once they start producing parts on TSMC's 5NM or 3NM and beyond but right now Apple has a pretty big lead over both and is TSMC's biggest customer which gets them an advantage. From a strategic game, this could even foil Nvidia's plan for ARM and data center conquest, thus placing Apple Semiconductor well above even Nvidia.

Why stop at server chips?

Of course we can follow the logic of entering the server market with moving into the AI or other markets such as automotive etc; The list and opportunities are long. We do doubt that Apple would ever sell its crown jewel chip technology to competitors but you never know.

Does "Apple Semiconductor" add to $2T market cap?

Its hard to move the needle on a company that's already pushing a $2T market cap, even a few hundred billion or so. While its hard to do some additive math here, we think more importantly that it just further underscores Apple's value and perhaps previously hidden value while also exposing some potential vulnerabilities of existing competitors in the semiconductor business. Apple is still somewhat limited to being a customer of TSMC but its a very symbiotic relationship much like the "Wintel", Microsoft/Intel relationship which dominated tech for so long "Apple/TSM Semiconductor Inc" is obviously very formidable and much more so than Wintel ever was.

The stocks

Even though Intel has been very beat up we still remain concerned about how they get out of the current predicament and differentiate from AMD. AMD stock has done well at Intel's expense but is stuck in a similar technology / market trap that has good short term dynamics but less so longer term. We think Apple's move to its own processors will be much faster than expected . Why in the world would I buy a dead end architecture? This could help margins even more. A faster move obviously benefits them. Levering semiconductors further is currently just a dream but a pretty good one that could easily be executed and makes sense especially in Apple's quest for growth as its a market that could move the needle even for them. Sometimes its better to be lucky than smart. Apple’s timing couldn't be much better given COVID-19, work/school remotely and Intel falling on its own sword. The M1 chip introduction is likely to be a huge success. I've been waiting to buy one and now I'm convinced. [post_title] => Is Apple the Most Valuable Semiconductor Company in the World? [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => is-apple-the-most-valuable-semiconductor-company-in-the-world [to_ping] => [pinged] => [post_modified] => 2020-11-25 21:47:32 [post_modified_gmt] => 2020-11-26 05:47:32 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=293309 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 3 [filter] => raw ) [3] => WP_Post Object ( [ID] => 293264 [post_author] => 13 [post_date] => 2020-11-24 10:00:01 [post_date_gmt] => 2020-11-24 18:00:01 [post_content] => The extremely popular RISC-V instruction set architecture (ISA) originally came from the Berkeley Architecture Research (BAR) group. BAR also developed several other key pieces of enabling technology that have helped RISC-V become so popular. Among these are Rocket Chip which serves as a RISC-V based SOC generator. It can generate multi-core systems with Rocket scalar cores, Z-Scale control processors, and a coherent memory system. The last item on that list, a coherent memory system, is an absolute necessity for these SOCs. Which brings us to another fascinating BAR project – TileLink. To cite BAR’s own description: Tile Link is a protocol designed to be a substrate for cache coherence transactions implementing a particular cache coherence policy within an on-chip memory hierarchy. [caption id="attachment_293265" align="aligncenter" width="969"]TileLink TileLink[/caption] Anyone building a RISC-V SOC, and perhaps many other kinds as well may want to include TileLink as the protocol for implementing memory coherence. It offers many features that make it an excellent choice. Truechip, a leading provider of verification intellectual property (VIP) has recently posted a webinar replay on TileLink and the VIP that True Chip provides to ensure system level compatibility with all the attached memory subsystem agents. The protocol is designed, when implemented properly, to prevent deadlocks. There are five unidirectional channels, each with a specified priority that makes this possible. TileLink can be used with clients that do not have their own cache or can be used to connect standalone caches to clients. Any arrangement of agents is allowed so long as they form an acyclic directed graph (DAG). The Truechip webinar goes through the details of the transactions on TileLink and explains the various options available for sharing data. TileLink supports data transfers with a size equivalent to the bus width, or multiple bus widths using what are called beats. Responses to operations are not necessarily ordered. The webinar also offers a comparison of TileLink with other potential interfaces such as AHB, Wishbone, AXI4, ACE and CHI. The Truechip VIP works by establishing a monitor that can observe master/slave communication and then connects to a scoreboard. When scaling up, the monitor can be connected to a cross bar to allow multiple slave/monitor environments. The VIP supports all three conformance levels, TL-UL, TL-UH and TL-C. The True Chip VIP supports complex network structures, so long as they conform to a DAG. All aspects of TileLink are parameterized to support any configuration. The Truechip VIP also supports permission transitions, busy and wait states, various memory maps, response generation & ordering. Truechip has developed their TruEYE™ graphical interface to assist in debugging and monitoring transactions. TruEYE™ offers tabular and graphical views. For instance, in the case of TileLink transactions, columns are set up with a timestamp, Channel, VALID, READY, SOURCE ADDRESS, OPCODE, PARAMETER, etc. Each transaction can be examined in detail. The test environment and test suite can include basic and directed protocol tests, random tests, error scenario tests, RAL tests, dynamic tests, and assertions & cover point tests. I recommend the webinar for anyone looking for more insight into building and verifying TileLink interfaces. RISC-V has changed the landscape for SOC design, making it possible to take robust and well-designed elements and build sophisticated SOCs. It’s nice to know that there is good support in the industry for these new specifications. True Chip has amazing wide support for many interfaces, including of course TileLink. The webinar and more information are available on the Truechip website www.truechip.net [post_title] => Webinar Replay on TileLink from Truechip [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => webinar-replay-on-tilelink-from-truechip [to_ping] => [pinged] => [post_modified] => 2020-11-22 19:37:58 [post_modified_gmt] => 2020-11-23 03:37:58 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=293264 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [4] => WP_Post Object ( [ID] => 293250 [post_author] => 16 [post_date] => 2020-11-24 06:00:31 [post_date_gmt] => 2020-11-24 14:00:31 [post_content] => Interpreting ISO 26262 without ambiguity is not always easy. Suppliers and integrators can read some aspects differently, creating confusion. Which is a problem since ISO 26262 has become so much a part of any discussion on automotive electronics that it has gained almost biblical significance. Yet most of us, even suppliers to the market, understand at best only what they have read in the document. I had a fascinating discussion with Kurt Shuler (VP Marketing at Arteris-IP) on the background to and challenges in interpretation in the standard. Kurt is a member on the technical advisory group to ISO 26262 and is extensively involved in safety management. He also has to advise Arteris-IP customers in their implementation to the standard. Hence his much better than average insight on this topic. Reality ISO 26262 Interpretation

The Origins of ISO 26262

Kurt started by talking about the origins of the standard, driven primarily by car and locomotive people, not electronics people. OEMs and Tier-1 people. Which is why semiconductor understanding in the first revision is not as deep as you might expect. It’s also a pretty hefty piece of work, almost 700 pages across 12 books. Those books were developed by multiple committees. Which means that, like the Bible, the standard sometimes contradicts itself. That makes for challenging conversations between suppliers and consumers in the value chain. Who is supposed to do what when you can’t agree on interpretation? To save his own sanity, Kurt developed a huge spreadsheet of notes to help him resolve confusion in customer debates.

The second edition of ISO 26262

The second edition of the standard cleaned up some issues. There were improvements in the main body of the document. They added a chapter 11 with guidelines and examples for semiconductors. But, as always, while some problems were fixed, some remained, and more were added. Kurt had to evolve his spreadsheet to incorporate the second edition changes. None of this should be a big surprise. Standards committees put a lot of work into putting out the best possible product. Experts build them, but they’re still fallible. They don’t have unbounded experience in all possible use-cases. Or in how others might interpret what they’ve written. There will always be problems and interpretation issues. For Kurt, these continue the work he has to put in to reaching agreement with clients on detailed interpretation.

Minding the gaps

The spreadsheet became kinda like his exegesis for the standard. A customer might say, “I read the standard. It says we have to do exactly this.” Kurt could check his spreadsheet and say, “Let me point you this statement part 11 where there’s an example. You should also look here in part 5, and this other section in part 10. When you look at those statements and examples together, this is why Arteris-IP has chosen this interpretation.” The customer would review these sections and most often agree. Kurt’s been doing this for a long time with a lot of customers. He has developed significant insight into the mostly commonly shared interpretations across many of the details. Which is important not only to resolve ambiguities. It’s also important to manage tradeoffs, say between specific numeric targets on coverage and expert judgement. Do you need to hit or exceed the numeric target every time or can you get close, and rely on expert judgment to bridge the gap? That sort of question has to be answered by a collective of experts: Kurt, experienced semi companies, Tier-1s and OEMs. Kurt’s spreadsheet has grown and grown.

Experience over enthusiasm

We all want to step up to ISO 26262, to demonstrate that our products are fully compliant. Absolutely with the best of intentions. But in some domains, enthusiasm and hard work alone are not enough. Integrators expect you to follow the standard, but they also want you to know what problems they may encounter in their handoffs. At those gaps in the standard. They want to lean on the experience of a partners who has worked through many years on multiple programs with multiple clients. Knowing proven bridges across areas of ambiguity, knowing rationales for why you might choose one way or another. This is irreplaceable. You can lean more about Arteris IP work in safety HERE. [post_title] => The Reality of ISO 26262 Interpretation. Experience Matters [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => the-reality-of-iso-26262-interpretation-experience-matters [to_ping] => [pinged] => [post_modified] => 2020-11-25 05:01:18 [post_modified_gmt] => 2020-11-25 13:01:18 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=293250 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [5] => WP_Post Object ( [ID] => 293303 [post_author] => 12 [post_date] => 2020-11-23 18:00:20 [post_date_gmt] => 2020-11-24 02:00:20 [post_content] => The third quarter 2020 semiconductor market totaled $114 billion, up 11.0% from second quarter 2020, according to World Semiconductor Trade Statistics (WSTS). The 3Q20 growth was the highest since 11.6% in 3Q16. The strong 3Q20 growth follows a 2.1% decline in 2Q20 versus 1Q20. The second quarter is normally a healthy growth quarter, averaging 4% over the last eight years. However, uncertainties due to the COVID-19 pandemic led to electronics companies cutting back on semiconductor purchases and some slowing of production. The strong 3Q20 market growth is due to electronics companies catching up to demand. Key markets for semiconductors have remained relatively strong despite the pandemic. The revenue of the top semiconductor companies reflects the strong 3Q20. The combined revenue growth of the top 14 companies was 10% in 3Q20 versus 2Q20. Intel and SK Hynix were exceptions, with revenue down 7.1% and 5.6% respectively. Seven of the companies saw revenue increases of over 20%. AMD had the strongest growth, up 45%, leading the company to claim the number 12 ranking. AMD’s growth was due to strong demand for PC, gaming, and data center products. MediaTek revenue increased 44%, driven by increased market share in smartphones overall and strong 5G growth. The outlook for the 4Q20 is mixed. Normally the fourth quarter semiconductor market is flat to down from the third quarter. Of the ten companies providing guidance, five expect 4Q20 revenues to increase over 3Q20 and five expect revenues to decline. STMicroelectronics is the most optimistic with 12.2% guidance and expected growth in all its product lines except RF communications. Micron Technology is the most pessimistic, projecting a 14.1% revenue decline due to weakness in demand in the enterprise segment. Intel is guiding for a 5.1% revenue decline due weakness in data center demand. Top Semiconductor Revenue 2020 The Memory companies (Samsung, SK Hynix, Micron and Kioxia) had modest combined 3Q20 revenue growth of 4%. The non-memory companies saw revenues increase 14%. Intel, at $18.3 billion in revenue, skews the combined results of the top 10 non-memory companies. Excluding Intel, the non-memory companies had combined 3Q20 revenue growth of 28%. Combined guidance for 4Q20 revenue growth is flat for the non-memory companies. Excluding Intel, the combined growth is 3%. The global economy is expected to bounce back in 2021 from a severe decline in 2020. Forecasts in the last month call for GDP to recover from a decline of 4% to 6% in 2020 to growth of 5% to 6% in 2021. The forecasts below were made before the announcement of successful COVID-19 vaccine phase 3 trials by Moderna, Pfizer, and AstraZeneca. Updated forecasts will most likely call for stronger GDP growth in 2021. World GDP Forecast 2020 2021 Third quarter data from IDC on two key semiconductor applications show an improving trend. PC units had a decline of 10% in 1Q20 versus a year earlier. The PC market has show strong growth since then, reaching 15% year-to-year in 3Q20. Smartphones had double-digit year-to-year declines in the first three quarters of 2020. 3Q20 recovered to only a 1% year-to-year decline. Smartphones should return to positive year-to-year growth in 4Q20. Unit Shipment 2020 Recent forecasts for semiconductor market growth in 2020 range from 3.3% to 5.5%. The forecasts made after 3Q20 WSTS data was available are 4.8% from the Cowan LRA model and 5.5% from us at Semiconductor Intelligence. With three quarters of 2020 data complete, it is safe to say the 2020 market growth will be somewhere between 4% and 6%. Semiconductor Market Forecasts 2020 Forecasts for the 2021 semiconductor market range from 4.2% from the Cowan LRA Model to 14% from Semiconductor Intelligence. The Cowan LRA Model is based on historical trends and does not include assumptions for the future. Our 14% forecast is based on the recent results and expectations of major semiconductor companies, expected strong global GDP growth in 2020, a strong PC market, and a recovering smartphone market. [post_title] => Semiconductor Boom in 2021 [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => semiconductor-boom-in-2021 [to_ping] => [pinged] => [post_modified] => 2020-11-25 05:01:53 [post_modified_gmt] => 2020-11-25 13:01:53 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=293303 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [6] => WP_Post Object ( [ID] => 293213 [post_author] => 11830 [post_date] => 2020-11-23 10:00:01 [post_date_gmt] => 2020-11-23 18:00:01 [post_content] =>

Webinar Menta is Breaking New Ground with eFPGA IP Using Adaptive DSPMenta is a unique embedded FPGA (eFPGA) company. Their eFPGA IP is based completely on standard cells provided by the foundry, the customer or a third party – no custom cells or custom cell characterization is needed. They also don’t require any specific library, process step or metal stack. All this makes Menta’s eFPGA IP easy to embed in a standard SoC design flow. The company went through several iterations of eFPGA architectures to arrive at the current approach. The process was driven by its customers. You can learn about Menta’s journey in an interview Dan Nenni did with Menta’s CEO here.  I recently had the opportunity to preview a new webinar from Menta that will be broadcast on December 15. Now, Menta is breaking new ground with eFPGA IP using adaptive DSP.

This unique adaptive DSP capability finds use in many applications, including AI, communication protocols, encryption, compression, interconnect fabrics and cybersecurity. Catherine Le Lan de Franssu, field application engineer at Menta, is the webinar presenter. She has a deep background in IC design and program management having worked at LSI Logic, Synopsys, TI and academia before joining Menta. She provides a very clear explanation of the unique and flexible DSP capability offered by Menta.

First, Catherine discusses the patented, flexible nature Menta’s eFPGA IP. The designer can define what is needed at a very granular level, including configurable lookup tables, memories from your vendor’s memory compiler, special customer-designed blocks, definition of I/O requirements (e.g., SPI, AHB, AXI, JTAG/scan chain) and a unique adaptive DSP capability. Catherine provides a lot of detail about the architecture of this DSP capability and how the designer can customize it. The configuration of registers and how pipelining can be used is also discussed.

The key goal of this adaptive DSP solution is to provide a wide range of options so the designer can choose the best hardware DSP architecture. For example, the ALU can range from 8 to 512 bits. DSP blocks can be cascaded, and the blocks can be dynamically reconfigured at each clock cycle if needed.

Catherine goes into a lot of detail about developing finite impulse response (FIR) algorithms with Menta’s adaptive FIR engine. The hardware architecture of the algorithm implementation can be tuned to hit the right performance or area target. The architecture supports from 4 to 512 taps for a FIR filter implementation.  A FIR generator automatically creates the RTL code for the target implementation.

Menta’s Origami user interface coordinates all this activity. Catherine explains how Origami generates all the files needed for pre-hardening and post hardening IP verification. She also explains some of the special capabilities of the DSP that make it highly testable.

Example implementations are then described. A 24X24 complex multiplier is covered in detail, including performance metrics. A 21-tap FIR filter implementation is also detailed using a 16-bit bus. The primary goal in this case is size and Catherine shows how to use the Oragami interface to achieve the required area.

The webinar concludes with a good Q&A session that covers many more features and capabilities of Menta’s DSP. If your next design will require DSP, I highly recommend you attend this webinar to see how Menta is breaking new ground with eFPGA IP using adaptive DSP. The webinar will be broadcast on Tuesday, December 15, 2020 at 10:00 AM PST. You can register for eFPGA IP Using Adaptive DSP here.

[post_title] => Webinar: Menta is Breaking New Ground with eFPGA IP Using Adaptive DSP [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => webinar-menta-is-breaking-new-ground-with-efpga-ip-using-adaptive-dsp [to_ping] => [pinged] => [post_modified] => 2020-11-22 15:23:23 [post_modified_gmt] => 2020-11-22 23:23:23 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=293213 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [7] => WP_Post Object ( [ID] => 293279 [post_author] => 28 [post_date] => 2020-11-23 06:00:09 [post_date_gmt] => 2020-11-23 14:00:09 [post_content] => With the announcement of early PDK availability for the 3nm GAA process node, designers are extremely interested in the characteristics of the new “gate-all-around” transistor structure and how it compares to the existing FinFET device.  The GAA transistor has been denoted as a (horizontal) nanowire or nanosheet. GAA FinFET I will talk to the EDA companies on what design challenges we can expect for the GAA process technology and what they have discovered thus far. SemiWiki will also cover the upcoming GAA related papers and announcements so stay tuned. To start I spoke with Aveek Sarkar, VP of Engineering at Synopsys. He is a 20+ year semiconductor professional splitting his time between Sun Microsystems, ANSYS, and Synopsys. Aveek's focus today is delivering a modern and open custom design platform that is changing the way analog and custom circuits are created. Given that Synopsys is an IP powerhouse with hundreds of internal designers using Synopsys tools, I felt this would be a good starting point. IP is the foundation of semiconductor design and is always first to a new process node. These questions are a follow-up to the press release Synopsys did with Samsung last month: Flow Leverages Innovative Synopsys Custom Design Platform Features to Streamline 3nm Analog and Mixed-Signal Design
Highlights:
  • Samsung and Synopsys collaboration will accelerate deployment of 3nm gate-all-around (GAA) process technology by designers of advanced applications
  • AMS Design Reference Flow provides complete methodology for analog/mixed-signal design at 3nm, including documented flows for design, layout, reliability analysis and signoff
  • Synopsys Custom Design Platform delivers industry-leading productivity for Samsung 3nm GAA design, including innovative features for reducing time to analog design closure
Quotes:
"With the Synopsys AMS Reference flow, designers can quickly deploy 3nm GAA technology for their most demanding applications, such as artificial intelligence, 5G networking, automotive, the Internet of Things and advanced data centers," said Sangyun Kim, vice president of Foundry Design Technology Team at Samsung Electronics. "The advanced methodologies enabled by Synopsys help our customers and internal IP developers to create analog and mixed-signal designs more efficiently." "In developing the 3nm GAA AMS Design Reference Flow, Samsung and Synopsys worked together to enable powerful techniques for shortening design cycles," said Aveek Sarkar, vice president of engineering at Synopsys. "As one example, the reference flow with Synopsys includes a novel solution for early electromigration analysis, which substantially shrinks design closure time."
Follow-up Questions:
What new Synopsys tool features were required in support of the Samsung 3GAA technology? From a tool feature POV, the change from FinFET to GAA was not as disruptive as the change from Planar to FinFET. However, we are finding with each new node there is a significant amount of “methodology tuning” that needs to take place. For this, we work together with our DesignWare IP development team to develop flows that work best for each new process. In the case of 3GAA, we believe that signoff quality early analysis of electrical effects has moved from a “nice to have” to an essential feature. A lot of our collaborative work with Samsung has been focused there. This includes in-design analysis of resistance, capacitance and electromigration during layout. What is “early” EM analysis, as mentioned in the press release? Early EM analysis is analysis that takes place before a given block of layout is finished. In a traditional flow, the layout team will finish a block so that it can go through a normal signoff flow – running LVS and extraction and then post-layout simulation and finally EM analysis. Fixing EM issues at this stage requires a lot of rework – to reduce current density on a path, you need to make room for the new routing resources. Our flow allows you to check for EM errors with signoff engines while layout is in progress. You are correct that analyzing EM for a net for self-heating effects requires that the underlying devices be placed first. We do include self-heating effects in our EM calculation. Early EM analysis is performed by layout designers during the interconnect process, so usually the related devices will be placed. Fundamentally, our goal is to “shift left” electrical analysis – finding electrical issues earlier in the design cycle – while using the full accuracy of the signoff tools. This delivers good correlation with the final signoff results even without fully completed layout. Besides early analysis, we also provide EM-aware routing that generates correct-by-construction connections. For more on the Synopsys Custom Design Platform, visit https://www.synopsys.com/custom.   [post_title] => EDA Tool Support for GAA Process Designs [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => eda-tool-support-for-gaa-process-designs [to_ping] => [pinged] => [post_modified] => 2020-11-24 09:31:15 [post_modified_gmt] => 2020-11-24 17:31:15 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=293279 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [8] => WP_Post Object ( [ID] => 293218 [post_author] => 6486 [post_date] => 2020-11-22 10:00:16 [post_date_gmt] => 2020-11-22 18:00:16 [post_content] => The semiconductor industry today is faced with several substantial issues—the continuing rise in design costs for complex SoCs, the decrease in the incidence of first-time-right designs and the increase in the design cycle time against shrinking market windows and decreasing product life cycles. An additional factor has now been added to SoC design costs with the emergence of complicated software applications intended to run on the SoC silicon. The costs of the software effort have outstripped the silicon design costs and have become the major part of the cost of these designs. IP integration is also a growing part of design costs. [caption id="attachment_293219" align="alignnone" width="2560"]AI Tools Blog 111820 Source: Semico Research Corp.[/caption] As happens often in our industry, the right solution surfaces at the right time. That solution is the incorporation of AI functionality into existing EDA tools as an aid to silicon and software designers and to make these designers more efficient and productive. While these tools will not solve every problem, they will allow for reasonable reductions in design costs and design cycle times. These improvements, by themselves, make the investments in these tools worthwhile and can immediately be impactful to the bottom lines of most companies. The use of EDA tools with AI functionality can greatly alter the trajectory of the design effort and later, the introduction to the market of products designed with these tools. The current trend in the EDA market for tools with AI functionality is to make designers more productive and efficient, acting as aids in the design process. A possibility for the future through the continuous learning capabilities of AI is to make suggestions to designers on better methods of doing their designs. The aim here is not to replace the designer, but to improve and expand the capabilities and expertise of the designers. This trend will also extend to the writing of the software applications that accompany the silicon solution. ‘Human-in-the-Loop’ is going to be trend for many years to come. Decreased design cycle times and reduced design costs may prompt some companies to undertake more designs in the same time they had done only one or two before. While this may be possible, overall market conditions and requirements will ultimately dictate the behavior of companies in this area. In certain instances, a market share battle between competitors may ensue, but will be ill-advised if not managed correctly. Currently AI functionality is being added to EDA tools in the form of add-on modules. This is both the fastest and most cost-effective method of deploying these capabilities in the short term. The idea is to make the existing tools better with the least amount of disruption. However, Semico believes this will be temporary. We believe that most companies will eventually re-architect their tools to incorporate the AI functionality as a standard feature. It is difficult to imagine any designer not wanting to use tools that are more efficient, faster, more accurate and deliver more cost-effective solutions. No doubt, marketing departments will be working overtime to determine what works and what doesn’t. What customers do and don’t want as part of the tools to incorporate into their deign flows. This will take some time to ascertain and efforts to build the tools from the ground up, incorporating AI functionality as standard features will then follow quickly. Until then, the add-on module approach would seem to be the most effective and economical. Semico is currently forecasting that the penetration rate for AI-enabled EDA tools will be at least 47.8% by 2025. This rate could be higher but will be gated by several factors:
  • Tool cost and availability from major vendors
  • Compatibility with existing tools
  • Breadth of coverage of different aspects of the design flow
  • Efficiency and Efficacy
Our view is that the introduction of AI-enabled EDA tools represents a leap forward in semiconductor design solutions and technology. In a typically semiconductor industry-focused approach, we are going to use a newer technology – AI enabled EDA tools, to solve another persistent problem caused by technology – rising device complexity levels causing escalating design costs and increasing design cycle times. Finally, Semico believes that the future is bright for companies that can deliver the right solutions at the right time and AI-focused EDA tools enable this goal brilliantly. Semico has recently written a report covering this topic; New Directions in the EDA Market: Designing with AI Tools, SC109-20 October, 2020 Here is a link to the Table of Contents on our website: https://semico.com/content/new-directions-eda-market-designing-ai-tools [post_title] => The Impact of AI-enabled EDA Tools on the Semiconductor Industry [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => the-impact-of-ai-enabled-eda-tools-on-the-semiconductor-industry [to_ping] => [pinged] => [post_modified] => 2020-11-24 11:31:36 [post_modified_gmt] => 2020-11-24 19:31:36 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=293218 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 2 [filter] => raw ) [9] => WP_Post Object ( [ID] => 293256 [post_author] => 19 [post_date] => 2020-11-22 06:00:59 [post_date_gmt] => 2020-11-22 14:00:59 [post_content] => DoorDash IPO Spins COVID 19 Impact The outlook for DoorDash’s highly anticipated public offering announced last week is inextricably bound up in the impact of the COVID-19 pandemic. It seems that the worse the COVID-19 pandemic becomes, the better the IPO circumstances look for DoorDash, but that's not exactly how DoorDash tells the tale. DoorDash filed its S-1 with the Securities and Exchange Commission on November 13th, just days after Pfizer announced that early tests of a COVID-19 vaccine it developed with BioNTech had prevented infection in some trial subjects. Curiously, DoorDash failed to mention the potential negative impact of the creation of an effective COVID-19 vaccine in its risk factors. DoorDash S-1: https://www.sec.gov/Archives/edgar/data/1792789/000119312520292381/d752207ds1.htm In the S-1, DoorDash acknowledges the existence of the pandemic: “Prior to the pandemic, we played a significant role in connecting merchants to new consumers and driving incremental sales, providing selection, experience, and value to consumers, and offering economic opportunity to those looking for income. With the pandemic, our platform has become a lifeline for merchants whose only revenue options are take-out and delivery, for consumers sheltering in place, particularly vulnerable populations whose health depends on isolating, and for many of the millions of newly unemployed in need of earnings opportunities.” That lifeline translated to $1.9B in revenue for the nine months ended Sept. 30, 2020, vs. $885M in the same period in 2019 and a net loss of $149M (in 2020) vs. $667M in 2019. It's no secret that even before the pandemic food delivery companies like DoorDash, Grubhub, and Uber Eats had already established contentious relationships with restaurants by wielding their demand creation leverage and grabbing what some considered an unfair share of the service price. In a post-COVID-19 world, food delivery partners became even more important to restaurants operating without dining rooms - with a corresponding increase in leverage. The long and the short of the matter is that DoorDash remains a loss-spinning venture in spite of its COVID-19 infused success. That success appears to be increasingly built upon the misfortune of others – including the 1M "dashers" (many of whom may have become newly unemployed) and 390,000 merchants (newly dependent upon delivery services) on the platform. The company claims 18M users. DoorDash is leveraging the advantages of its platform including demand creation, service expansion, and “operational excellence” to consolidate the food delivery business and expand into non-food sectors. The company claims 50% market share in the space, so the consolidation is proceeding quite well in the face of what it acknowledges is intense competition. DoorDash was and is targeting the shift toward “dine-in and delivery meals.” The company cites Pre-COVID-19 estimates that the shift to “off-premise consumption” has created a $302.6B market opportunity. Precisely what that opportunity looks like Post-COVID-19 is unclear. DoorDash says, in its S-1: “Fifty-eight percent of all adults and 70% of millennials say that they are more likely to have restaurant food delivered than they were two years ago, and we believe the COVID-19 pandemic has further accelerated these trends.” What DoorDash fails to note is that what COVID-19 giveth (increased demand), COVID-19 taketh away (100,000 restaurants – 1 out of every 6 – closed). In its risk factors, DoorDash has one concern regarding COVID-19: “The COVID-19 pandemic, or a similar public health threat, could adversely affect our business, financial condition, and results of operations.” More significantly, DoorDash might actually be vulnerable to a mitigation of the pandemic via the highly anticipated Pfizer vaccine or other means. Sadly, DoorDash’s prospects will dim in direct proportion to the speed of the recovery from the pandemic. DoorDash notes the acceleration of dine-in trends from the pandemic, but remains mute on how permanent or impermanent these impacts may be. DoorDash also fails to note the emergence and evolution of food delivery as “ghost kitchens” – i.e. delivery-only – restaurants emerge that may operate their own delivery services – not unlike pizzerias. And what about the corollary reality of shut in diners that are desperate to once again eat in the wild. Visiting restaurants during the pandemic has suddenly become an exotic, special occasion. The restaurants near where I live that have managed to remain open are busy – even at the height of the pandemic – even with curbside pickup stations. When the COVID-19 fever lifts, an entirely new food service marketplace will emerge with new accommodations and business models that may favor or disadvantage DoorDash. But one thing is clear. DoorDash should more honestly disclose the risks to its business. The successful creation and distribution of a COVID-19 vaccine is a real risk factor – as is better COVID-19 behavior by the general public that may lead to a relaxing of restrictions. While food delivery service can be great – or sometimes disappointing – if we all wear masks and socially distance maybe all this food delivery won’t be so essential. Judging by the animated diners I see when I infrequently go out to eat these days, it’s clear that humans are social animals. Sitting isolated in our private caves is not the wave of the future. [post_title] => DoorDash IPO Spins COVID-19 Impact [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => doordash-ipo-spins-covid-19-impact [to_ping] => [pinged] => [post_modified] => 2020-11-24 09:38:53 [post_modified_gmt] => 2020-11-24 17:38:53 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=293256 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 1 [filter] => raw ) ) [post_count] => 10 [current_post] => -1 [in_the_loop] => [post] => WP_Post Object ( [ID] => 293363 [post_author] => 14 [post_date] => 2020-11-25 10:00:46 [post_date_gmt] => 2020-11-25 18:00:46 [post_content] => - Tsinghua $198M Bond Bust - Good for memory: Samsung Micron LG Toshiba - - Not good for chip equipment - Could China Credit Crunch hit more than foundry embargo? - Damage to China memory positive for other memory makers - Not good for chip equip if customers can't get money China Semiconductor Bond Bust China's most prestigious leader of the effort to become dominant in semiconductors suffered an embarrassment of defaulting on $198M in bonds that were due Nov 17th. While seemingly a drop in the bucket of overall debt and the fact that they were in the midst of negotiating their way out it still sends shivers through China's debt market and sent the bonds plummeting. Tsinghua is not the only state backed Chinese firm with bond troubles which makes the concerns all the more worrisome.

Chinese tech group joins list of companies to default on bond issue

NAND in Wuhan and DRAM in Chongqing Tsinghua already has a NAND factory in otherwise famous Wuhan and is planning a DRAM fab in Chongqing. They are a spinoff subsidiary of the prestigious Bejing University. They are perhaps the shining star of China's semiconductor aspirations. Though SMIC has been around a long time it seemed Tsinghua had more potential. Tsinghua Unigroup default tests China's chipmaking ambitions

Good for non Chinese memory makers like Samsung & Micron, LG & Toshiba

Being in the memory market and having the specter of China entering your market after watching China annihilate the LED & solar cell markets was likely quite chilling. China obviously doesn't care about profitability (at least not in the beginning) and could easily trash pricing and destroy the commodity memory market just like the commodity LED and solar markets before it. If I were in Boise I might have a little schadenfreude about the Chinese bond market right now, not unlike TSMC and SMIC. Anything that slows down China's aspirations in the memory market is likely positive for other competitors. Equipment vendors likely between a rock and a hard place in China Checking accounts receivable. Semiconductor equipment makers may not be as happy about the bond default and subsequent credit downgrades. We would bet a lot of money that the equipment makers are likely owed a whole lot more than $198M in equipment purchases and are looking at many times that in future orders and business. So their exposure far exceeds the bondholders. Unlike the bondholders, equipment makers don't want to stop shipping to their biggest, best and fastest growing market, that is China. If equipment makers stop shipping due to credit risk/downgrades or fear of not getting paid then Tsinghua will avoid doing business with them at all costs (its not like there aren't trying to avoid American equipment already given what happened to their cousins at SMIC). Equipment vendors have to keep shipping with the hope that the Chinese government will be the backstop, or the company figures it out. We can only imagine that some CFO's have to be checking their Tsinghua related accounts receivable exposure.

Credit is all about faith Too big/important to fail?

Lest anyone forget, the credit market is all about faith. Faith in getting paid back on the loan. The 2008/2009 market collapse was a collapse in the credit market. Faith in ever getting repaid went to zero. The semiconductor industry is very highly capital intensive and very fickle in cyclical profitability. In addition the would be Chinese chip makers are likely finding out that the semiconductor market is much, much harder than the LED and solar markets which were relative pushovers. The cost of an LED "fab" and complexity of process is not even a rounding error as compared to making a 128 level NAND chip. It is likely that getting to yield, meaning getting to revenue, let alone profitability will likely be a lot longer and a lot harder than many in China likely anticipated after the cakewalk in LED and solar. This means that many Chinese firms could have miscalculated when they would have been able to pay back debt and could find themselves in a cash crunch needing to extend credit terms out some more years/months. We don't know what caused Tsinghua's issue but breaking the faith was not good as their bonds fell all the way down to 68 cents on the dollar at one point. (we don't think equipment vendors would like to take 68 cents on the dollar owed them). In the end, Tsinghua, like some US financial firms in 2008/9, is too big/important to fail and the Chinese government will step in at some point. The question is when and how and who will get hurt in the collateral damage

Could the US administer a "Coup de Grace"? Part of the outgoing, "Scorched earth" policy

It is abundantly clear that the outgoing administration has embarked on a scorched earth policy for various reasons. Much of the scorched earth has been directed at international relations such as potentially attacking Iran, recalling troops and trying to make good on other campaign promises. Trade with China has been talked about as one such target. The SMIC embargo, announced shortly before the election certainly was effective at hurting China's chip ambition. Could the embargo be extended to memory, which is certainly capable of potential military "dual use technology" as a parting shot on the way out the door? Or maybe a blanket embargo? If there were a time to hurt China, the lame duck session is it.

The stocks

Most all semi stocks have been super hot as demand continues to be strong. The Tsinghua news is mildly positive for other memory makers as it will likely weaken and or slow China's memory ambitions and ability to crush memory pricing. It is likely not all that negative for equipment companies as they have even survived the SMIC embargo without so much as a scratch. If anything, it may be a hidden positive as it will likely moderate memory spending which drives the notorious boom bust cycles in memory. TSMC continues to be a huge winner. Micron seems in fine shape as well and would be happy to see Tsinghua go the way of Jinhua, even though we don't think that will happen. Equipment companies may see a hiccup or two in revenue recognition but not likely more than that unless things really go off the tracks, like the US upping the ante. While a possibility, we think the administration seems too pre-occupied with other fights with too little time left on the clock. [post_title] => China Semiconductor Bond Bust! [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => china-semiconductor-bond-bust [to_ping] => [pinged] => [post_modified] => 2020-11-25 17:38:51 [post_modified_gmt] => 2020-11-26 01:38:51 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=293363 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [comment_count] => 0 [current_comment] => -1 [found_posts] => 7358 [max_num_pages] => 736 [max_num_comment_pages] => 0 [is_single] => [is_preview] => [is_page] => [is_archive] => [is_date] => [is_year] => [is_month] => [is_day] => [is_time] => [is_author] => [is_category] => [is_tag] => [is_tax] => [is_search] => [is_feed] => [is_comment_feed] => [is_trackback] => [is_home] => 1 [is_privacy_policy] => [is_404] => [is_embed] => [is_paged] => [is_admin] => [is_attachment] => [is_singular] => [is_robots] => [is_favicon] => [is_posts_page] => [is_post_type_archive] => [query_vars_hash:WP_Query:private] => 443e714a5290f77b0df02e2f78f50560 [query_vars_changed:WP_Query:private] => [thumbnails_cached] => [stopwords:WP_Query:private] => [compat_fields:WP_Query:private] => Array ( [0] => query_vars_hash [1] => query_vars_changed ) [compat_methods:WP_Query:private] => Array ( [0] => init_query_flags [1] => parse_tax_query ) [tribe_is_event] => [tribe_is_multi_posttype] => [tribe_is_event_category] => [tribe_is_event_venue] => [tribe_is_event_organizer] => [tribe_is_event_query] => [tribe_is_past] => [tribe_controller] => Tribe\Events\Views\V2\Query\Event_Query_Controller Object ( [filtering_query:protected] => WP_Query Object *RECURSION* ) )

China Semiconductor Bond Bust!

China Semiconductor Bond Bust!
by Robert Maire on 11-25-2020 at 10:00 am

China Semiconductor Bond Bust

– Tsinghua $198M Bond Bust
– Good for memory: Samsung Micron LG Toshiba –
– Not good for chip equipment
– Could China Credit Crunch hit more than foundry embargo?
– Damage to China memory positive for other memory makers
– Not good for chip equip if customers can’t get money

China’s… Read More


Cadence is Making Floorplanning Easier by Changing the Rules

Cadence is Making Floorplanning Easier by Changing the Rules
by Mike Gianfagna on 11-25-2020 at 8:00 am

Mixed placement floorplan

SoC designs are getting more complex, resulting in a higher level of difficulty to get anything done. This trend is well-known. What I want to focus on here is how to deal with the issue of complexity. There are many approaches to taming this problem — faster algorithms for one, and improved algorithm efficiency or the ability to run… Read More


Is Apple the Most Valuable Semiconductor Company in the World?

Is Apple the Most Valuable Semiconductor Company in the World?
by Robert Maire on 11-25-2020 at 6:00 am

Apple M1

– The new M1 chip unveils previously hidden asset
– Could/should Apple sell semiconductors?
– Are servers next?
– The M1 chip appears to be a rousing success and the beginning of a new era

Essentially 100% of all early reports on the performance of the M1 chip have come back with stellar reviews. Great performance… Read More


Webinar Replay on TileLink from Truechip

Webinar Replay on TileLink from Truechip
by Tom Simon on 11-24-2020 at 10:00 am

TileLink

The extremely popular RISC-V instruction set architecture (ISA) originally came from the Berkeley Architecture Research (BAR) group. BAR also developed several other key pieces of enabling technology that have helped RISC-V become so popular. Among these are Rocket Chip which serves as a RISC-V based SOC generator. It can … Read More


The Reality of ISO 26262 Interpretation. Experience Matters

The Reality of ISO 26262 Interpretation. Experience Matters
by Bernard Murphy on 11-24-2020 at 6:00 am

Man scratching head min

Interpreting ISO 26262 without ambiguity is not always easy. Suppliers and integrators can read some aspects differently, creating confusion. Which is a problem since ISO 26262 has become so much a part of any discussion on automotive electronics that it has gained almost biblical significance. Yet most of us, even suppliers… Read More


Semiconductor Boom in 2021

Semiconductor Boom in 2021
by Bill Jewell on 11-23-2020 at 6:00 pm

Top Semiconductor Revenue 2020

The third quarter 2020 semiconductor market totaled $114 billion, up 11.0% from second quarter 2020, according to World Semiconductor Trade Statistics (WSTS). The 3Q20 growth was the highest since 11.6% in 3Q16. The strong 3Q20 growth follows a 2.1% decline in 2Q20 versus 1Q20. The second quarter is normally a healthy growth … Read More


Webinar: Menta is Breaking New Ground with eFPGA IP Using Adaptive DSP

Webinar: Menta is Breaking New Ground with eFPGA IP Using Adaptive DSP
by Mike Gianfagna on 11-23-2020 at 10:00 am

Webinar Menta is Breaking New Ground with eFPGA IP Using Adaptive DSP

Menta is a unique embedded FPGA (eFPGA) company. Their eFPGA IP is based completely on standard cells provided by the foundry, the customer or a third party – no custom cells or custom cell characterization is needed. They also don’t require any specific library, process step or metal stack. All this makes Menta’s eFPGA IP easy to… Read More


EDA Tool Support for GAA Process Designs

EDA Tool Support for GAA Process Designs
by Daniel Nenni on 11-23-2020 at 6:00 am

GAA FinFET

With the announcement of early PDK availability for the 3nm GAA process node, designers are extremely interested in the characteristics of the new “gate-all-around” transistor structure and how it compares to the existing FinFET device.  The GAA transistor has been denoted as a (horizontal) nanowire or nanosheet.

I will talk… Read More


The Impact of AI-enabled EDA Tools on the Semiconductor Industry

The Impact of AI-enabled EDA Tools on the Semiconductor Industry
by Richard Wawrzyniak on 11-22-2020 at 10:00 am

AI Tools Blog 111820

The semiconductor industry today is faced with several substantial issues—the continuing rise in design costs for complex SoCs, the decrease in the incidence of first-time-right designs and the increase in the design cycle time against shrinking market windows and decreasing product life cycles. An additional factor has … Read More


DoorDash IPO Spins COVID-19 Impact

DoorDash IPO Spins COVID-19 Impact
by Roger C. Lanctot on 11-22-2020 at 6:00 am

DoorDash IPO Spins COVID 19 Impact

The outlook for DoorDash’s highly anticipated public offering announced last week is inextricably bound up in the impact of the COVID-19 pandemic. It seems that the worse the COVID-19 pandemic becomes, the better the IPO circumstances look for DoorDash, but that’s not exactly how DoorDash tells the tale.

DoorDash filed… Read More