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Parasitic Interconnect Cross-Probing[/caption]
An engineer can then find which nets are the heaviest loaded, and Sujit ran a pre-built script that allowed him to filter and remove all capacitors below a threshold value.
A SPICE netlist was loaded, and we viewed the MOS transistors, along with some parasitic capacitors:
[caption id="attachment_284119" align="alignnone" width="850"]
SPICE netlist[/caption]
Next, we wanted to know what had changed in a SPICE netlist over time, so a DIFF script quickly highlight where the differences were located by showing that net n6 was modified:
[caption id="attachment_284120" align="alignnone" width="850"]
Net n6 was modified[/caption]
StarVision Pro comes with some 100 scripts, so I got the idea that they had automated most debugging tasks for me, saving me time from having to write my own scripts. Of course, you can always just view the Tcl source code for the scripts, and create new derivatives and combinations to make your debugging happen faster.
Videos
On YouTube there's a channel for EDA Direct, and they've recorded over a dozen intro videos on specific StarVision Pro topics, and each video is brief at under 2 minutes of viewing time:
Blocking chip sales to Huawei back on front burner
Covid19 & China Trade are equally bad
Long lived Uncertainty could "plague" industry sales going forward
Political Predictability worse than Disease Predictability
Reuters broke a story today that the proposed licensing of chip equipment to prevent "bad actors" getting chips made on US equipment was back on again, after many, including ourselves, thought it was a dead issue at least during Covid19.
Reuters Article on Chip Equip Blockade
Apparently at a meeting yesterday, cabinet officals agreed to change the "Foreign Direct Products Rule" such that licenses would be required by foreign users of US technology which would allow the US to prevent "bad actors" (read that as Huawei) from getting chips made on US chip equipment (AMAT, LRCX. KLAC et al) or equipment using US technology (ASML).
This rule change still needs presidential approval and Trump has previously been hesitant to support this but in light of the current bad relations with China over Covid19 his tune may have changed.
We were both right and wrong...very bad luck
We had joked in a prior note that:
"It would be a case of very bad luck if just when we start to get over the pandemic that the government would step in and halt sales that just restarted.......
Like getting over a bad case of the flu only to walk outside and get hit by a truck...."
Haircut becomes Crewcut - March 10th
We were also wrong in our most recent note in which we suggested that it it would be crazy and unthinkable that the administration would go forward with the blockade.
"We think the likelihood of that happening any time soon is just about zero as the US can't do anything to upset China as China supplies 90% of our pharmaceuticals, the majority of our PPE (personal protective equipment) like masks, and probably a lot of ventilators."
Covid19 Cycle
I guess we don't care if China cuts off our supply of medicine or PPE or ventilators at the worst possible time in retribution for us cutting off Huawei......
The only take away thats clear is that the predictability of Covid19 is better than the predictability of politics which remains a loose, wild cannon....
Embargo collision course with Taiwan and TSMC
Back in February when the embargo discussions hit a high note we talked about the collision course we were setting ourselves up for with Taiwan and TSMC...
China Chip Equip Embargo
We are now obviously back on that collision course and will be taking some of our allies along with us form the ride wether they like it or not. Most notably will be the Netherlands and ASML which did not ship an EUV tool to China due to pressure from the US.
The proposed rule change also includes equipment made with US technology which is a clear definition of ASML's EUV tools as the heart and soul of the tool is the EUV source invented and made in the USA by former Cymer in San Diego.
At the time of the sale of Cymer to ASML there were security concerns and we could imagine that there may have been secret agreements or assurances about control of that technology that were agreed to in order to win approval of that deal.
Aside from the collision course with TSMC the rule could essentially halt all equipment sales to China as there would be no way that a Chinese chip making company would agree to not sell to Huawei (let alone TSMC).
We would be back to a virtual death sentence for Chinese Chip companies much like the now dead and buried Jinhua.
But the collateral damage would be putting US equipment makers in the intensive care unit as China is the fastest growing and most significant part of their business.
Where would this put the US vis a vis Taiwan?
TSMC is the crown jewel of Taiwan which remains a short boat ride away from China and between a rock and a hard place.
Much as China was very upset with the Netherlands over the ASML EUV embargo, China would absolutely freak out if Taiwan stopped selling critical, 5G chips to Huawei. It would be much worse than a slap in the face.
Obviously things could quickly cascade into a very bad nightmare scenario with China retaliating and halting medical sales to the US or something similarly critical.
Starting another plague to add to the first
It seems as if the timing couldn't be much worse, just as the economy is in a free fall lets cut off chip equipment sales to China and start another trade war.
We hope this is political posturing or something similar. The problem is that we are concerned with the current rhetoric involving China and Covid19 and the need for someone to blame and retaliate against to generate support and re-direct angst.
But as we have previously mentioned, California is not high on the list of the current administrations supporters and most chip equipment companies are there so there may be less concern about the collateral damage generated by opening a second front of a war with China.
Stocks hate uncertainty
It is always the case that investors hate uncertainty more than almost anything else. Even more uncertainty than Covid19 has just been added to chip equipment stocks at just the worst time.
Its hard to image the stocks getting any more unstable than they already are but this embargo could easily be it.
With the stock wildly gyrating up and down 5% and 10% mper day with little stability in sight let alone a firm bottom, we are hard pressed to get back in even though the stocks are relatively cheap.
The problem is that they could get cheaper and the China embargo could go on much, much longer , long after Covid19 is a distant memory.
[post_title] => Newsflash Chip Equip Blockade back on!
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In short, they were both very, very hard to beat. Around 2013, there was a disruption in The Force and things started to change. First, Avago bought LSI. Then there were more acquisitions, with LSI ultimately being deep inside a large, substantial and diversified company called Broadcom. Singular focus on ASICs is hard to accomplish in such an environment. Two years later, GLOBALFOUNDRIES (GF) acquired IBM Microelectronics. Did that make GF a foundry, an ASIC vendor or both? There was debate on that topic. Then, three years later GF spun out its custom silicon business (the IBM part) as Avera Semiconductor. Then, last year Marvell acquired Avera.
All this churn created a void in the ASIC market. At eSilicon, we heard the same thing from many customers – they were looking for a dedicated, focused ASIC company that had the IP, the right technology experience, a strong production track record and a willingness to be a partner to build game-changing, critically needed custom chips. Thanks to its deep expertise in 2.5D packaging and complex digital designs, eSilicon became a tier-1 ASIC supplier for the data center, high-performance networking, AI and 5G markets to help fill that void. A few months ago, eSilicon was acquired by Inphi with certain assets sold to Synopsys.
Late last year Dan Nenni posted a discussion on this topic, Where has the ASIC Business Gone? In that post, Dan referenced DELTA Microelectronics, a company with a specific focus on ASIC. Then last month, Presto Engineering acquired DELTA. I’ll discuss the relevance of these events in my next post on this topic. For now, I would like to catalog what it takes to be a contender to fill an ASIC void:
It is a demand driven downturn - harder to predict
It may not be "business as usual" after this virus
What systemic changes could the industry face?
Trying to figure out another cycle-driven by inorganic catalyst
Investors and industry participants in the semiconductor industry who are used to normal cyclical behavior of over and under supply driven by factors emanating from the technology industry itself now have to try to figure out the impact of an external damper unlike any we have previously seen.
We are truly in uncharted waters as the tech industry in general has continued to grow, perhaps at varying rates, but we haven't seen a broad based, global downturn such as we may be in line for. Many would point to the economic crisis of 2008/2009 which was certainly negative but does not have the same "off a cliff with no skid marks" that the current global crisis has for its sudden sharp drop.
We would also point out that the semiconductor industry is famous for self inflicted cycles based on over supply from building way too much capacity. In fact we would argue that most chip cycles are self inflicted and most are supply side initiated.
The COVID-19 cycle is demand based as we haven't had a sudden change in global chip capacity, as fabs have kept running but we can expect a demand drop that has yet to fully manifest itself.
Technology is always the first to get whacked
When the economy goes south, technology buys are the first to suffer. Consumers continue to buy food, shelter, fuel and guns & ammo but don't buy the next gen Iphone or bigger flat screen. 5G can wait while I put food on the table. Given that smart phones are nothing more than containers of silicon, its clear that the chip industry will get it in the neck.
There are also a lot of other things in addition to the virus such as the oil market issues and the election which has all but been forgotten about. The effects on the technology market will persist long after the virus has been arrested and controlled.
There was a baseline assumption at one time that all the economic damage associated with COVID-19 would certainly be contained within the calendar year such that any business delayed by the virus out of H1 would just make H2 of 2020 that much stronger and it would all be a "wash" on an annualized basis.
The current trajectory as to the the length and depth of the "COVID-19 Chip Cycle" is unknown as to whether it is "V", "U" or "L" shaped. Right now it feels at least like a "U" if not an extended "U" shape (a canoe...).
The chip industry was barely a quarter out of a "U" shaped memory driven down cycle, having been pulled out by technology spending on the foundry/logic side when we were ambushed by COVID-19.
Two types of spending cycles; Technology & Capacity
There are two types of spending cycles in the chip industry, technology driven spending versus capacity driven spending. Capacity driven spending is the bigger part and technology spend is more consistent.
The industry has been on a technology driven spending recovery that was just about to turn on a capacity driven push. While we think that technology driven spending to sustain Moore's Law and 5NM/3NM will continue, we think that capacity spending will likely slow again, especially on the memory side as a drop in demand will get us back into an oversupply condition that we were just starting to emerge from.
The supply/demand balance in the chip industry remains a somewhat delicate balancing act and the COVID-19 elephant just jumped on one side.
One could argue that foundry/logic which has been the driver of the current recovery could falter as 5G, which is a big demand driver, is a "nice to have" not a "gotta have" as we could see 5G phone demand slow before the Iphone 12 ever launches.
On the plus side, work from home and remote learning for schools is clearly stressing demand for server capacity and overall cloud services which should bode well for Intel and AMD and associated chip companies
China Chip Equipment embargo likely off the table for now
At one point, not too long ago, it felt like we were only days away from imposing severe restrictions and licenses on the export of technology that could help China with 5G, such as semiconductor equipment.
We think the likelihood of that happening any time soon is just about zero as the US can't do anything to upset China as China supplies 90% of our pharmaceuticals, the majority of our PPE (personal protective equipment) like masks, and probably a lot of ventilators.
Politicians have bigger fish to fry with fighting over a trillion dollars of a rescue package and pointing fingers at one another. So at least COVID-19 has crowded out other things we had to worry about in the chip industry. Probably no one cares if the Chinese dominate 5G as there won't be a lot of demand to dominate.
There may be permanent systemic changes
There is a lot of complaining about corporate "bailouts", stock buy backs, executive pay etc; associated with any financial rescue package. While much of this may be focused on airlines and other more directly impacted industries, even if the chip industry never gets a dime of bailout money there will likely be increased scrutiny on corporate behavior in general and there could even be some legislation associated with it.
Buy backs which have become very big in the chip industry during good times may become less popular. We would not be surprised to see an increased focus on semiconductor manufacturing moving to Asia as people have figured out we don't even make our own pharmaceuticals any more.
Is an out sourced global supply chain a bad thing?
The technology industry has prided itself on how far and wide the supply chain for a technology can be. An Iphone is perhaps a poster child for supply chain logistics.
The problem is that broad and wide supply chains have been exposed as our soft underbelly, during COVID-19, that make us more susceptible to interruptions, even in some far away place, that can completely shut us down.
These supply chains work like dominoes that can cause a cascading effect to bring things to a halt.
Truly multinational companies that rely on the free movement of people and goods across borders with no friction might think twice about how they will deal with another global crisis as there is a high likelihood we will experience another one....not a question of if but rather when. That we haven't had a global disruption like COVID-19 before is probably just pure luck.
Boards of large companies will start to ask and demand for plans to deal with global disruption just as they have local contingency plans today to deal with local disasters.
Will the world get less interconnected?
Maybe moving back to a more vertically integrated, local model is safer albeit a little more expensive. There is likely some political will for more isolationist economic behavior after COVID-19 is over.
The semiconductor industry in the US is a shell of its former self as most production and much technology has been off shored with the primary driver being economic savings which mean less when you can't produce anything.
Balance sheet safety
We would point out that the semiconductor industry does seem to be relatively flush with cash as compared to cycles past. However there are some companies in the space that have a significant amount of debt (in some cases more than their cash) on their balance sheet.
The US has over 7 Trillion dollars in corporate debt, now more than ever, and about a third of our GDP. In previous cycles in the chip industry we have seen some companies go under due to debt load.
The popular model to lever up balance sheets with debt could potentially reverse itself as there are a long list of companies that will have their hand out for the government bailouts.
If we slow down buy backs, getting out of debt should be easy for most but there still are some that are deeply in debt, just a little less so in the semiconductor industry.
There are a handful of companies that could see COVID-19 related weakness push them closer to debt problems
M&A rebound?
Could we see the government loosen up its dislike of corporate mergers. If companies make the argument that getting together makes them stronger and more resistant to global issues then we could see a few more larger mergers happening under the right circumstances. There is probably not a lot left in the semiconductor industry but there are a few deals that didn't happen that could be revisited....after all , valuations are a lot more attractive now, especially for those companies that have dry powder in the form of cash.
Stock valuations are attractive
We are seeing stock valuations that are now looking attractive on a P/E basis much as the stocks were getting too expensive just a couple of months ago.
We are seeing multiple contraction rather than expansion as some stocks are discounting an unrealistic level of contraction much as they were previously discounting too bright a future. Much of the sentiment will be determined on Q1 conference calls which are coming up. If we were management, we would probably take a very conservative view as going out on a limb will not likely be rewarded.
Investors also want to see a company reset expectations in one swoop rather than a death by a thousand cuts over the next few quarters
Investors will want some sort of comfort that we are at or near a COVID-19 bottom even though that may not be the real case... just lie to me and make me feel better.....
[post_title] => COVID-19 Chip Cycle - How deep, long and what shape?
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[post_content] => It’s a matter of pride to me and many others from Atrenta days that the brand we built in SpyGlass has been so enduring. It seems that pretty much anyone who thinks of static RTL checking thinks SpyGlass. Even after Synopsys acquired Atrenta, they kept the name as-is, I’m sure because the brand recognition was so valuable.
Even good things must evolve. Synopsys verification has a strong “VC” brand and it was natural that SpyGlass should fold in under this, still with a strong connection to its founding identity. So now we have VC SpyGlass, in line with VC LP and VC Formal.
This isn’t just a rebranding. Synopsys have put a lot of work into this next generation SpyGlass, including 3X performance increase in half the memory, always a plus in any context and especially valuable when you want to screen full-chip RTL. But there are a number of other significant advantages which resonate all too clearly from my time at Atrenta.
One is a 10X reduction noise. Anyone who’s ever used a static verification tool knows that noise can be a huge pain. Simulation will only catch bugs exercised and detected by the tests you run. Static verification will catch all bugs within the range of checks it performs. But the devil’s bargain you make for this completeness is that it will also catch many things that aren’t problems or are just different manifestations of a problem it already reported. You may have to wade through a whole bunch of spurious errors to find the one or two real problems you need to fix.
Reducing this noise level is a very big deal. I remember the Atrenta team working on methods to compress errors by root cause as one approach to noise reduction. Other techniques used formal methods to weed out structurally apparent errors which are not functionally possible. It sounds like Synopsys has extended these methods further.
Another key advantage I cannot over-emphasize is completing compatibility with the Synopsys implementation tools. This starts with synthesis compatibility. Under the hood, SpyGlass does a quick synthesis so it can run a lot of checks on an elaborated graph. How effective (or noisy) that is depends very much on how well it mirrors the ultimate real implementation. At a superficial level that’s not such a big deal. You use one of the standard open-source synthesis platforms and you’re good, right?
Wrong. There are a number of places where using a different synthesis solution is likely to generate false errors or miss real errors: datapath and mux inferencing are just two examples. When a tool gets this stuff wrong, pretty soon it’s thrown out. We always wrestled with trying to match DC behavior as closely as we could, but you can never do as well as you can when using the real thing. No longer a problem in VC SpyGlass.
Another related problem was matching behavior in constraints. There’s a lot of useful information in those constraints to flag clocks, resets and so on. Especially useful in CDC and reset analysis and can also be useful in other aspects of static analysis. When is a clock really a clock? You can try to infer this bottom-up by just looking at the RTL, tracing back from register clocks. But that’s not foolproof. Constraints fix the ambiguity, but you need to interpret them the same way the implementation tools do. Not so bad in vanilla SDC but potentially much more difficult in Tcl. Again, no longer a problem in VC SpyGlass.
Finally, VC SpyGlass has unified debug with Verdi. Let’s face it, Verdi is the de facto standard for functional debug in the industry. Everybody uses it. We had an interface to Verdi when I was at Atrenta. But there are interfaces and then there are native integrations. Native integrations are invariably faster and more capable. You can switch back and forth between VC tools, retaining a consistent VC interface throughout.
I’m happy to see VC SpyGlass fully integrated the VC family. It confirms the value we created and a continuing bright future for the technology. You can learn more about VC SpyGlass HERE.
[post_title] => SpyGlass Gets its VC
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[post_content] => I got a chance to chat with Richard Solomon at Synopsys recently about a very real threat for all of us and what Synopsys is doing about it. No, the topic isn’t the Coronavirus, it’s one that has been around a lot longer and will continue to be a very real threat – data and interconnect security.
First, a bit about Richard. He is the technical marketing manager for DesignWare PCI Express (PCIe) Controller IP at Synopsys. He previously worked at NCR Microelectronics, Symbios Logic and over two decades at LSI Logic, including the position of architect for host interfaces there. Richard has seen a lot of complex design challenges in his career, and we spent some time discussing data/interconnect security in the context of his experience and the plans Synopsys is developing.
Richard began with a big picture view of the problems associated with a lack of security. Looking through a “cost” lens, here are some facts:
I had the opportunity to preview an upcoming SemiWiki webinar on IR drop and power integrity. These topics, all by themselves, have real stopping power. Almost everyone I speak with has a story to tell about these issues in a recent chip design project. When you combine hot topics like this with a presentation that details the collaboration between Synopsys and ANSYS to solve them, you have a real winner in my view. The details of how industry-leading extraction and analysis tools from ANSYS are tied to industry-leading implementation tools from Synopsys are clearly worth a look.
You can view this webinar on Tuesday, March 31, 2020 at 10AM Pacific time. Mark that on your calendar. The registration link is included, above. I’ll repeat it later. Let’s first review who’s presenting at this webinar and what they’ll cover.
The first speaker is Rahul Deokar, director of marketing and business development for the Synopsys Fusion Design Platform, with focus on signoff products, including RedHawk Analysis Fusion. Rahul begins his presentation with a review of the technology trends and associated challenges and dangers presented by things like dynamic voltage drop and power integrity. He then presents Redhawk-SC and discusses its capabilities to effectively deal with the problems under discussion.
Rahul then describes RedHawk Analysis Fusion, a two-year project to combine the analysis capabilities of ANSYS RedHawk with the implementation capabilities of Synopsys ICC II/Fusion Compiler. Signoff quality analysis with a native integration to an industry-leading implementation flow at the block, subsystem and full-chip levels. This really got my attention.
Getting into more details, Rahul explains the benefits of block-level signoff accuracy, robust place & route optimization and the ability to access the latest distributed processing capabilities of RedHawk-SC. Rahul then summarizes the added features in the new release of RedHawk Fusion. The list is quite extensive and impressive. He also covers the power integrity design flow that is enabled by RedHawk Fusion. To give you a feeling for the what’s included, I’ll just mention one of the many capabilities covered:
Dynamic Power Shaping: optimizes peak current and reduces dynamic voltage drop via clock scheduling.
All the capabilities presented are illustrated with real design examples, including case studies of a 7nm design. To whet your appetite further, machine learning is also employed in the release.
Marc Swinnen then presents the details of ANSYS RedHawk-SC, their next-generation product for 7nm and below. Marc is the director of product marketing at ANSYS. The next-generation architecture for RedHawk was developed about four years ago and it’s called SeaScape – RedHawk-SC is based on it. Marc explains that the motivation for this new platform was two-fold:
StarVision Pro[/caption]
The wow moment is when you read in a file format and then quickly visualize an automatic schematic, neatly laid out with inputs on the left and outputs on the right showing you all of the interconnect, cell instances and hierarchy. Circuit designers, logic designers and even DFT engineers can each benefit from quickly seeing how an SoC is assembled. For logic verification you can even see the logic state on each net in a design as a function of time.
During a live demo on a laptop running Linux I saw Sujit read in a digital design, and this works even if your design is incomplete, missing IP or has syntax errors. Just look at how neat the auto-generated schematic appears:
[caption id="attachment_284112" align="alignnone" width="850"]
Auto-generated schematic[/caption]
Useful debugging features include:
Parasitic Interconnect Cross-Probing[/caption]
An engineer can then find which nets are the heaviest loaded, and Sujit ran a pre-built script that allowed him to filter and remove all capacitors below a threshold value.
A SPICE netlist was loaded, and we viewed the MOS transistors, along with some parasitic capacitors:
[caption id="attachment_284119" align="alignnone" width="850"] SPICE netlist[/caption]
Next, we wanted to know what had changed in a SPICE netlist over time, so a DIFF script quickly highlight where the differences were located by showing that net n6 was modified:
[caption id="attachment_284120" align="alignnone" width="850"] Net n6 was modified[/caption]
StarVision Pro comes with some 100 scripts, so I got the idea that they had automated most debugging tasks for me, saving me time from having to write my own scripts. Of course, you can always just view the Tcl source code for the scripts, and create new derivatives and combinations to make your debugging happen faster.
Videos
On YouTube there's a channel for EDA Direct, and they've recorded over a dozen intro videos on specific StarVision Pro topics, and each video is brief at under 2 minutes of viewing time:
Having the right tool for the job at hand is always a joy, and when your IC project involves RTL code, gates, transistors and even parasitic interconnect, then you need some EDA tool help for debugging and finding out why your design behaves the way it is. An FAE named Sujit Roy did a conference call with me last week to show what StarVision… Read More
Blocking chip sales to Huawei back on front burner
Covid19 & China Trade are equally bad
Long lived Uncertainty could “plague” industry sales going forward
Political Predictability worse than Disease Predictability
Reuters broke a story today that the proposed licensing of chip equipment to prevent “bad… Read More
By now it is pretty clear that everywhere outside of China and South Korea human beings are doing a lousy job of “social distancing,” locking down, and sheltering in place. This is unfortunate because experts agree that only a complete lockdown will stop COVID-19 from infecting millions, continuing to kill thousands,
2019 will be remembered as the year the automotive industry decided to right-size its autonomous vehicle ambitions. Multiple auto makers tempered their vaunted claims for delivering fully autonomous cars within a few years and Daimler Chairman of the Board Ola Kälenius declared in December that the pursuit of autonomous “robotaxi
It started slowly at first. Then it began picking up steam. I’m referring to consolidation in the semiconductor sector. I had a front-row seat for what consolidation did to the ASIC part of semiconductor and that is the topic of this discussion. I was the VP of marketing at eSilicon, the company that invented the fabless ASIC model.… Read More
It is a demand driven downturn – harder to predict
It may not be “business as usual” after this virus
What systemic changes could the industry face?
Trying to figure out another cycle-driven by inorganic catalyst
Investors and industry participants in the semiconductor industry who are used to normal cyclical… Read More
It’s a matter of pride to me and many others from Atrenta days that the brand we built in SpyGlass has been so enduring. It seems that pretty much anyone who thinks of static RTL checking thinks SpyGlass. Even after Synopsys acquired Atrenta, they kept the name as-is, I’m sure because the brand recognition was so valuable.
Even good… Read More
I got a chance to chat with Richard Solomon at Synopsys recently about a very real threat for all of us and what Synopsys is doing about it. No, the topic isn’t the Coronavirus, it’s one that has been around a lot longer and will continue to be a very real threat – data and interconnect security.
First, a bit about Richard. He is the technical… Read More
EUV lithography is widely perceived to be the obvious choice to replace DUV lithography due to the shorter wavelength(s) used. However, there’s a devil in the details, or a catch if you will.
Electrons have the last word
The resist exposure is completed by the release of electrons following the absorption of the EUV photon.… Read More
I had the opportunity to preview an upcoming SemiWiki webinar on IR drop and power integrity. These topics, all by themselves, have real stopping power. Almost everyone I speak with has a story to tell about these issues in a recent chip design project. When you combine hot topics like this with a presentation that details the collaboration… Read More
Prevent and Eliminate IR drop and Power Integrity Issues using Redhawk Fusion
Conversation with Dr. Walden Rhines: Predicting Semiconductor Business Trends!
eNVM Technology Choices for Advanced Automotive, Industrial and Multi Market Solutions
Detecting Security Vulnerabilities in a RISC-V Based System-on-Chip
Artificial Intelligence in Micro-watts: How to make TinyML a reality
Design Methodologies for Next-Generation Heterogeneously Integrated 2.5/3D-IC Designs
Maximize your Hardware Assurance with eFPGA IP
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