TSMC Q4 2019 “2020 Bellwether” Conference Call SummaryAfter returning from a week in Southern China…Read More
Samsung spend is up but can it offest TSMC slowing?Samsung is warming up and spending again Samsung…Read More
| Date: | Feb. 5, 6, 7, 2020 |
| Location: | SEMI Headquarters, 673 South Milpitas Blvd., Milpitas, California, 94035, USA |
| Class Schedule: | Wednesday: 8:30 AM - 5:00 PM Thursday: 9:00 AM - 5:00 PM Friday: 9:00 AM - 5:00 PM |
| Tuition: | $1,895 |
1. Process integration. The 10/7nm technology nodes represent a landmark in semiconductor manufacturing and they employs transistors that are faster and smaller than anything previously fabricated. However, such performance comes at a significant increase in processing complexity and requires the solution of some very fundamental scaling and fabrication issues, as well as the introduction of radical, new approaches to semiconductor manufacturing. This section of the course highlights the key changes introduced at the 10/7nm nodes and describes the technical issues that had to be resolved in order to make these nodes a reality.
2. Detailed 10nm Fabrication Sequence. The FinFET represents a radical departure in transistor architecture. It also presents dramatic performance increases as well as novel fabrication issues. The 10nm FinFET is the 3rd generation of non-planar transistor and involves some radical changes in manufacturing methodology. The FinFET’s unusual structure makes its architecture difficult for even experienced processing engineers to understand. This section of the course drills down into the details of 10nm FinFet structure and its fabrication, highlighting the novel manufacturing issues this new type of transistor presents. A detailed step-by-step 10nm fabrication sequence is presented (Front-end and Backend) that employs colorful 3D graphics to clearly and effectively communicate the novel FinFET architecture at each step of the fabrication process. Attention to key manufacturing pitfalls and specialty material requirements are pointed out at each phase of the manufacturing process, as well as the chemistries used.
3. Nanowire Fabrication - the 5nm Node. Waiting in the wings is the Nanowire. The advent of this new and radically different 3D transistor features gate-all-around control of short channel effects and a high level of scalability. A detailed process flow of a Horizontal Nanowire fabrication process will be presented that is beautifully illustrated with colorful 3D graphics and which is technically accurate.
4. DRAM Memory. DRAM memory haS evolved through many generations and multiple incarnations. Despite claims that DRAM memory is nearing its scaling limit, new technological developments keep pushing the scaling envelope to extremes. This part of the course examines the evolution of DRAM memory and presents a detailed DRAM process fabrication flow.
5. 3D NAND Flash Memory. The advent of 3D NAND Flash memory is a game changer. 3D NAND Flash not only dramatically increases non-volatile memory capacity, it will also add at least three generations to the life of this memory technology. However, the structure and fabrication of this type of memory is radically different, even alien, to any traditional semiconductor fabrication methodology. This section of the course presents a step-by-step visual description of the unusual manufacturing methodology used to create 3D Flash memory, focusing on key problem areas and equipment opportunities. The fabrication methodology is presented as a series of short videos that clearly demonstrate the fabrication operations at each step of the process flow.
6. Advanced Lithography. Lithography is the “heartbeat” of semiconductor manufacturing and is also the single most expensive operation in any fabrication process. Without further advances in lithography continued scaling would difficult, if not impossible. Recently there have been significant breakthroughs in Extreme Ultra Violet (EUV) lithography that promise to radically alter and greatly simplify the way chips are manufactured. This section of the course begins with a concise and technically correct introduction to the subject and then provides in-depth insights into the latest developments in photolithography. Special attention is paid to EUV lithography, its capability, characteristics and the recent developments in this field.
7. Emerging Memory Technologies. There are at least three novel memory technologies waiting in the wings. Unlike traditional memory technologies that depend on electronic charge to store data, these memory technologies rely on resistance changes. Each type of memory has its own respective advantages and disadvantages and each one has the potential to play an important role in the evolution of electronic memory.
This section of the course will examine each type memory, discuss how it works, and what its relative advantages are in comparison with other new memory types.
8. Survey of leading edge devices. This part of the course presents a visual feast of TEMs and SEMs of real-world, leading edge devices for Logic, DRAM and Flash memory. The key architectural characteristics for a wide range of key devices will be presented and the engineering trade-offs and compromises that resulted in their specific architectures will be discussed. The Fellow Emeritus representative of the world’s leading chip reverse engineering firm will present the section of the course.
9. 3D Packaging Versus 3D Monolithic Fabrication. Unlike all other forms of advanced packaging that communicate by routing signals off the chip, 3D packaging permits multiple chips to be stacked on top of each other, and to communicate with each other using Thru-Silicon Vias (TSVs), as if they were all one unified microchip. An alternate is the 3D Monolithic approach, in which a second device layer is fabricated on a pre-existing device layer and electrically connected together employing standard nano-dimensional interconnects. Both approaches have advantages and disadvantages and promise to create a revolution in the functionality, performance and the design of electronic systems.
This part of the course identifies the underlying technological forces that have driven the development of Monolithic fabrication and 3D packaging, how they are designed and manufactured, and what the key technical hurdles are to the widespread adoption of these revolutionary technologies.
10. The Way forward: a CMOS technology forecast. Ultimately, all good things must come to an end, and the end of FinFET technology appears to be within sight. No discussion of advanced CMOS technology is complete without a peek into the future, and this final section of the course looks ahead to the 5/3.5/2.5 nm CMOS nodes and forecasts the evolution of CMOS device technology for Logic, DRAM and Flash memory.
Happy Chinese New Year. Let’s hope the Year of the Rat brings a recovery for the semiconductor industry. The initial signs are all good with many positive indications in the news this week, but let’s hope the Wuhan coronavirus doesn’t derail the recovery by becoming a global emergency. To all those based in China stay safe and healthy.
Here is my weekly summary of all the key semiconductor and technology news from around the world this week.
In IC Insights 2020 edition of The McClean Report they predict that 26 out of the 33 IC product categories will show positive growth in 2020 with 5 products expected to enjoy double digit growth. This is much more positive than 2019 where only 6 categories had positive growth, but still not as good as 2018. Product categories expecting double growth, are NAND, Automotive special purpose IC, DRAM, display drivers and embedded MPU.
This week several major companies reported quarterly earnings, with a very optimistic message being given by all.
Texas Instruments earnings report pointed to a recovery across the IC industry. They said “most markets showed signs of stabilising” and forecast Q1 revenue midpoint of US$3.25billion. Last quarter they posted better than expected earnings of US$3.35billion, but this was still down 10% on a year ago and down 11% sequentially. As Texas Instruments have a very broad portfolio across all markets it is a good indicator of the general market so it is quite optimistic that they see the market stabilising after 5 quarters of decline.
STMicro also posted solid results for Q4 reporting revenue of US$2.75billion, up 7.9% sequentially on strong sales for low emission cars and next generation smartphones, though traditional older generation automotive products were down. The poor sales of established automotive products will also impact next quarter where they forecast up to 14% drop in sales. STM did also announce they will invest $1.5billion in 2020 direct at capital expenditure.
Intel also gave a very upbeat message at their Q4 earnings call. Intel reported that strong cloud computing demand drove revenue in Q4 to US$20.2, up 8% on Q3. For the year they reported revenue of $71.965billion, up 1.3% on 2018. For the coming year they forecast revenue to be up a further 2% at $73.5billion, with revenue in Q1 at $19billion. In addition Intel plans to spend $17 billion on capex to increase capacity to Ensure they can support customer demand and build inventory..
TSMC also gave a bullish message at their investors conference. CC Wei, TSMC’s CEO said he expected revenue for 2020 to grow by more than 17% driven by demand for smartphones, high performance computer devices, the Internet of Things related applications and automotive electronics this year.
In December the Global Purchasing Managers Index was neutral with a PMI of 50 on average, however this varies by country significantly with China, Taiwan and South Korea all showing modest expansion.
Several 3rd party foundry vendors are entering or expanding their efforts in the silicon carbide (SiC) foundry business amid booming demand for the technology especially from automotive applications. However the entrance of these new comers may not be so easy as the traditional IDM companies like Cree and Rohm use proprietary processes to differentiate their products.
Finally, with many different variants of 7nm technology being made available here is a concise summary of the differences between the variants and the benefits.
[post_title] => The Tech Week that was January 20th
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[post_content] => The use of machine learning (ML) to solve complex problems that could not previously be addressed by traditional computing is expanding at an accelerating rate. Even with advances in neural network design, ML’s efficiency and accuracy are highly dependent on the training process. The methods used for training evolved from CPU based software, to GPUs and FPGAs – which offer big advantages because of their parallelism. However, there are significant advantages to using specially designed domain specific computing solutions.
Because training is so compute intensive, both total performance and performance per watt are both extremely important. It has been shown that domain specific hardware can offer several orders of magnitude improvement over GPUs and FPGAs when running training operations.
[caption id="attachment_281972" align="aligncenter" width="919"]
AI Domain Specific Processor[/caption]
On December 12th GLOBALFOUNDRIES (GF) and Enflame Technology announced a deep learning accelerator solution for training in data centers. The Enflame Cloudblazer T10 uses a Deep Thinking Unit (DTU) on GF’s 12LP FinFET platform with 2.5D packaging. The T10 has more than 14 billion transistors. It uses PCIe 4.0 and Enflame Smart Link for communication. The AI accelerator supports a wide range of data types, including FP32, FP16, BF16, Int8, Int16, Int32 and others.
The Enflame DTU core features 32 scalable intelligent processors (SIP). Groups of 8 SIPs each are used to create 4 scalable intelligent clusters (SIC) in the DTU. HBM2 is used to provide high speed memory for the processing elements. The DTU and HBM2 are integrated with 2.5D packaging.
This design highlights some of the interesting advantages of GF’s 12LP FinFET process. Because of high SRAM utilization in ML training, SRAM power consumption can play a major role in power efficiency. GF’s 12LP low voltage SRAM offers a big power reduction for this design. Another advantage of 12LP is much higher level of interconnect efficiency compared to 28nm or 7nm. While 7nm offers smaller feature size, there is no commensurate improvement in routing density for higher level metals. This means that for a highly connected design like the DTU, 12LP offers a uniquely efficient process node. Enflame is taking advantage of GF’s comprehensive selection of IP libraries for this project. The Enflame T10 has been sampled and is scheduled for production in early 2020 on GF’s Fab 8 in Malta New York.
A company like Enflame has to walk a very fine line in designing an accelerator like the T10. The specific requirements for machine learning determine many of the architectural decisions for the design. On-chip communication and reconfigurability are essential elements. The T10 excels in this area with its on-chip reconfiguration algorithm. Their choice in selecting 12LP means optimal performance without the risk and expense of going to a more advanced node. GF is able to offer HBM2 and 2.5D packaging in an integrated solution, further reducing risk and complexity for the project.
It is widely understood that increasing training data set size improves the operation and performance of ML applications. The only way to handle these increasing workloads is with fast and efficient accelerators that are designed specifically for the task. The CloudBlazer T10 looks like it should be an attractive solution. The full announcement and more information about both companies is available on the GLOBALFOUNDRIES website.
[post_title] => Specialized Accelerators Needed for Cloud Based ML Training
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FPGAs, today and throughout the history of semiconductors, play a critical role in design enablement and electronic systems. Which is why we included the history of FPGAs in our book “Fabless: The Transformation of the Semiconductor Industry” and added a new chapter in the 2019 edition on the history of Achronix.
In a recent blog post “FPGAs in the 2020s – The New Old Thing” Achronix reminds us that even though FPGAs are 35 years old the coming age of AI in the cloud represents a new FPGA growth opportunity to which I agree to 100%. In fact, during our first webinar series last year the Achronix ML webinar broke analytic records.
Whether on the edge (eFPGA) or in the cloud (FPGA), programmable technology will play a critical role with the explosive data growth of the 5G era which has just begun. We started tracking AI on SemiWiki in Q4 of 2015 and have published 182 blogs that have garnered close to one million views which is quite good. We also get to see who reads what, when, and where. Just to net it out, AI is everywhere and companies big and small are consuming AI design enablement information as fast as we can publish it, absolutely.
Back to the Achronix blog post “FPGAs in the 2020s – The New Old Thing”, it is full of interesting data and links that will be of great use if you are investigating FPGA use in the 5G era. I have also spent many hours researching AI and have finished several AI projects in collaboration with some big name companies and SemiWiki partners. Hit me up in the comments section if you want to talk more. AI is coming, there is no stopping it, and it is exciting so let’s talk.
FPGAs in the 2020s – The New Old Thing, January 8, 2020 FPGAs are the new old thing in semiconductors today. Even though FPGAs are 35 years old, the next decade represents a growth opportunity that hasn’t been seen since the early 1990s. Why is this happening now? There continues to be a data explosion in the world, with IDC predicting over 175 zetabytes of data will be generated annually by 2025. With this much data, there is a tremendous opportunity to analyze it for insights that can change and influence the world. AI will play a huge role in this data mining operation, and companies are growing their workforce with deep skills in machine learning and data analytics to meet the challenges of the future... And don't miss the upcoming Achronix webinar: New Block Floating Point Arithmetic Unit for processing AI/ML Workloads in FPGA Abstract: Block Floating Point (BFP) is a hybrid of floating-point and fixed-point arithmetic where a block of data is assigned a common exponent. We describe a new arithmetic unit that natively performs Block Floating Point for common matrix arithmetic operations and creates floating-point results. The BFP arithmetic unit supports several data formats with varying precision and range. BFP offers substantial power and area savings over traditional floating-point arithmetic units by trading off some precision. This new arithmetic unit has been implemented in the new family of 7nm FPGAs from Achronix. We cover the architecture and supported operations of the BFP unit. In this presentation, artificial intelligence and machine learning workloads are benchmarked to demonstrate the performance improvement and power savings of BFP as compared to half-precision (FP16) operations. About the presenter Dr. Mike Fitton is senior director, strategy and planning at Achronix. He has 25+ years of experience in the signal processing domain, including system architecture, algorithm development, and semiconductors across wireless operators, network infrastructure and most recently in machine learning. [post_title] => FPGAs in the 5G Era! [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => fpgas-in-the-5g-era [to_ping] => [pinged] => [post_modified] => 2020-01-26 21:06:29 [post_modified_gmt] => 2020-01-27 05:06:29 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=281945 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [4] => WP_Post Object ( [ID] => 281987 [post_author] => 19 [post_date] => 2020-01-26 10:00:23 [post_date_gmt] => 2020-01-26 18:00:23 [post_content] =>
Believe it or not, Tesla Motors is teaching us to be better drivers. One of the most remarkable lessons we are learning is that motor vehicles on public roadways ought to stay away from emergency and other service vehicles. In the U.S., we can all expect to hear more about “Move Over” laws – now enacted in all 50 states.
It sometimes seems as if Tesla vehicles have an uncanny ability, while operating in Autopilot mode, to collide with emergency vehicles parked on highways while on official business. The latest incident occurred on December 29th in Cloverdale, Ind., when a Tesla Model 3 collided with a fire truck on Interstate 70. The fire truck reportedly had its lights flashing while parked in the left lane. A passenger in the vehicle was killed. (Coincidentally on the same day in Gardena, Ca., a Tesla Model S also reportedly operating on Autopilot ran a stoplight and crashed into the side of a Honda Civic, killing its two occupants.)
Let’s be clear about one thing. Non-Tesla vehicles get into crashes every day in the U.S. (and around the world) resulting in 100 lives lost daily in the U.S. (3,500 globally). Highway fatalities have become sufficiently routine as to be accepted as the cost of owning and operating our own cars on public rights of way.
Tesla crashes and the associated injuries and fatalities, on the other hand, are news events because the company has introduced computer-based driving into the equation in such a manner as to appear reckless and inspire opposition and outrage. Tesla crashes are also news events because they remain relatively rare.
The unique inclination of Tesla’s operating on Autopilot to collide with emergency vehicles, though, has shown a spotlight on a big problem for which a solution may be in the offing. Last week, U.S. Department of Transportation Secretary Elaine Chao announced the commitment of $38M to equip emergency response vehicles and infrastructure with life-saving V2X technology in the 5.9GHz band. Chao noted that emergency response vehicles are involved in roughly 46,000 crashes, causing 17,000 injuries and 150 fatalities annually.
The First Responder Safety Technology Pilot Program described by Chao will provide funding to equip emergency response vehicles, transit vehicles, and related infrastructure including traffic signals and highway-rail grade crossings with V2X technology. Chao did not specify the nature of the V2X wireless technology but her comments were interpreted to be technology agnostic – though she did note the agency’s preference that 5.9GHz be preserved for transportation applications regardless of the technology.
Chao’s announced plans mirror legislation sponsored by U.S. Senators Dick Durbin (D-IL), and Tammy Duckworth (D-IL) and introduced in 2019 intended to establish a new national safety priority within an existing federal grant program to increase public awareness of “Move Over” laws and encourage implementation of life-saving digital alert technology.
The USDOT’s announcement of these initiatives also follows appropriations language secured by Durbin, establishing a $5M pilot program to test and deploy these digital alert technologies to protect law enforcement, first responders, roadside crews, and others while on the job. (Worth noting a demonstration at CES2020 by Veoneer and Verizon equipping roadside workers with 5G infused safety vests for communication with oncoming vehicles.)
Chicago-based HAAS Alert supports the Senate bill. The company has spent years implementing its vision of a “Safety Cloud” intended to aggregate digital alerts derived from tracking devices mounted on emergency response and service vehicles.
The effort by HAAS Alert to create its safety cloud has taken many forms, but progress has been steady. The goal is to deliver a driver alerting system that might integrate with embedded in-vehicle infotainment systems and or smartphones to warn drivers of emergency vehicles stopped in the road ahead or approaching from behind or even approaching perpendicularly at an upcoming intersection.
On January 6, Haas Alert announced a deal with Oshkosh-Pierce Manufacturing whereby HAAS Alert digital alerting technology will be included as a standard safety feature at no additional cost in Pierce's custom fire apparatus and as an available aftermarket solution for apparatus currently in service. HAAS Alert struck a similar deal with vehicle maker RevGroup in 2018.
Other HAAS Alert deals and initiatives include:
A signed trade deal between the US and China has finally been signed. How much does this settle down the relationship and what will continue to cause problems? Given that in the same week as the deal was signed, the US government confirmed their new tough restrictions on allowing Chinese investment at any level into technology and many other sectors deemed sensitive in the US, clearly not all is well.
For companies manufacturing in China, we have the benefit of certainty of what tariff levels we need to deal with. If exports are in the 7.5% tariff category that’s low enough that we might just keep manufacturing in China. For multinationals with sophisticated supply chains and factories all around the world, their executives simply put the tariff costs into their models and determine whether Mexico, Turkey, Vietnam or China is now the best place to produce products for China. The losers in all this are smaller companies that perhaps only had 1 factory in China and who sold most of their output in the US. Shifting production is enormously disruptive and they may not even have the skills to do so. With clarity on tariffs, expect an uptick in investment in factories in China as companies move ahead with investments that had been on hold.
China has agreed to purchase US$200bn over a 2017 base line from the US. How hard will that be and who wins and loses?
· Manufactured goods: Provided Boeing is able to get the 737Max recertified in China sometime in the next 2 years, simply clearing the backlog on these planes ordered by China will generate many billions of incremental sales. Certainly, China will be willing to buy more technology products such as semiconductors from the US – but there may be friction on this if the US restricts the ability of Chinese companies to buy these products. China can buy more oil from the US, if the US actually has the capacity in its ports to enable this. China has a surplus of refining capacity and could import US oil to fill these refineries who will simply turnaround their output and export it. Winners – Chinese refineries, losers – refineries elsewhere in Asia. Automotive exports from the US to China are modest and not likely to grow much. Chinese consumers aren’t very interested in US style pick-up trucks. GM makes China specific cars in China; Tesla manufactures in China. The largest exporter of auto from the US to China is probably Mercedes.
· Agricultural products. Probably the most important category for the Trump administration to see progress on in 2020. Soya beans and other cereals, beef and pork, premium fruit and vegetables. Winners US agricultural producers, losers South American producers and possibly Chinese consumers who may end up paying higher prices if US goods are not cost competitive in global markets.
· Services. Again, there could be much friction here. China could say: “We are encouraging more Chinese tourists to visit the US and students to study in the US, but you, the US, won’t give them visas”. Chinese companies will be very willing to license US technologies, brands and other IP, but will CFIUS allow them to do so?
So yes, there is a path to achieving the $200B – but it requires constructive engagement from the US, as much as from China.
China also agreed to accelerate opening up financial services and other sectors to US companies, with faster issuance of licenses to operate. China made clear today that this opening is to companies of any nationality, not just American. Many of the announced moves on IP protection and technology transfer were contained in the new Foreign Investment Law which went into effect a few weeks ago.
The trade deal does nothing to address the growing separation in many areas that both governments seem to be pushing for. In brief, restrictions on Chinese investments in US technology startups, in financial services, in any business that capture personally identifiable information will all be harder. Exports of technology products and IP from the US to China will be harder and China will continue to seek to become more self-sufficient. Market access in the US for Chinese technology companies will diminish further. China’s “secure and control” policy domestically will likewise reserve more of its technology market for Chinese companies. Chinese researchers will find it harder to obtain and retain positions at US universities or even in leading US tech companies. Chinese and US versions of product standards will emerge. The Chinese and US internets will continue to diverge and may eventually even lose interconnectivity. The threat to delist Chinese businesses currently trading on US stock exchanges remains real.
The trade deal does remove some uncertainties, allowing companies to move forward with their investment plans for manufacturing. It will lead to greater purchases by China from the US, but not without creating significant frictions. And it does nothing to shift the direction of travel towards separation on flows of capital, of talent, of IP and of technology based goods
[post_title] => US China Trade Deal - Will it Work?
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There is a live CEVA webinar coming up that you will NOT want to miss. We have been working with CEVA since 2012 and have posted 130 collaborative blogs. Those blogs have earned 927,901 views thus far and counting. The average blog on SemiWiki.com gets 5,885 views so they are ahead of the game.
First, why even use formal in such a flow? One reason is obvious. When you synthesize from one format to another, from C++ to RTL or from RTL to gates, no amount of simulation is going to prove conclusively that synthesis didn’t introduce some subtle error along the way. That’s why equivalence checking was invented, to prove that at minimum the input and output implementations are functionally equivalent at a cycle-level.
Another reason is to do some level of formal checking on the C++ itself. A couple of examples are out-of-range-accesses on arrays and uninitialized memory reads. You might catch these in C++ simulation, but you might not. Experienced programmers know that behind rarely taken branches can lurk dragons; formal is a good way to expose such problems. And the beauty of these methods is that they not only discover that a problem is possible, but they also show you how to create that problem, which should make it easier to figure out a fix.
Still, the bulk of Renesas’ usage is in equivalence checking and this starts with C++ to C++ checks. Renesas talks about image processing IP and communication IP, both natural applications for HLS. Both types of design are intrinsically complex and will evolve through multiple iterations. Equivalence checking between C++ revs can assure as completely as possible that unintended functional changes are not introduced.
This is sequential equivalence checking and will not always get to a proof of equivalence (or no-equivalence) without a little assistance. What will push a proof towards convergence in these cases is more hints (constraints) on behavior, such as bounding the range of an apparently unbound array index.
The best-known application of equivalence checking in HLS flows is in comparing the source C++ with the synthesized RTL. There’s an advantage here (I’m guessing) in having the HLS synthesizer and the SLEC equivalence checker come from the same product group. The checker knows what kinds of transformations the synthesizer can make, such as how it inserts pipeline stages, and can factor these in when looking for a complete proof.
I believe based on my reading of the Renesas white paper that they only edit the source C++, so all RTL changes are based on re-synthesis from source updates. They run equivalence checking on each RTL drop to establish either that they can get to a full proof or to find any bottlenecks to getting to proofs. This is with the goal of ensuring a full proof by the time they get to the final RTL drop.
Methods to help along full-proofs at this level are pretty familiar – help in identifying equivalence points between the two designs, along with some level of abstraction and hierarchical proving.
Renesas results are impressive in comparison with verification through extensive simulation. They show one example, for an image processor IP, in which they were able to reduce turnaround time from 260 days (simulation-based) to 4 days using equivalence checking. Of course you still want to do lots and lots of simulation (in C+) to prove functionality and performance. Catapult SLEC removes the need to worry about implementation bugs being introduced in mapping from C++ to RTL.
You can read the Renesas white paper HERE.
[post_title] => Formal and High-Level Synthesis
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[post_content] => Our friends at Threshold Systems have a new class that may be of interest to you. It's an updated version of the Advanced CMOS Technology class held last May. As part of the previous class we did a five part series on The Evolution of the Extension Implant which you can see on the Threshold Systems SemiWiki landing page HERE. And here is the updated course description:
| Date: | Feb. 5, 6, 7, 2020 |
| Location: | SEMI Headquarters, 673 South Milpitas Blvd., Milpitas, California, 94035, USA |
| Class Schedule: | Wednesday: 8:30 AM - 5:00 PM Thursday: 9:00 AM - 5:00 PM Friday: 9:00 AM - 5:00 PM |
| Tuition: | $1,895 |
1. Process integration. The 10/7nm technology nodes represent a landmark in semiconductor manufacturing and they employs transistors that are faster and smaller than anything previously fabricated. However, such performance comes at a significant increase in processing complexity and requires the solution of some very fundamental scaling and fabrication issues, as well as the introduction of radical, new approaches to semiconductor manufacturing. This section of the course highlights the key changes introduced at the 10/7nm nodes and describes the technical issues that had to be resolved in order to make these nodes a reality.
2. Detailed 10nm Fabrication Sequence. The FinFET represents a radical departure in transistor architecture. It also presents dramatic performance increases as well as novel fabrication issues. The 10nm FinFET is the 3rd generation of non-planar transistor and involves some radical changes in manufacturing methodology. The FinFET’s unusual structure makes its architecture difficult for even experienced processing engineers to understand. This section of the course drills down into the details of 10nm FinFet structure and its fabrication, highlighting the novel manufacturing issues this new type of transistor presents. A detailed step-by-step 10nm fabrication sequence is presented (Front-end and Backend) that employs colorful 3D graphics to clearly and effectively communicate the novel FinFET architecture at each step of the fabrication process. Attention to key manufacturing pitfalls and specialty material requirements are pointed out at each phase of the manufacturing process, as well as the chemistries used.
3. Nanowire Fabrication - the 5nm Node. Waiting in the wings is the Nanowire. The advent of this new and radically different 3D transistor features gate-all-around control of short channel effects and a high level of scalability. A detailed process flow of a Horizontal Nanowire fabrication process will be presented that is beautifully illustrated with colorful 3D graphics and which is technically accurate.
4. DRAM Memory. DRAM memory haS evolved through many generations and multiple incarnations. Despite claims that DRAM memory is nearing its scaling limit, new technological developments keep pushing the scaling envelope to extremes. This part of the course examines the evolution of DRAM memory and presents a detailed DRAM process fabrication flow.
5. 3D NAND Flash Memory. The advent of 3D NAND Flash memory is a game changer. 3D NAND Flash not only dramatically increases non-volatile memory capacity, it will also add at least three generations to the life of this memory technology. However, the structure and fabrication of this type of memory is radically different, even alien, to any traditional semiconductor fabrication methodology. This section of the course presents a step-by-step visual description of the unusual manufacturing methodology used to create 3D Flash memory, focusing on key problem areas and equipment opportunities. The fabrication methodology is presented as a series of short videos that clearly demonstrate the fabrication operations at each step of the process flow.
6. Advanced Lithography. Lithography is the “heartbeat” of semiconductor manufacturing and is also the single most expensive operation in any fabrication process. Without further advances in lithography continued scaling would difficult, if not impossible. Recently there have been significant breakthroughs in Extreme Ultra Violet (EUV) lithography that promise to radically alter and greatly simplify the way chips are manufactured. This section of the course begins with a concise and technically correct introduction to the subject and then provides in-depth insights into the latest developments in photolithography. Special attention is paid to EUV lithography, its capability, characteristics and the recent developments in this field.
7. Emerging Memory Technologies. There are at least three novel memory technologies waiting in the wings. Unlike traditional memory technologies that depend on electronic charge to store data, these memory technologies rely on resistance changes. Each type of memory has its own respective advantages and disadvantages and each one has the potential to play an important role in the evolution of electronic memory.
This section of the course will examine each type memory, discuss how it works, and what its relative advantages are in comparison with other new memory types.
8. Survey of leading edge devices. This part of the course presents a visual feast of TEMs and SEMs of real-world, leading edge devices for Logic, DRAM and Flash memory. The key architectural characteristics for a wide range of key devices will be presented and the engineering trade-offs and compromises that resulted in their specific architectures will be discussed. The Fellow Emeritus representative of the world’s leading chip reverse engineering firm will present the section of the course.
9. 3D Packaging Versus 3D Monolithic Fabrication. Unlike all other forms of advanced packaging that communicate by routing signals off the chip, 3D packaging permits multiple chips to be stacked on top of each other, and to communicate with each other using Thru-Silicon Vias (TSVs), as if they were all one unified microchip. An alternate is the 3D Monolithic approach, in which a second device layer is fabricated on a pre-existing device layer and electrically connected together employing standard nano-dimensional interconnects. Both approaches have advantages and disadvantages and promise to create a revolution in the functionality, performance and the design of electronic systems.
This part of the course identifies the underlying technological forces that have driven the development of Monolithic fabrication and 3D packaging, how they are designed and manufactured, and what the key technical hurdles are to the widespread adoption of these revolutionary technologies.
10. The Way forward: a CMOS technology forecast. Ultimately, all good things must come to an end, and the end of FinFET technology appears to be within sight. No discussion of advanced CMOS technology is complete without a peek into the future, and this final section of the course looks ahead to the 5/3.5/2.5 nm CMOS nodes and forecasts the evolution of CMOS device technology for Logic, DRAM and Flash memory.
Our friends at Threshold Systems have a new class that may be of interest to you. It’s an updated version of the Advanced CMOS Technology class held last May. As part of the previous class we did a five part series on The Evolution of the Extension Implant which you can see on the Threshold Systems SemiWiki landing page HERE. And… Read More
Happy Chinese New Year. Let’s hope the Year of the Rat brings a recovery for the semiconductor industry. The initial signs are all good with many positive indications in the news this week, but let’s hope the Wuhan coronavirus doesn’t derail the recovery by becoming a global emergency. To all those based in China stay safe … Read More
The use of machine learning (ML) to solve complex problems that could not previously be addressed by traditional computing is expanding at an accelerating rate. Even with advances in neural network design, ML’s efficiency and accuracy are highly dependent on the training process. The methods used for training evolved from CPU… Read More
FPGAs, today and throughout the history of semiconductors, play a critical role in design enablement and electronic systems. Which is why we included the history of FPGAs in our book “Fabless: The Transformation of the Semiconductor Industry” and added a new chapter in the 2019 edition on the history of Achronix.
In a recent blog… Read More
Believe it or not, Tesla Motors is teaching us to be better drivers. One of the most remarkable lessons we are learning is that motor vehicles on public roadways ought to stay away from emergency and other service vehicles. In the U.S., we can all expect to hear more about “Move Over” laws – now enacted in all 50 states.
It sometimes … Read More
Car companies are interesting creatures in a corporate world increasingly dominated by Internet-centric behemoths from Silicon Valley, Seattle, and China. While the denizens of the Internet have demonstrated their ability to create billions of dollars in shareholder value from the whims and whimsy of browsing consumers,
ASML reported sales of 4B Euros and a nice gross margin of 48% resulting in 2.70 Euros per share in earnings. Orders came in at 2.4B
A signed trade deal between the US and China has finally been signed. How much does this settle down the relationship and what will continue to cause problems? Given that in the same week as the deal was signed, the US government confirmed their new tough restrictions on allowing Chinese investment at any level into technology … Read More
There is a live CEVA webinar coming up that you will NOT want to miss. We have been working with CEVA since 2012 and have posted 130 collaborative blogs. Those blogs have earned 927,901 views thus far and counting. The average blog on SemiWiki.com gets 5,885 views so they are ahead of the game.
One of the reasons CEVA is so popular on SemiWiki
Formal verification has made significant inroads in RTL and gate-level verification because it provides complementary strengths to conventional dynamic verification methods; using both provides higher levels of coverage and confidence in the correctness of an implementation. I haven’t heard as much about formal use in … Read More
Don’t Blame Trump for Auto Downturn