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                    [post_date] => 2020-10-29 10:00:18
                    [post_date_gmt] => 2020-10-29 17:00:18
                    [post_content] => I've used OLED (Organic Light-Emitting Diode) displays for many years in my monitors, laptops, tablets, e-readers and smart phones; and knew that the AMOLED (Active-Matrix OLED) displays used thin-film transistor technology where each pixel can be controlled, but I hadn't considered the actual design process until Chen Zhao from Empyrean brought up the topic. What follows is part one of a Q&A discussion, where I learned about the design challenges of Flat Panel Design (FPD) and how automation is being applied.

Q: Can you give me a brief history of FPD technology?

After years of persistent efforts, traditional flat panel display (FPD) technology such as liquid crystal display (LCD) has made considerable progress1. Advanced technologies such as organic light-emitting diodes (OLED)2 and flexible panels3 have also make breakthroughs, and the industry share has also greatly increased.

Q: What is the FPD design flow like?

Like integrated circuit design, electronic design automation (EDA) is also the cornerstone of FPD circuit design. The FPD design flow includes panel circuit schematic design, layout design, circuit simulation, circuit layout parasitic parameter extraction, circuit design verification, etc. It is similar to analog integrated circuit design flow, but also has its unique design flow and design methodology.

[caption id="attachment_292460" align="alignnone" width="850"]FPD design flow min FPD Design Flow[/caption]

Q: How was FPD design approached in the early days?

The design flow of early domestic display panels was realized by point tools from multiple EDA tools. Because users need to switch frequently between these manufacturers’ EDA tools, the design flow is cumbersome, data compatibility and confidentiality are not good enough, and problems are not easy to track down. It will cause mutual wrangling, inefficiency, delays in construction, and will deteriorate product quality. In addition, these tools are basically tools from integrated circuit design, and they are obviously lacking in solving the unique professional needs of display panels and customized development.

Q: Instead of using point tools, what is a more efficient and elegant approach?

In order to solve various FPD problems of users, it is urgent to develop an EDA full-flow solution for FPD design. All tools are seamlessly integrated on a unified EDA platform to make the FPD design flow efficient and smooth, ensure design quality, and improve design effectiveness. At the same time, in order to meet the ever-changing design requirements of high-end and new FPD and the customization requirements of domestic customers, it is necessary to continuously develop new functions and new products to improve the leadership of FPD EDA tools.

Q: What specific tools has Empyrean put together for the design of FPD?

EMPYREAN has launched the world's only FPD full-flow design system. Shown below are the main tools of the system, including TCAD, SPICE modeling, circuit schematic design, layout design, circuit simulation, circuit simulation waveform analysis, parasitic RC extraction, layout physics and electrical verification, full design layout analysis, and mask analysis, etc., to achieve full flow coverage, smooth data transfer, and to greatly improve design efficiency.

[caption id="attachment_292462" align="alignnone" width="1100"]Empyrean FPD full design flow min Empyrean FPD Full Design Flow[/caption]

Q: Does this Empyrean design flow work only for LCD designs?

In addition to achieving the world’s only FPD design full-flow solution, on the basis of meeting LCD conventional design, EMPYREAN keeps up with the forefront of FPD design requirements, especially for the current popular and advanced fields such as curvilinear-shaped design, OLED high-end display, and touch panel4. EMPYREAN has pioneered a series of supporting design technologies, which enable FPD design to a new level and allow display companies to enter the high-end display field.

Q: How are the TFT devices simulated, and what models are being used?

EsimFPD Model is a SPICE model parameter extraction and optimization software specially designed for FPD by EMPYREAN. The traditional thin film transistor (TFT) RPI model has many problems in terms of model accuracy of amorphous silicon (A-Si)5 and low temperature polysilicon (LTPS)6. After years of continuous development and improvement, the R&D team of EMPYREAN has greatly improved the accuracy of the model in terms of temperature effect, sub-threshold area, leakage current and other important device characteristics7.

Taking into account the impact of process fluctuations on device characteristics, we have improved the traditional modeling methodology. Based on a large number of sampled data, we have performed statistical analysis on the device characteristics, and extracted process corner model and statistical model, which will help to reserve the smallest possible reasonable margin for subsequent FPD circuit design, and improve product performance and yield.

Q: What are the challenges of defining an accurate model?

In order to further improve the accuracy of model, based on the geometric dependence of device physics, we considered the geometry dependency of device characteristics with gate length and width of TFT devices, and developed the so-called bin model which can cover big geometry area8.

Our work has been extended to support new devices such as OLED, oxide semiconductor TFT (IGZO)9, and Micro-LED10.

In addition, we support reliability modeling of TFT devices5,6,9, including DC/AC stress model, hysteresis model, and image-sticking model, etc. The device reliability model can be used in circuit simulation tools to analyze the long-term reliability of FPD circuits. The next figure shows the fit of our stress model.

[caption id="attachment_292470" align="alignnone" width="650"]Fitting of stress model min Fitting of stress model[/caption]

Summary

FPD technology enables many consumer and industrial products that allow us to visualize information every day on our smart phones and monitors, and the design challenges for displays increases with each new product generation. Empyrean has nine tools that work in concert to form a full design flow for FPD products, and in part two I'll cover topics like:
  • Design technology of curvilinear-shaped FPDs
  • FPD layout design
  • FPD layout verification
  • Hierarchical FPD circuit simulation
  • RC extraction and analysis
  • Thermoelectric analysis
  • Mask analysis
  • Job file automation

References

  1. Xiang Feng, Xiao Sun, Qiang Zhang, Dan Wang, “Development Trend of LCD Technology”, Invited Paper, SID Symposium Digest of Technical Papers, 2018
  2. Ho-Kyoon Chung, Hye-Dong Kim, Boris Kristal, “AMOLED Technology for Mobile Displays”, Invited Paper, SID Symposium Digest of Technical Papers, 2012
  3. Chang‐Xiang Wu,Yen‐Lin Pan,Hung‐Ming Tsai,“Modeling and Analysis of the Flexible Touch Panel on the Flexible Active-matrix OLED Display”,SID Symposium Digest of Technical Papers, 2014
  4. Wei-Feng Zhou,Li-Qiang Chen,David Wang,“ New Full Screen Flexible AMOLED Solution with Fingerprint”, Invited Paper, SID Symposium Digest of Technical Papers, 2018
  5. Ching-Chieh Shih, Yeong-Shyang Lee, Kuo-Lung Fang, Ching-Hung Chen, and Feng-Yuan Gan, “A Current Estimation Method for Bias-Temperature Stress of a-Si TFT Device”, IEEE Trans. Dev. And Mat. Reliability, Vol. 7, No. 2, pp. 347, 2007
  6. Kim et al, “Investigation of the Instability of Low-Temperature Poly-Silicon Thin Film Transistor under a Negative Bias Temperature Stress”, Electron. Mater. Lett., Vol. 9, 2013
  7. Lifeng Wu, “An introduction of OLED/TFT device model and FPD design flow”, Invited Paper, MOS-AK Compact Modeling Workshop, Beijing, China, June 2018
  8. AnThung Cho, Lifeng Wu, Qionghua Mo, James Hsu, Kaijun Liu, Justin, Yunqin Hu, Wade Chen, York Lu, Xiaobin Fan, and Scott Lin, “Corner and Binning Model Simulation of TFT for GOA Driver Circuit in G8.6 Large-size TFT-LCDs”, International Display Workshops, Nagayo, Japan, December 2018
  9. Ken Hoshino, David Hong, Hai Q. Chiang, and John F. Wager, “Constant-Voltage-Bias Stress Testing of a-IGZO Thin-Film Transistors”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 7, 1365, JULY 2009
  10. Brian R.Tull, Nancy Twu, Yu-Jen Hsu, “Micro-LED Micro displays by Integration of III-V LEDs with Silicon Thin Film Transistors”, Invited Paper, SID Symposium Digest of Technical Papers, (246-248), 2017
[post_title] => Automating the Design of Flat Panel Displays [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => automating-the-design-of-flat-panel-displays [to_ping] => [pinged] => [post_modified] => 2020-10-28 09:20:21 [post_modified_gmt] => 2020-10-28 16:20:21 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=292459 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [1] => WP_Post Object ( [ID] => 292154 [post_author] => 16 [post_date] => 2020-10-29 06:00:19 [post_date_gmt] => 2020-10-29 13:00:19 [post_content] => I must admit I’m impressed with how CEVA is pulling together foundational solutions for advanced consumer electronics. This through their own technologies (DSP, audio, vision, neural nets) and a rapid pace of partnerships, investments and acquisitions. Off the top of my head, I remember recent announcements on Immervision for image correction for wide angle lenses, partnerships for 3D/spatial audio, and Hillcrest Labs for motion sensing and fusion. I’ll talk here about the last one, as applied to hearing, sensor fusion in hearables. Sensor Fusion in Hearables

Why sensor fusion in hearables?

Isn’t that an OEM problem, not an audio IP problem? Not according to Seth Sternberg, product manager at CEVA. Fusion is playing an increasingly important role in hearables. Start with the stuff we already know. Tap on an earbud to take a call or start a call – That tap is detected by an accelerometer. Take an earbud out of your ear and music stops playing. Put it back in and music starts again. Both based on proximity detection. So far, no fusion needed. But these sensing techniques are imperfect. For example, if I take the earbud out of my ear and hold it in my hand or lay it face down on a table, the sensor thinks its back in my ear. Fuse the proximity detection with other sensors, eg an accelerometer to detect motion, and you cover some of those cases better.

3D audio

3D audio is another use case. This is where an audio source is positioned in space, and as you move your head the apparent source position remains constant. Virtual audio like virtual video. To track this takes 9-axis motion and movement detection – gyroscope, accelerometer and magnetometer. These fuse together and then guide either object-based audio or ambisonics to create the illusion of a fixed audio source. Apple just put this in the AirPods Pro and both the PS5 and Xbox support this feature for gaming. Another application is fitness tracking. There’s a definite case for putting this in earbuds since our heads may move more reliably than our wrists during exercise.

Context awareness

Context-aware fusion is another application. If I’m in a noisy area, or if I’m running, why not have the earbuds crank up the volume in my earbuds a little.?Or perhaps I’m making a call, again in a noisy area. A sensor can detect when I am speaking because my jaw is moving. A front-facing microphone can amplify pickup when I am speaking and cancel pickup otherwise. Cutting down most of the background babble.

The devil's in the detail with sensors

This is just a sample of possible applications for fusion in audio.  Now dig a little deeper. All of the sensing depends on processing inputs from MEMS devices, then combining that input. These are imperfect: they're noisy, they drift, and they must be recalibrated regularly against other sensors and other inputs. Handling this task requires special expertise and detailed understanding of sensors from multiple manufacturers: STMicroelectronics, Bosch-Sensortec, TDK InvenSense, and others. Recalibration adds another wrinkle. If there had been a noticeable drift, the wearer doesn’t want to experience a sudden correction. The correction must be handled smoothly or transparently. Conversely, when detecting motion in a robot (say computer vision for a vacuum cleaner), you want immediate correction. The robot doesn’t get motion sickness and it should avoid crashing into the dog. Which underlines that how a application manages corrections must be sensitive to the application.

An easier life for OEM's, a better experience for users

The same is true for fusion according to Seth. Some expectations are pretty uniform across applications, others need to allow for application tuning. All of which can make sensor fusion a nightmare for OEMs. One of CEVA’s big aims in this release of MotionEngine Hear is to shoulder most of this burden. This software package handles all of the direct interface with the sensors, noise management, recalibration and fusion, so that OEMs can focus on what will differentiate their product. And for the end-user, the software brings context-awareness, and closes some of the gaps for true wireless stereo earbuds, such as more accurate in-ear detection. MotionEngine Hear is platform-agnostic, though naturally they’d love to have you run it on CEVA platforms. You can learn more HERE. [post_title] => Sensor Fusion in Hearables. A powerful complement [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => sensor-fusion-in-hearables-a-powerful-complement [to_ping] => [pinged] => [post_modified] => 2020-10-29 07:33:54 [post_modified_gmt] => 2020-10-29 14:33:54 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=292154 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [2] => WP_Post Object ( [ID] => 291960 [post_author] => 11830 [post_date] => 2020-10-28 10:00:25 [post_date_gmt] => 2020-10-28 17:00:25 [post_content] =>

How ML Enables Cadence Digital Tools to Deliver Better PPA

There has been a lot written about artificial intelligence/machine learning (AI/ML) and its application in the Cadence digital design flow. Most recently, I covered significant verification efficiency improvements in Xcellium ML.  A recent digital-themed white paper from Cadence takes a broader look at the impact of ML on power, performance and area (PPA). I had a chance to speak with Rod Metcalfe, product management group director in the Digital & Signoff Group at Cadence. Rod has a broad background in EDA, having worked at Synopsys, Magma, Avant!, Viewlogic and GEC Avionics before joining Cadence almost six years ago. He is the author of the white paper and quite knowledgeable on the subject of how ML enables Cadence digital tools to deliver better PPA.

The white paper begins with a discussion of ML as part of the Cadence Innovus Implementation System. ML, along with multi-threading and support for massively parallel computing are mentioned. The piece states that this makes developing a device with more than 10 million instances easier. I quizzed Rod on where a 10 million instance design fit in the spectrum of cutting-edge. His view was a design of this size was becoming mainstream. We’re in the big leagues now.

Any discussion of ML at Cadence will advance the concept of “ML inside” and “ML outside”, referring to how machine intelligence is implemented in the flow. Rod’s white paper had an excellent definition of these concepts. It is worth repeating here:

[ML] Inside means using ML to reduce the time required to achieve timing closure inside the tools, while [ML] outside refers to using expert systems to help close the loop across a complete iterative design flow. The former is effective because it allows ML to carry out “what-if” evaluations much faster, while the latter will help engineers with the necessary knowledge to make design and flow decisions more quickly.

There is an important process implied in this notion.  Designers are faced with many, many choices in the early phase of a complex design project. If ML can point the designer in the right direction by making (very) informed decisions regarding the best path to take, this has a fundamental impact on the efficiency and quality of the design process. Another quote from the white paper drives this point home:

What is important at this early stage is the speed with which the results can be generated, along with enough accuracy to inspire confidence. As there is limited design data available at this early stage in the design flow, this can be difficult. However, the amount of data available at the end of the place-and-route stage is considerable, which allows timing prediction to be much more accurate. The opportunity here is to use this late-stage data to deliver better early-stage results.

With regard to using late-stage data to make a more informed decision for the (next) early stage process, this is how ML in EDA makes an impact—how “old” data becomes a vibrant source of new perspectives.

I discussed the division of labor for these tasks with Rod. It turns out the customer is a key part of the process. Cadence develops advanced algorithms that “learn” from prior results, but the customer is the one who “trains” the tool with data from their unique design process. Before the days of ML, the EDA vendor would send an experienced AE to the customer site, and that person would perform the tuning function for the customer. Now, the customer can do it themselves with their own data, thanks to these new algorithms. This is real progress and a new way of working.

There are many more valuable and thought-provoking insights in this white paper. I’ll conclude with two of them. First, real PPA improvements for a high-performance CPU design are shared across 5nm – 12nm examples. Timing and power improvements are eye-popping. You need to read the white paper.

Second, there is a discussion of how to use ML and expert systems to automatically optimize a complete design implementation flow across many different tools. I quizzed Rod about this. Was this a futuristic comment, or did it describe something that is working today? He explained this is very real and working today. Want to learn more?  Read the white paper. You can find out how ML enables Cadence digital tools to deliver better PPA here.

[post_title] => How ML Enables Cadence Digital Tools to Deliver Better PPA [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => how-ml-enables-cadence-digital-tools-to-deliver-better-ppa [to_ping] => [pinged] => [post_modified] => 2020-10-26 19:40:46 [post_modified_gmt] => 2020-10-27 02:40:46 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291960 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 2 [filter] => raw ) [3] => WP_Post Object ( [ID] => 292289 [post_author] => 28 [post_date] => 2020-10-28 06:00:25 [post_date_gmt] => 2020-10-28 13:00:25 [post_content] => 2020 Wilson Report Verification ASIC FPGA Harry Foster and I started in semiconductors at the same time so it was great to reminisce while talking about the latest Wilson Research Group Functional Verification Trend reports. Before I get into the reports lets talk about Harry who is a verification superstar: Harry is Chief Scientist Verification for the Design Verification Technology Division of Mentor, A Siemens Business; and is the Co-Founder and Executive Editor for the Verification Academy. In addition, Harry is serving as the 2021 Design Automation Conference General Chair. He holds multiple patents in verification and has co-authored six books on verification. Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions to developing industry standards and was the original creator of the Accellera Open Verification Library (OVL) standard. There are two reports, one for ASIC and one for FPGA design. I’m more of an ASIC design person so I was not surprised with the ASIC report.  I'm not an FPGA design person so I was quite surprised with some of the FPGA findings on Non-trivial bug escapes. A little frightening actually. Both reports are available on the Mentor website. You can get the ASIC report HERE and the FPGA report HERE. Harry also did a webinar 2020 Wilson Research Group Verification Survey Results which you can find HERE.
Overview:
The 2019 global semiconductor market was valued at $385.4 billion after experiencing a 15% decline due to a 32% drop in the memory IC market, which is expected to recover in 2021. The IC/ASIC portion of the semiconductor market is valued at about $186.6 billion. The IC/ASIC semiconductor market is expected to reach a value of $233.4 billion by 2024, growing at a compounded annual growth rate (CAGR) of 4.6% during this forecast period. In contrast, the FPGA portion of the semiconductor market is valued at about $5 billion and is expected to reach a value of $7.5 billion by 2030, growing at a compounded annual growth rate (CAGR) of 4.4% during this forecast period. While COVID-19 has had a negative impact in 2020 on a number of market segments (e.g., consumer and automotive), other market segments (e.g., data center computing, networking, storage, and communication) are experiencing positive growth required to support today’s growing work-from-home (WFH) environment. Ensuring functional correctness is still one of the biggest challenges for both the ASIC/IC and FPGA markets. To quantify this, every two years, Mentor, A Siemens Business commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world. In this presentation, Harry Foster highlights the key findings from the 2020 Wilson Research Group Functional Verification Study and provides his interpretation and analysis behind today's emerging trends. The findings from this study provide invaluable insight into the state of today’s IC/ASIC and FPGA markets in terms of both design and verification trends.
What You Will Learn:
  • Latest industry ASIC and FPGA trends in design
  • Latest industry ASIC and FPGA trends in verification
  • An analytical interpretation of the study results
Bottom line:  It's a good report with a huge amount of history behind it and is definitely worth the reading time. Just a quick disclaimer, while looking at trends is important, trends are just one piece of the puzzle. If you want to drill down further SemiWiki is the best place. We are staffed by semiconductor design professionals and if we don't have the answers you are looking for we certainly know someone (like Harry Foster) who does, absolutely. [post_title] => ASIC and FPGA Design and Verification Trends 2020 [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => asic-and-fpga-design-and-verification-trends-2020 [to_ping] => [pinged] => [post_modified] => 2020-10-29 14:10:57 [post_modified_gmt] => 2020-10-29 21:10:57 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=292289 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [4] => WP_Post Object ( [ID] => 292445 [post_author] => 12 [post_date] => 2020-10-27 10:00:17 [post_date_gmt] => 2020-10-27 17:00:17 [post_content] => Data on China production of mobile phones from the National Bureau of Statistics of China indicates a double-digit decline in the year 2020. In 1Q 2020, the early stages of the COVID-19 pandemic, China mobile phone production declined 50% from 4Q 2019 and dropped 33% from a year earlier. Many factories were temporarily closed in an effort to control the spread of COVID-19. Production has since recovered with 2Q 2020 units up 36% from 1Q and 3Q 2020 units up 15% from 2Q. However even if production in 4Q 2020 returns to the 4Q 2019 peak of 517 million units, total 2020 production would be 1525 million units, down 15% from 2019. China Mobile Phone Update 2020 Mobile phones include both smartphones and feature phones. Smartphones account for about 75% of total mobile phone units. Although not all mobile phones are produced in China, China production tracks closely with estimates of the total mobile phone market, as shown in the table below. Mobil Phones 2020 The smartphone market decline in 2020 will not be as severe as the overall mobile phone decline. Recent forecasts call for a smartphone unit decline of about 10% to 11%. Smart phones 2020 The smartphone market decline is due to a combination of temporary cuts in production and temporary shutdowns of retail outlets because of the pandemic. Apple introduced its iPhone 12 lineup earlier this month, its first 5G phones. The iPhone 12 models are expected to boost smartphone demand in 4Q 2020. However, the iPhone 12 and 12 Pro did not begin shipping to customers until last Friday, October 23. The iPhone 12 mini and the iPhone 12 Pro Max will not ship to customers until November 13, almost halfway through the quarter. Analysts estimate Apple will ship about 80 million units of all iPhone 12 models in 4Q 2020. The iPhone 12 models should account for about 15% of total mobile phone production in the quarter and about 20% of smartphone production – not enough to significantly boost overall units in the quarter. The outlook for Chinese production of microcomputer units is much stronger than the outlook for mobile phones. In 1Q 2020 China production of microcomputers dropped 42% from 4Q 2019 and was down 15% from a year earlier. However, production bounced back strongly in 2Q 2020, up 72% from 1Q 2020 and up 17% from a year earlier. Based on data through 3Q 2020 and our Semiconductor Intelligence forecast for 4Q 2020, microcomputer production will be up 8% in 2020 over 2019. China Computer Production The definition of microcomputers in the China production data is uncertain, but it likely is a combination of PCs and tablets. China microcomputer production in 2019 was 338 million units. IDC estimated 2019 shipments of PCs were 266 million units and tablets were 143 million units, for a total of 410 million units. The China microcomputer production is 83% of the combined PC and tablet shipments. Our Semiconductor Intelligence forecast of 8% growth in China microcomputer production in 2020 fits with IDC’s September forecast of 3.3% growth for combined PC and tablet shipments in 2020. We expect a strong recovery in China mobile phone production in 2021. Following a 15% decline in 2020, production should grow about 20% in 2021. 2021 production of 1830 million mobile phone units would be a 2% increase from 1798 million units in 2019. China microcomputer production in 2021 should grow about 8%, the same rate as in 2020. China Production 2020 The China production data is consistent with overall trends in electronics in 2020. Demand for PCs and tablets has increased in 2020 as the pandemic has forced many people to work from home, learn from home, and even communicate socially from home. Many households without PCs or tablets have needed to acquire them, often subsidized by employers or schools. Other households have upgraded their PCs or tablets. The demand for mobile phones has been steady but was disrupted by temporary shutdowns of production facilities and retail outlets. Smartphone growth is recovering driven by 5G phones, including the iPhone 12 models. Semiconductor Intelligence is a consulting firm providing market analysis, market insights and company analysis for anyone involved in the semiconductor industry - manufacturers, designers, foundries, suppliers, users or investors. Please contact me if you would like further information. Bill Jewell Semiconductor Intelligence, LLC billjewell@sc-iq.com [post_title] => China Mobile and Computer Update 2020 [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => china-mobile-and-computer-update [to_ping] => [pinged] => [post_modified] => 2020-10-27 14:14:30 [post_modified_gmt] => 2020-10-27 21:14:30 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=292445 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [5] => WP_Post Object ( [ID] => 292411 [post_author] => 16 [post_date] => 2020-10-27 06:00:01 [post_date_gmt] => 2020-10-27 13:00:01 [post_content] => Arm and Mentor Recently announced that the Arm Design Reviews program now offers Mentor help in verification design reviews. I talked to Paul Williams (Sr Consultant and Verification Practice Lead at Mentor Graphics) and Peter Lewin (Dir. Mktg at Arm Partner Enablement Group) to get more insight into Arm Design Services, particularly the verification angle. First, to be clear, the review is intended to address customer implementations of Arm subsystems in their SoCs together with connectivity from the subsystem into other parts of the SoC. Apart from that, you’ll still have to handle your own design reviews for the rest of your chip. Arm Design Reviews

Review structure

Arm were already offering design reviews covering architecture, security, RTL design, physical implementation, trusted firmware, power management firmware and Linux power and thermal frameworks. This week they announced with Mentor this RTL verification component with particular emphasis on reviews of plans to validate signal connectivity, coherency, correct implementation and system performance (all with respect to the Arm subsystem). Paul kicked off by noting that Mentor have been doing quite a lot of verification services and review work over the years working with Arm as a customer. Now they’re taking this outside to Arm customers. The Mentor approach to review has three components. The first stage is a high-level view of the verification architecture – the big picture plan and structure. The second stage is a more detailed verification plan review – drilling down into the plan, what will need to be created or modified, schedule and resources allocated to various components of the plan. The final stage review comes towards the end of the project when they review coverage, which components of the plan are still incomplete and how those gaps might be addressed.

Assessment and recommendations

Paul pointed out the wide range of design application types they encounter. They see everything from massive multi-processor coherent system with huge complexity to a little MPU to detect if you shut the car door correctly. The design review service allows them to fit advice and recommendations to each need. They start with the same process that Arm already use for their design reviews. This is a written questionnaire, to help them set the scope. This guides who they will bring to the interview sessions. For example, if questions about formal or functional safety come up, they know who they’ll want to bring in. On methodologies, Paul was quick to point out that they don’t recommend tools, but they do recommend techniques. If a part of the test plan needs a lot of small tests - great candidate for massively parallelized simulation. When testing a satellite link, need to pump through lots of data, emulation makes more sense. If they need to prove a control FSM, or sets of FSMs, can never deadlock, this is an obvious candidate for formal. He added, no surprise that techniques like formal are often not in the mainstream for a number of these clients. The review is a chance for them to talk to experts. To get a better understanding of what might be possible if they can stretch a little. They’ll also discuss UVM, C and PSS approaches, assertion-based verification and requirements traceability. Again as appropriate to the needs of the client. Sounds like a valuable service, especially for module makers and system companies. Design teams who don’t live and breathe all the latest and greatest advances in RTL verification. You can learn more about the Arm/Mentor partnership HERE. [post_title] => Arm Design Reviews add Mentor for Verification Review [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => arm-design-reviews-add-mentor-verification-review [to_ping] => [pinged] => [post_modified] => 2020-10-25 06:27:01 [post_modified_gmt] => 2020-10-25 13:27:01 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=292411 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [6] => WP_Post Object ( [ID] => 292419 [post_author] => 19385 [post_date] => 2020-10-26 10:00:38 [post_date_gmt] => 2020-10-26 17:00:38 [post_content] => In an earlier article [1], the resolution limit for the space between paired features was described by the Rayleigh criterion of ~0.6 wavelength/numerical aperture, where the numerical aperture (NA) represented the sine of the largest angle for a ray focused from the lens to a point. It is also given by the radius of the lens divided by the focusing distance (or focal length). Yet, it is quite common practice in semiconductor device lithography to work with images with sizes of, say, ~0.4 wavelength/NA. While it is still possible to have images below the Rayleigh criterion, they will face some fundamental difficulties.

The Rayleigh unit of defocus

For the upcoming discussion, it is important to have a reference scale for defocus. The Rayleigh unit (RU) of defocus (0.5 wavelength/(NA)^2) has been used by many authors [2-6]. The proof is given in [6] and is derived from the optical path difference between a ray traveling along the optical axis and a ray from the edge of the lens (pupil) to the point of focus.

The canary: an isolated feature (line) pair

As a reference we will consider a pair of lines targeted at a width of 0.4 wavelength/NA and separated by the same distance (Figure 1). This pair of lines is repeated as well, at a pitch of 8x the linewidth, i.e., 3.2 wavelength/NA. Also, for simplicity, the object to be imaged is actually an opaque film with only two openings corresponding to the lines. In leading-edge lithography systems, the object is four time (4x) the size of the targeted image on the wafer.
Impact of Defocus
Figure 1. Pair of lines (k1 ~ 0.4), separated by gap of same width (plan view). The pair of line is repeated on a pitch 8x the linewidth.

On-axis illumination

First, we look at the on-axis illumination case, which is simplest. It is also some times referred to as sigma=0, where sigma is the ratio of illumination radius in the pupil to the NA. Under this condition, we find that defocus has a noticeable effect on the observed "pitch", i.e., the center-to-center distance between the two lines (Figure 2).
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Figure 2. Defocus narrows the observed pitch between the two lines, under on-axis illumination. The dotted line indicates the threshold intensity at which the image is printed. Under defocus, both edges of the lines are shifted inward. The underlying reason comes from the diffraction analysis. Under on-axis illumination, the pattern is formed from the interference of seven diffraction orders (labeled -3, -2, -1, 0, 1, 2, 3), separated in spatial frequency at an interval of wavelength/pitch. The normalized electric field amplitudes of the diffraction orders are shown as a spectrum in Figure 3. When defocused, the diffraction orders propagating closest to the NA (-3 and 3) deviate most in optical path from the axis. They determine the positions of the peaks and the trough in between, leading to the narrowed gap.
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Figure 3. Normalized electric field amplitudes for the diffraction orders with and without defocus. At one full Rayleigh unit of defocus, the lines are essentially merged:
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Figure 4. The pair of lines are merged at 1 Rayleigh unit of defocus. Pitch has no practical meaning here as it is completely determined by the focusing of the gap between the lines, which in turn is affected by the true pitch of 8x the linewidth, i.e., 3.2 wavelength/NA.

Slightly off-axis illumination (sigma=0.3, parallel to lines), with truncation of diffraction spectrum

Next, we consider illumination that is slightly off-axis in the direction parallel to the lines. It is about a third of the pupil radius offset from the center. Consequently, the -3 and +3 orders considered significant in the on-axis case are now truncated. The next highest orders, -2 and +2 were not that significant to begin with, so the image is determined mainly by the 0th, -1st and +1st orders. This only allows one peak per pitch (Figure 5).
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Figure 5. With slightly off-axis (parallel to the lines) illumination, the highest diffraction orders from the on-axis case are truncated. This leaves the image mainly determined by orders -1, 0, and 1. Only a single peak may be achieved per pitch. The truncated diffraction order spectrum also looks very similar even under defocus (Figure 6).
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Figure 6. With the truncation of the -3rd and +3rd orders, the diffraction order spectrum is now hardly impacted by defocus. The truncation of the -3rd and +3rd essentially obliterated the target pattern, despite giving much better defocus tolerance. Truncation of the diffraction spectrum also explains enlarged tip-to-tip distance when dipole illumination is used for minimum pitch lines [7], with no help available from optical proximity correction (OPC) [8].

Do Sub-Resolution Assist Features help?

As mentioned in the previous article [1], arrayed features offer a way to go below the Rayleigh criterion. One possibility is to pretend to print an entire array but use subresolution width (or subresolution assist features (SRAFs)) to not print the parts other than the selected locations (Figure 7) [9]. The illumination is also adjusted to match the ideal dipole point locations for the pitch corresponding to the line pair.
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Figure 7. Sub-resolution assist features are an imperfect simulation of an extended array, by means of adding extra features (the outer lines here, plan view) which are too small to print. The impact on the diffraction order spectrum is shown in Figure 8.
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Figure 8. Diffraction order spectrum after SRAFs are applied. The 0th and 4th orders correspond to the 0th and 1st orders of the pitch corresponding to the line pair. This helps reinforce the distance between the lines. However, it also becomes possible to print unwanted lines at the same pitch if the dose is too high. This can be avoided by having the subresolution assist width sufficiently small compared to the main line width. This is the role of the other diffraction orders. However, with the other orders remaining significant, the defocus affects linewidth quite significantly. Moreover, there is still some pitch walking due to defocus (Figure 9).
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Figure 9. Defocus causes some pitch walking even when SRAFs are used, pushing the lines slightly further apart. The defocus causes the lines to shift away from each other, unlike the on-axis illumination case without SRAFs. The +1st order is the dominant influence here. At just a little over 1 Rayleigh unit of defocus, the lines disappear (Figure 10).
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Figure 10. At a little over 1 Rayleigh unit of defocus, the line pair disappears, despite the use of SRAFs. Thus, the SRAF approach does not offer much improvement of the defocus tolerance. By continuing to increase the defocus, to double this value, we see more clearly the extent of continued pitch walking through defocus:
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Figure 11. At 2.1 Rayleigh units of defocus, the extent of pitch walking even when using SRAFs is very clear. The assist feature is essentially a "blur" on the outside of the pair of lines. As the lines are defocused, they more easily merge with the "blur" than each other, thus moving them outward instead of inward.

How to print the target feature while preserving pitch through defocus?

It is now clear that the target feature as drawn in Figure 1 cannot be printed directly without issues of pitch preservation through defocus and the above approaches cannot even preserve the image up to 1 Rayleigh unit of defocus. Other approaches described in [1] may be applied: (1) double patterning or (2) patterning an array (in the true sense, not with SRAFs) and then trimming to keep only the pair in question. The second option has better overlay tolerance with self-aligned patterning, e.g., see [10].

Conclusion

Pitch is not practically fixed for an isolated pair of features as it is vulnerable to defocus. Some non-optimal illuminations completely wipe out any appearance of pitch. It can only be appropriate to apply pitch to describe truly arrayed features.

Appendix: Rayleigh unit of defocus

In this section, we present the proof of the derivation of the Rayleigh unit of defocus, from [6]. The idea is to calculate the optical path difference between a ray from the lens center traveling down the axis and a ray from the edge of the lens to the focal point. The distance along the axis over which the path difference ranges from zero to a quarter wavelength gives the depth of focus. Basically, two waves which are 90 degrees out of phase (corresponding to a quarter wavelength difference) would not interfere with each other but effectively add in quadrature as if incoherent. The path difference for an axial distance D and angle theta between the two rays is given by D(1-cos(theta)) ~ D * 2* (sin(theta/2))^2. Estimating sin(theta/2)~NA/2 gives D * 2 * (NA/2)^2 equal to the quarter wavelength, which in turn gives D = (1/2) wavelength/(NA)^2.

References

[1] https://www.linkedin.com/pulse/lithography-resolution-limits-paired-features-frederick-chen/ [2] https://www.jstage.jst.go.jp/article/photopolymer1988/2/3/2_3_375/_pdf [3] H. J. Levinson, Principle of Lithography, SPIE Press, 2005, p. 35. [4] https://patents.google.com/patent/US6327033 [5] W. B. Glendinning and J. N. Helbert (ed.), Handbook of VLSI Microlithography: Principles, Technology and Applications, Noyes Publications, 1991, p. 273 [6] L. F. Thompson, C. Grant Willson, and M. J. Bowden, Introduction to Microlithography, ACS, 1994, p. 76. [7] M. Eurlings et al., Proc. SPIE 4404, 266 (2001). [8] T. Matsuda wt al., Proc. SPIE 7973, 797316 (2011). [9] https://vlsicad.ucsd.edu/Publications/Conferences/186/c186.pdf [10] https://www.cerc.utexas.edu/utda/publications/C117.pdf [post_title] => Impact of Defocus and Illumination on Imaging of Pitch [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => impact-of-defocus-and-illumination-on-imaging-of-pitch [to_ping] => [pinged] => [post_modified] => 2020-10-26 14:27:43 [post_modified_gmt] => 2020-10-26 21:27:43 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=292419 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [7] => WP_Post Object ( [ID] => 292141 [post_author] => 11830 [post_date] => 2020-10-26 06:00:20 [post_date_gmt] => 2020-10-26 13:00:20 [post_content] => [caption id="attachment_292168" align="aligncenter" width="1600"]Silicon Lfecycle Management Silicon Lfecycle Management[/caption]

SLM.  It’s a TLA (three-letter acronym) that you’ll be hearing more about. It stands for silicon lifecycle management and it has the potential of re-defining the role of EDA in the entire electronics ecosystem. A working definition of SLM is “monitoring, analysis and optimization of semiconductor devices as they are designed, manufactured, tested and deployed in end user systems.” These are ambitious, far-reaching goals. To achieve them requires substantial technology for both chip design as well as IP development for the sensors that implement the “monitoring” part. Realizing the vision touches many parts of the design to manufacturing ecosystem. In short, a major industry player is required. So, when Synopsys recently announced its new silicon lifecycle management platform, covered on SemiWiki here, I definitely took notice.

For SLM to deliver on its mission, there needs to be specialized monitors embedded in the chip to gather data about the chip’s performance and environment. Some analysis of the data will be done on chip, but most will be done in the cloud, so a communications backbone and deep data analytics are needed as well. In addition, the design flow needs to support efficient and effective integration of the monitoring IP in the design. Introducing this technology cannot impact chip performance.

As the number one EDA supplier and the number two IP supplier in the industry, Synopsys is well-positioned to address these challenges. I recently had the chance to speak with Steve Pateras, senior director of hardware analytics and test marketing at Synopsys. Steve has substantial experience in IC test from Mentor Graphics, LogicVision and IBM before joining Synopsys. He took me on a rather compelling tour of the new Synopsys SLM platform.

Why SLM, Why Synopsys?

We started by discussing the motivation for a silicon lifecycle management platform. Why was it needed, and what does Synopsys bring to the table? Steve explained that semiconductors are now part of more products and systems than ever before. Many of these systems have substantial performance and reliability requirements. Missing the mark can have impact on people and societies. Consider high-performance computing, hyperscale data centers, autonomous vehicles, mass transportation and industrial IoT. Performance or reliability compromises can impact human life and well-being in significant ways for these kinds of applications.

What this means is that design analysis and optimization can no longer end with chip delivery. It needs to continue throughout the life of the device if performance and reliability are to be maintained in the field. Steve explained that Synopsys aims to achieve these goals with a holistic approach by closing the silicon loop to optimize all phases of the silicon lifecycle. Components of the solution include industry-leading IP, implementation, verification and test solutions. Steve spent some time to elaborate how the pieces fit together.

Gathering the Data

Synopsys provides non-intrusive monitor and sensor IP that are embedded in chip designs. This IP acquires real-time process, voltage, temperature and structural operational data via a transport layer that brings the data off chip and into the cloud for analysis. Local, on-chip data analysis is also supported.

Automated integration of this IP into the RTL or gate-level design is provided through the Synopsys TestMAX™test integration solution which, when coupled with the Fusion Compiler™ RTL-to-GDSII solution for synthesis and physical implementation, ensures the monitors are integrated while maintaining optimal power, performance, and area (PPA) design metrics. The SLM platform links TestMAX to Synopsys’ signoff analysis tools for guidance on where to optimally place the monitors and sensors.

Analyzing the Data

Next, Steve explained that once the data is acquired from either manufacturing test or field operation, it is processed by several targeted analytics engines. PrimeShield closes the loop on design implementation by leveraging both silicon data-based timing model calibration to minimize required margins as well as advanced analytics to further optimize design PPA, reliability and silicon predictability.

The SiliconDash™ semiconductor manufacturing analytics engine and the Yield Explorer™ design yield analysis engine use fab and test data enhanced with monitor and sensor data to optimize manufacturing and test operational efficiencies as well as improve overall yield. The platform also features two additional analytics engines, an Adaptive Learning Engine and an Embedded Learning Engine, that enable optimized test bring-up and introduce self-analysis and predictive maintenance capabilities during the in-field operation of the chip. The figure below summarizes the capabilities and technologies embodied in the Synopsys SLM platform. 

[caption id="attachment_292169" align="aligncenter" width="525"]Synopsys SLM Platform Capabilities Synopsys SLM Platform Capabilities[/caption]

Looking to the Future

Steve ended our discussion with a forward view of what this all means. The Synopsys SLM platform sets a new bar for how devices can be monitored, from design to deployment. He explained that ongoing monitoring and optimization of performance and reliability is now a lifelong process. The new platform from Synopsys closes the silicon loop to enable a new way forward in chip design and ongoing maintenance.

You can learn more about the new silicon lifecycle management platform from Synopsys here.

[post_title] => Synopsys Enhances Chips and Systems with New Silicon Lifecycle Management Platform [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => synopsys-enhances-chips-and-systems-with-new-silicon-lifecycle-management-platform [to_ping] => [pinged] => [post_modified] => 2020-10-25 19:34:35 [post_modified_gmt] => 2020-10-26 02:34:35 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=292141 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [8] => WP_Post Object ( [ID] => 292342 [post_author] => 16 [post_date] => 2020-10-25 10:00:34 [post_date_gmt] => 2020-10-25 17:00:34 [post_content] => I attended one of the Arm partner events in Cambridge many years ago, when they first talked about the coherent hub for managing cache coherence. I was impressed, but the obvious question even then was how any non-Arm IP was going to hook into this hub. They had a solution, of course, the ACE interface, and I left satisfied. As is the way with these things, that solution was good for a while. But System-on-Chip (SoC) architectures continued to evolve and get more complex. Pushing for cache coherence everywhere. Now video and hardware accelerator streams dominate a lot of processing with high levels of parallelism, not only in the CPU cluster but also in AI accelerators among other IPs. As more processing elements are added the complexity of the software to simply manage the data flow explodes, so we’re starting to see hardware cache coherence everywhere across the SoC. (I was surprised to learn that even Mali is non-native on the CHI interface; it still connects through ACE.) Cache Coherence Everywhere

Coherency challenge in a heterogenous system

The figure here illustrates the challenge. Of course, you can connect all your own IP into the coherent interconnect as long as they support CHI, ACE or ACE-Lite interfaces. But being able to connect isn’t the end of your problems. The interconnect is no longer serving just the needs of that high-speed CPU cluster. Now it has to service a wide variety of bandwidth demands, varying levels of QoS need, and some traffic expecting real-time support. Anything that doesn’t have coherency support, you’ll have to do development work to add an appropriate interface. It shouldn’t be a surprise that meeting all these conflicting needs is going to be hard. Maybe impossible.

Topology challenges

There’s another problem – interconnect topology. SoCs of this type tends to be big, even extending to multi-die in package implementations. Generic mesh and crossbar connectivity would be wildly impractical, consuming huge levels of real estate. This is also true inside AI accelerators. So designers have explored different ways to structure interconnect topologies. Trees - popular in earlier crossbar-based designs. Mesh networks – Arm offers an option here. Rings and Torii. All ways to distribute connectivity across chip-scale distance without needing to overload a central point of coherence. Inconveniently, SoC integrators are saying they need mixtures of all these options to create an interconnect optimized for their requirements. Could you fake it with a mesh network? Apparently not as efficiently, in part because in a mesh, communication has to jump from node to node to node to cross long distances. You could drop otherwise unused nodes in the mesh, but apparently, that still can’t rise to the performance levels of other options.

The advantages of a coherent NoC

What you really want is coherency, but with all the distance spanning, low congestion, and tunable QoS advantages of a Network-on-Chip (NoC). A NoC in which the central transport function of the interconnect is independent of the IP protocols attached to it. Each interface – CHI, ACE, ACE-Lite and AXI (non-coherent) – can connect through an interface to the transport layer. Designer-guided tuning across the die can optimize impact on floorplan. And bandwidth, QoS and latency can be optimized through designer choices and configuration software automation on connections and choice of switches. Coherency in the network is managed through one or more snoop filters in directories. And IP with non-coherent interfaces (e.g. AXI) can connect through an adapter with a proxy cache to allow participation as equal citizens in the cache coherent system. This is what Arteris IP offers in their Ncore 3 coherent interconnect. NoC reach, connect any protocol and QoS management with coherency. Pretty impressive. You can learn more about Ncore 3 here and at the upcoming Linley conference. [post_title] => Cache Coherence Everywhere may be Easier Than you Think [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => cache-coherence-everywhere-may-be-easier-than-you-think [to_ping] => [pinged] => [post_modified] => 2020-10-23 06:39:08 [post_modified_gmt] => 2020-10-23 13:39:08 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=292342 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 4 [filter] => raw ) [9] => WP_Post Object ( [ID] => 292326 [post_author] => 13 [post_date] => 2020-10-25 08:00:50 [post_date_gmt] => 2020-10-25 15:00:50 [post_content] => Cadence made waves a while back with its innovative Clarity 3D Solver, a FEM solver for near field EM analysis. Now they are shaking things up with their new far field Clarity 3D Transient Solver. System level EMI and EMC analysis has often exceeded the limits of simulation tools, leading to expensive and time-consuming prototype development and measurement. Previous solvers were not architected for parallel processing and suffered from capacity limitations. EMI and EMC are extremely important in consumer electronics, automotive systems and healthcare devices. Each of these markets can benefit from high accuracy, high capacity far field EM simulation. Medical devices often require optimized wireless communications, especially when interacting with the human body. Likewise, there are strict criteria necessary for device safety. Consumer electronics designs often have to trade off emissions, antenna placement, cooling, specific absorption rates (SAR) and other factors to arrive at a carefully balanced solution. [caption id="attachment_292327" align="aligncenter" width="1063"]Clarity 3D Transient Solver Clarity 3D Transient Solver[/caption] I recently had a call with Cadence Product Management Group Director for Multi-Physics System Analysis Brad Griffin to go over the features and capabilities of their new Clarity 3D Transient Solver. He pointed out that the solver can use GPUs or CPUs to achieve nearly linear scaling of runtime with increased processors. Because it can use hundreds of processors the capacity is practically unbounded. Cadence also offers access to the Clarity 3D Transient Solver through their Cloudburst Platform that runs in the cloud. Access to Cadence tools is optionally provided through the Cloudburst web interface which also enables high throughput file transfers of design data.  This virtually eliminates IT overhead for cloud accessibility for Cadence customers and offers massive scalability when needed. Brad talked about their pre-announcement engagement with Ultimate Technologies, an EMI/EMC testing company, that was able to compare Clarity 3D Transient Solver results to actual measurement data. The solver was very accurate and enabled their automotive customers to pass EMI testing months sooner, often saving as much as 30% of the design cycle time. Simulation allowed rapid iterations to get to the final passing version of the systems. According to Brad, board level screening can be accomplished with Sigrity Aurora in-design analysis to catch many common design mistakes that produce excessive EMI. Then the entire system, including enclosures, etc. can be run with high accuracy in the Clarity 3D Transient Solver. Similarly, near field simulation models can be generated in their 3D FEM solver and supplied to the Clarity 3D Transient Solver to assist in getting the most comprehensive results. The solver is fully integrated with Cadence chip, package and PCB design tools. CAD data from 3D mechanical design tools can also be imported into the Clarity 3D Transient Solver. When the MCAD data is merged with Cadence electrical CAD design data, not only can problems be found, but they can be fixed and re-simulated.  Brad emphasized that the combined design and analysis solution makes the EMI signoff task much more efficient than when just point tools are used for analysis. Cadence has shown a consistent and strong execution of a complete flow for designing electronic products and systems. With the Clarity 3D Transient Solver they have moved into new territory. In many markets, such as automotive, much more complex systems are being designed that have interactions with each other and their operating environment. It’s good to see well integrated solutions that can scale with the complexity of the design challenges. More information about Cadence’s new Clarity 3D Transient Solver can be found on the Cadence website.         [post_title] => Clarity 3D Transient Solver Speeds Up EMI/EMC Certification [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => clarity-3d-transient-solver-speeds-up-emi-emc-certification [to_ping] => [pinged] => [post_modified] => 2020-10-25 07:54:03 [post_modified_gmt] => 2020-10-25 14:54:03 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=292326 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) ) [post_count] => 10 [current_post] => -1 [in_the_loop] => [post] => WP_Post Object ( [ID] => 292459 [post_author] => 3 [post_date] => 2020-10-29 10:00:18 [post_date_gmt] => 2020-10-29 17:00:18 [post_content] => I've used OLED (Organic Light-Emitting Diode) displays for many years in my monitors, laptops, tablets, e-readers and smart phones; and knew that the AMOLED (Active-Matrix OLED) displays used thin-film transistor technology where each pixel can be controlled, but I hadn't considered the actual design process until Chen Zhao from Empyrean brought up the topic. What follows is part one of a Q&A discussion, where I learned about the design challenges of Flat Panel Design (FPD) and how automation is being applied. Q: Can you give me a brief history of FPD technology? After years of persistent efforts, traditional flat panel display (FPD) technology such as liquid crystal display (LCD) has made considerable progress1. Advanced technologies such as organic light-emitting diodes (OLED)2 and flexible panels3 have also make breakthroughs, and the industry share has also greatly increased. Q: What is the FPD design flow like? Like integrated circuit design, electronic design automation (EDA) is also the cornerstone of FPD circuit design. The FPD design flow includes panel circuit schematic design, layout design, circuit simulation, circuit layout parasitic parameter extraction, circuit design verification, etc. It is similar to analog integrated circuit design flow, but also has its unique design flow and design methodology. [caption id="attachment_292460" align="alignnone" width="850"]FPD design flow min FPD Design Flow[/caption] Q: How was FPD design approached in the early days? The design flow of early domestic display panels was realized by point tools from multiple EDA tools. Because users need to switch frequently between these manufacturers’ EDA tools, the design flow is cumbersome, data compatibility and confidentiality are not good enough, and problems are not easy to track down. It will cause mutual wrangling, inefficiency, delays in construction, and will deteriorate product quality. In addition, these tools are basically tools from integrated circuit design, and they are obviously lacking in solving the unique professional needs of display panels and customized development. Q: Instead of using point tools, what is a more efficient and elegant approach? In order to solve various FPD problems of users, it is urgent to develop an EDA full-flow solution for FPD design. All tools are seamlessly integrated on a unified EDA platform to make the FPD design flow efficient and smooth, ensure design quality, and improve design effectiveness. At the same time, in order to meet the ever-changing design requirements of high-end and new FPD and the customization requirements of domestic customers, it is necessary to continuously develop new functions and new products to improve the leadership of FPD EDA tools. Q: What specific tools has Empyrean put together for the design of FPD? EMPYREAN has launched the world's only FPD full-flow design system. Shown below are the main tools of the system, including TCAD, SPICE modeling, circuit schematic design, layout design, circuit simulation, circuit simulation waveform analysis, parasitic RC extraction, layout physics and electrical verification, full design layout analysis, and mask analysis, etc., to achieve full flow coverage, smooth data transfer, and to greatly improve design efficiency. [caption id="attachment_292462" align="alignnone" width="1100"]Empyrean FPD full design flow min Empyrean FPD Full Design Flow[/caption] Q: Does this Empyrean design flow work only for LCD designs? In addition to achieving the world’s only FPD design full-flow solution, on the basis of meeting LCD conventional design, EMPYREAN keeps up with the forefront of FPD design requirements, especially for the current popular and advanced fields such as curvilinear-shaped design, OLED high-end display, and touch panel4. EMPYREAN has pioneered a series of supporting design technologies, which enable FPD design to a new level and allow display companies to enter the high-end display field. Q: How are the TFT devices simulated, and what models are being used? EsimFPD Model is a SPICE model parameter extraction and optimization software specially designed for FPD by EMPYREAN. The traditional thin film transistor (TFT) RPI model has many problems in terms of model accuracy of amorphous silicon (A-Si)5 and low temperature polysilicon (LTPS)6. After years of continuous development and improvement, the R&D team of EMPYREAN has greatly improved the accuracy of the model in terms of temperature effect, sub-threshold area, leakage current and other important device characteristics7. Taking into account the impact of process fluctuations on device characteristics, we have improved the traditional modeling methodology. Based on a large number of sampled data, we have performed statistical analysis on the device characteristics, and extracted process corner model and statistical model, which will help to reserve the smallest possible reasonable margin for subsequent FPD circuit design, and improve product performance and yield. Q: What are the challenges of defining an accurate model? In order to further improve the accuracy of model, based on the geometric dependence of device physics, we considered the geometry dependency of device characteristics with gate length and width of TFT devices, and developed the so-called bin model which can cover big geometry area8. Our work has been extended to support new devices such as OLED, oxide semiconductor TFT (IGZO)9, and Micro-LED10. In addition, we support reliability modeling of TFT devices5,6,9, including DC/AC stress model, hysteresis model, and image-sticking model, etc. The device reliability model can be used in circuit simulation tools to analyze the long-term reliability of FPD circuits. The next figure shows the fit of our stress model. [caption id="attachment_292470" align="alignnone" width="650"]Fitting of stress model min Fitting of stress model[/caption] Summary FPD technology enables many consumer and industrial products that allow us to visualize information every day on our smart phones and monitors, and the design challenges for displays increases with each new product generation. Empyrean has nine tools that work in concert to form a full design flow for FPD products, and in part two I'll cover topics like:
  • Design technology of curvilinear-shaped FPDs
  • FPD layout design
  • FPD layout verification
  • Hierarchical FPD circuit simulation
  • RC extraction and analysis
  • Thermoelectric analysis
  • Mask analysis
  • Job file automation

References

  1. Xiang Feng, Xiao Sun, Qiang Zhang, Dan Wang, “Development Trend of LCD Technology”, Invited Paper, SID Symposium Digest of Technical Papers, 2018
  2. Ho-Kyoon Chung, Hye-Dong Kim, Boris Kristal, “AMOLED Technology for Mobile Displays”, Invited Paper, SID Symposium Digest of Technical Papers, 2012
  3. Chang‐Xiang Wu,Yen‐Lin Pan,Hung‐Ming Tsai,“Modeling and Analysis of the Flexible Touch Panel on the Flexible Active-matrix OLED Display”,SID Symposium Digest of Technical Papers, 2014
  4. Wei-Feng Zhou,Li-Qiang Chen,David Wang,“ New Full Screen Flexible AMOLED Solution with Fingerprint”, Invited Paper, SID Symposium Digest of Technical Papers, 2018
  5. Ching-Chieh Shih, Yeong-Shyang Lee, Kuo-Lung Fang, Ching-Hung Chen, and Feng-Yuan Gan, “A Current Estimation Method for Bias-Temperature Stress of a-Si TFT Device”, IEEE Trans. Dev. And Mat. Reliability, Vol. 7, No. 2, pp. 347, 2007
  6. Kim et al, “Investigation of the Instability of Low-Temperature Poly-Silicon Thin Film Transistor under a Negative Bias Temperature Stress”, Electron. Mater. Lett., Vol. 9, 2013
  7. Lifeng Wu, “An introduction of OLED/TFT device model and FPD design flow”, Invited Paper, MOS-AK Compact Modeling Workshop, Beijing, China, June 2018
  8. AnThung Cho, Lifeng Wu, Qionghua Mo, James Hsu, Kaijun Liu, Justin, Yunqin Hu, Wade Chen, York Lu, Xiaobin Fan, and Scott Lin, “Corner and Binning Model Simulation of TFT for GOA Driver Circuit in G8.6 Large-size TFT-LCDs”, International Display Workshops, Nagayo, Japan, December 2018
  9. Ken Hoshino, David Hong, Hai Q. Chiang, and John F. Wager, “Constant-Voltage-Bias Stress Testing of a-IGZO Thin-Film Transistors”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 7, 1365, JULY 2009
  10. Brian R.Tull, Nancy Twu, Yu-Jen Hsu, “Micro-LED Micro displays by Integration of III-V LEDs with Silicon Thin Film Transistors”, Invited Paper, SID Symposium Digest of Technical Papers, (246-248), 2017
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