In the fast-paced world of AI development, bridging the gap from trained models to production-ready applications can feel like an eternity. Enter Semidynamics’ newly launched Inferencing Tools, a game-changing software suite designed to slash deployment times on the company’s Cervell RISC-V Neural Processing… Read More
A Compelling Differentiator in OEM Product DesignJennifer, an OEM hardware designer, is planning a…Read More
Pioneering Engineer Dr. Tsu-Jae King Liu to Receive Semiconductor Industry's Top HonorIn a landmark recognition of trailblazing innovation and…Read More
PDF Solutions Charts a Course for the Future at Its User Conference and Analyst DayEvery major supplier has its user event. This…Read More
Synopsys and NVIDIA Forge AI Powered Future for Chip Design and Multiphysics SimulationIn a landmark announcement at NVIDIA's GTC Washington,…Read MoreAdding Expertise to GenAI: An Insightful Study on Fine-Tuning
I wrote earlier about how deep expertise, say for high-quality RTL design or verification, must be extracted from in-house know-how and datasets. In general, such methods start with one of many possible pre-trained models (GPT, Llama, Gemini, etc.). To this consultants or in-house teams add fine-tuning training, initially… Read More
EDA Has a Value Capture Problem — An Outsider’s View
By Liyue Yan (lyan1@bu.edu)
Fact 1: In the Computer History Museum, how many artifacts are about Electronic Design Automation (EDA)? Zero.
Fact 2: The average starting base salary for a software engineer at Netflix is $219K, and that number is $125K for Cadence; the starting base salary for a hardware engineer at Cadence is $119K… Read More
WEBINAR: How PCIe Multistream Architecture is Enabling AI Connectivity
In the race to power ever-larger AI models, raw compute is only half the battle. The real challenge lies in moving massive datasets between processors, accelerators, and memory at speeds that keep up with trillion-parameter workloads. Synopsys tackles this head-on with its webinar, How PCIe Multistream Architecture is Enabling… Read More
A Six-Minute Journey to Secure Chip Design with Caspia
Hardware-level chip security has become an important topic across the semiconductor ecosystem. Thanks to sophisticated AI-fueled attacks, the hardware root of trust and its firmware are now vulnerable. And unlike software security, an instantiated weakness cannot be patched. The implications of such vulnerabilities are… Read More
Lessons from the DeepChip Wars: What a Decade-old Debate Teaches Us About Tech Evolution
The competitive landscape of hardware-assisted verification (HAV) has evolved dramatically over the past decade. The strategic drivers that once defined the market have shifted in step with the rapidly changing dynamics of semiconductor design.
Design complexity has soared, with modern SoCs now integrating tens of billions… Read More
Think Quantum Computing is Hype? Mastercard Begs to Disagree
Just got an opportunity to write a blog on PQShield, and I’m delighted for several reasons. Happy to work with a company based in Oxford and happy to work on a quantum computing-related topic, which you’ll find I will be getting into more deeply over coming months. (Need a little relief from a constant stream of AI topics.) Also important,… Read More
CEO Interview with Sanjive Agarwala of EuQlid Inc.
Sanjive Agarwala is co-founder and CEO of EuQlid, a quantum technology company, developing novel 3D imaging tools to support the design and manufacturing of semiconductors and batteries.
Prior to EuQlid, Sanjive served as Corporate Vice President and General Manager of the IP Group at Cadence Design Systems. His business included… Read More
CEO Interview with Rodrigo Jaramillo of Circuify Semiconductors
With over 18 years of experience in the semiconductor industry, Rodrigo Jaramillo is the Co-Founder and CEO of Circuify Semiconductors, an engineering design solutions startup based in Guadalajara, Mexico. Circuify provides ASIC, SoC, and Chiplet design services for the North American semiconductor industry, with experience… Read More
Predicting EUV Stochastic Defect Density with Electron Noise and Resist Blur Models
Recently, the statistics of secondary electron noise and its impact on defect probability in EUV lithography has been directly addressed for the first time[1]. In this article, we will take into account some updated blur models for EUV resists, both of the chemically amplified (CAR) and metal oxide (MOR) types.
First, let’s review… Read More



PDF Solutions Charts a Course for the Future at Its User Conference and Analyst Day