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                    [post_date] => 2020-03-30 06:00:51
                    [post_date_gmt] => 2020-03-30 13:00:51
                    [post_content] => Having the right tool for the job at hand is always a joy, and when your IC project involves RTL code, gates, transistors and even parasitic interconnect, then you need some EDA tool help for debugging and finding out why your design behaves the way it is. An FAE named Sujit Roy did a conference call with me last week to show what StarVision Pro can do with mixed-signal design debug. Sujit works at EDA Direct, a company started in 1997 providing EDA tools from Mentor, Cliosoft and Concept Engineering, along with training and services.

The StarVision Pro tool comes from Concept Engineering, an EDA company from Germany that has been in business for three decades now. I first heard about Concept Engineering about 18 years ago, because the EDA company that I worked at had a need to visualize SPICE netlists as schematics to better understand circuit simulation results from a Fast SPICE tool. It's been rewarding to see the growth of features as StarVision Pro has expanded its scope to cover so many input file formats:

[caption id="attachment_284108" align="alignnone" width="960"]starvision pro StarVision Pro[/caption]

The wow moment is when you read in a file format and then quickly visualize an automatic schematic, neatly laid out with inputs on the left and outputs on the right showing you all of the interconnect, cell instances and hierarchy. Circuit designers, logic designers and even DFT engineers can each benefit from quickly seeing how an SoC is assembled. For logic verification you can even see the logic state on each net in a design as a function of time.

During a live demo on a laptop running Linux I saw Sujit read in a digital design, and this works even if your design is incomplete, missing IP or has syntax errors. Just look at how neat the auto-generated schematic appears:

[caption id="attachment_284112" align="alignnone" width="850"]rtl schematic 850 min Auto-generated schematic[/caption]

Useful debugging features include:
  • Click any net and dynamically expand a cone of logic
  • Cross-probe between schematic and RTL source code
  • Search for nets by filtering a name
  • Trace an internal net to an IO pin
In the screenshot above we've loaded in logic simulation results from a VCD file, then moved to a specific time point in the simulation run, and finally visualize the logic state on our nets. This kind of visual debug really speeds up the functional verification process to find and fix bugs. The next design file to be read in was from a parasitic extraction tool as a SPEF file, so we can quickly see the RC values that make up a net.  This screenshot shows how you can click on the schematic and cross-probe into the source file: [caption id="attachment_284117" align="alignnone" width="850"]parasitic cross probe min Parasitic Interconnect Cross-Probing[/caption] An engineer can then find which nets are the heaviest loaded, and Sujit ran a pre-built script that allowed him to filter and remove all capacitors below a threshold value. A SPICE netlist was loaded, and we viewed the MOS transistors, along with some parasitic capacitors: [caption id="attachment_284119" align="alignnone" width="850"]spice netlist min SPICE netlist[/caption] Next, we wanted to know what had changed in a SPICE netlist over time, so a DIFF script quickly highlight where the differences were located by showing that net n6 was modified: [caption id="attachment_284120" align="alignnone" width="850"]n6 min Net n6 was modified[/caption] StarVision Pro comes with some 100 scripts, so I got the idea that they had automated most debugging tasks for me, saving me time from having to write my own scripts. Of course, you can always just view the Tcl source code for the scripts, and create new derivatives and combinations to make your debugging happen faster. Videos On YouTube there's a channel for EDA Direct, and they've recorded over a dozen intro videos on specific StarVision Pro topics, and each video is brief at under 2 minutes of viewing time: https://www.youtube.com/watch?v=0uKj0GOb08c&t=24s Summary Designing, verifying and re-using mixed-signal chips and IP blocks can be a tedious and error-prone task, especially since most of the file formats are textual, which makes them difficult to understand as part of a larger or hierarchical design. Using an automatic visualization tool like StarVision Pro is sure to save you hours and days of engineering effort, because now you can see the structure of your IC design, along with simulation values in an intuitive schematic format. Circuit designers, logic designers, DFT engineers and verification engineers can all benefit by adding a tool like this to their methodology. Related Blogs [post_title] => Mixed-Signal Debugging Gets a Boost [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => mixed-signal-debugging-gets-a-boost [to_ping] => [pinged] => [post_modified] => 2020-03-26 10:56:02 [post_modified_gmt] => 2020-03-26 17:56:02 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=284107 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [1] => WP_Post Object ( [ID] => 284241 [post_author] => 14 [post_date] => 2020-03-29 14:00:50 [post_date_gmt] => 2020-03-29 21:00:50 [post_content] => US China Blockade Blocking chip sales to Huawei back on front burner Covid19 & China Trade are equally bad Long lived Uncertainty could "plague" industry sales going forward Political Predictability worse than Disease Predictability Reuters broke a story today that the proposed licensing of chip equipment to prevent "bad actors" getting chips made on US equipment was back on again, after many, including ourselves, thought it was a dead issue at least during Covid19. Reuters Article on Chip Equip Blockade Apparently at a meeting yesterday, cabinet officals agreed to change the "Foreign Direct Products Rule" such that licenses would be required by foreign users of US technology which would allow the US to prevent "bad actors" (read that as Huawei) from getting chips made on US chip equipment (AMAT, LRCX. KLAC et al) or equipment using US technology (ASML). This rule change still needs presidential approval and Trump has previously been hesitant to support this but in light of the current bad relations with China over Covid19 his tune may have changed. We were both right and wrong...very bad luck We had joked in a prior note that: "It would be a case of very bad luck if just when we start to get over the pandemic that the government would step in and halt sales that just restarted....... Like getting over a bad case of the flu only to walk outside and get hit by a truck...." Haircut becomes Crewcut - March 10th We were also wrong in our most recent note in which we suggested that it it would be crazy and unthinkable that the administration would go forward with the blockade. "We think the likelihood of that happening any time soon is just about zero as the US can't do anything to upset China as China supplies 90% of our pharmaceuticals, the majority of our PPE (personal protective equipment) like masks, and probably a lot of ventilators." Covid19 Cycle I guess we don't care if China cuts off our supply of medicine or PPE or ventilators at the worst possible time in retribution for us cutting off Huawei...... The only take away thats clear is that the predictability of Covid19 is better than the predictability of politics which remains a loose, wild cannon.... Embargo collision course with Taiwan and TSMC Back in February when the embargo discussions hit a high note we talked about the collision course we were setting ourselves up for with Taiwan and TSMC... China Chip Equip Embargo We are now obviously back on that collision course and will be taking some of our allies along with us form the ride wether they like it or not.  Most notably will be the Netherlands and ASML which did not ship an EUV tool to China due to pressure from the US. The proposed rule change also includes equipment made with US technology which is a clear definition of ASML's EUV tools as the heart and soul of the tool is the EUV source invented and made in the USA by former Cymer in San Diego. At the time of the sale of Cymer to ASML there were security concerns and we could imagine that there may have been secret agreements or assurances about control of that technology that were agreed to in order to win approval of that deal. Aside from the collision course with TSMC the rule could essentially halt all equipment sales to China as there would be no way that a Chinese chip making company would agree to not sell to Huawei (let alone TSMC). We would be back to a virtual death sentence for Chinese Chip companies much like the now dead and buried Jinhua. But the collateral damage would be putting US equipment makers in the intensive care unit as China is the fastest growing and most significant part of their business. Where would this put the US vis a vis Taiwan? TSMC is the crown jewel of Taiwan which remains a short boat ride away from China and between a rock and a hard place. Much as China was very upset with the Netherlands over the ASML EUV embargo, China would absolutely freak out if Taiwan stopped selling critical, 5G chips to Huawei. It would be much worse than a slap in the face. Obviously things could quickly cascade into a very bad nightmare scenario with China retaliating and halting medical sales to the US or something similarly critical. Starting another plague to add to the first It seems as if the timing couldn't be much worse, just as the economy is in a free fall lets cut off chip equipment sales to China and start another trade war. We hope this is political posturing or something similar.  The problem is that we are concerned with the current rhetoric involving China and Covid19 and the need for someone to blame and retaliate against to generate support and re-direct angst. But as we have previously mentioned, California is not high on the list of the current administrations supporters and most chip equipment companies are there so there may be less concern about the collateral damage generated by opening a second front of a war with China. Stocks hate uncertainty It is always the case that investors hate uncertainty more than almost anything else.  Even more uncertainty than Covid19 has just been added to chip equipment stocks at just the worst time. Its hard to image the stocks getting any more unstable than they already are but this embargo could easily be it. With the stock wildly gyrating up and down 5% and 10% mper day with little stability in sight let alone a firm bottom, we are hard pressed to get back in even though the stocks are relatively cheap. The problem is that they could get cheaper and the China embargo could go on much, much longer , long after Covid19 is a distant memory. [post_title] => Newsflash Chip Equip Blockade back on! [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => newsflash-chip-equip-blockade-back-on [to_ping] => [pinged] => [post_modified] => 2020-03-29 21:14:31 [post_modified_gmt] => 2020-03-30 04:14:31 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=284241 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 3 [filter] => raw ) [2] => WP_Post Object ( [ID] => 284246 [post_author] => 19 [post_date] => 2020-03-29 12:00:27 [post_date_gmt] => 2020-03-29 19:00:27 [post_content] => Shut Uber Down Now
By now it is pretty clear that everywhere outside of China and South Korea human beings are doing a lousy job of "social distancing," locking down, and sheltering in place. This is unfortunate because experts agree that only a complete lockdown will stop COVID-19 from infecting millions, continuing to kill thousands, overwhelming healthcare systems, and devastating the global economy. Nowhere is this failure to shut down more apparent than in our willingness to allow taxis and ride hailing operators to continue to operate without safety partitions. This lax approach to COVID-19 policy must end. The onset of COVID-19 has exposed an essential weakness of the transportation gig economy - the lack of safety partititions in ride hailing vehicles. In fact, the pervasive competitive influence of ride hailing operators such as Uber and Lyft in the U.S., led, in 2016, to the New York City Taxi and Limousine Commission dropping the requirement for a safety shield in yellow taxis. The NYTLC predicated its decision on the need for taxis to be able to be more personal in order to more effectively compete with Uber and Lyft. What the agency seemed to have forgotten at the time, five years ago, is that prior to the institution of the safety shields more than 40 taxi drivers were being murdered every year. The installation of safety shields nearly completely eliminated these fatal encounters. We now have potentially fatal encounters of an entirely different kind - drivers, who may be infected with the coronavirus, driving passengers who may be infected with the coronavirus, creating a powerful vector for spreading the disease across the landscape. While taxi and ride hailing business is down 60%-70% - drivers can still handle 10-20 fares a day any one of which or all of which may be or become "spreaders" of the disease. What is the response from Uber and Lyft? Encourage drivers and passengers to wash their hands, wear masks, don't touch your face, and, my favorite: ROLL THE WINDOWS DOWN! Seriously? Roll the windows down as an anti-COVID-19 measure? Serious social distancing or lockdown policy must forbid the use of taxi or ride hailing service providers unless the individual operators have a certified safety shield permanently installed in their vehicles. There is a reason we have regulatory agencies overseeing the taxi industries. The lives of passengers and drivers are at stake. There are well understood safety measures in place that were created decades ago when drivers were being routinely assaulted and, in some cases, killed by anonymous passengers. Airlines have been shut down. People are too close for safety on planes and planes should not be transporting potentially infected passengers anywhere - domestically or internationally - with the exception of exceptional circumstances. Public transportation networks have been shutdown or are offering reduced service. Like planes, passengers are in too close proximity on trains and buses and there are too many touchable surfaces to guarantee safety. Taxis and ride hailing operators MUST shut down, unless their vehicles are equipped with certified safety shields. There is no excuse. Allowing these operators to continue to function as if it is business as usual is criminal. It is not unlike retail clerks. We are beginning to hear stories of retail clerks at pharmacies and grocery stores testing positive and, in at least one case in Italy, dying. Supermarket chains in the U.S. are in the process of erecting Plexigas shields at their cash registers to protect their clerks. Like post-911 airport security - these Plexigas shields are likely to become a permanent fixture at your local grocery store.
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Partitions actually serve many functions as evidenced by the Rolls Royce Phantom Partition Wall which includes an intercom and a pass-through for notes (but big enough for a weapon). Notes Project Manager Doug Claus: "The Phantom is the vehicle of choice for ‘social distancing’ in the ultimate luxury sector.” Claus says the electrochromatic screen on the Phantom Partition Wall changes from transparent to opaque at the touch of a button. There is an integrated intercom system which mutes the front compartment audio system as the owner’s call is patched through immediately, but requires the owner to accept a call from the front compartment, so as not to be unduly interrupted. The partitions implemented by taxis and ride hailing operators may not rise to the level of luxury and performance of the Phantom Partition Wall, but the masses requiring transportation beyond the luxury sector are entitled to the same level of safety and security. Uber, Lyft, Gett, Grab, Via, Yandex, DiDi and the rest of the ride hailing operators - and yellow and black and green and blue taxis - must have partitions to operate safely in the time of COVID-19. To proceed otherwise is to court disaster in the name of business as usual. For further insight into mobility strategies, regulations, decision making, please register for and join a Strategy Analytics Webinar, for this Thursday, March 26th: Swiss MaaS: The Evolution of Mobility in Switzerland, Europe and the World https://www.strategyanalytics.com/strategy-analytics/webinars-and-events/webinars/strategy-analytics-webinar/swiss-maas-the-status-of-mobility-in-switzerland-europe-and-the-world
[post_title] => Shut Uber Down Now [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => shut-uber-down-now [to_ping] => [pinged] => [post_modified] => 2020-03-29 10:46:33 [post_modified_gmt] => 2020-03-29 17:46:33 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=284246 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 1 [filter] => raw ) [3] => WP_Post Object ( [ID] => 284250 [post_author] => 19 [post_date] => 2020-03-29 10:00:32 [post_date_gmt] => 2020-03-29 17:00:32 [post_content] => Tesla’s 2019 Turning Point
2019 will be remembered as the year the automotive industry decided to right-size its autonomous vehicle ambitions. Multiple auto makers tempered their vaunted claims for delivering fully autonomous cars within a few years and Daimler Chairman of the Board Ola Kälenius declared in December that the pursuit of autonomous “robotaxis” was proving more challenging than originally thought, so the company was shifting its focus toward autonomous trucks. Kallenius added to his AV skepticism earlier this month when he said Daimler would further prioritize electric vehicle development over autonomous cars in view of urgent European and global regulatory requirements. But autonomous vehicle thought leadership at Daimler originated with Christoph von Hugo. Speaking at the Paris Auto Show in 2016, von Hugo, head of active safety for Daimler, sought to put AV ethical concerns to rest when he averred that autonomous driving systems would, first and foremost, opt to protect passengers and drivers over bystanders. In this context it is interesting to note that 2019 actually ended with two fatal crashes of cars built by Tesla Motors – one outside Terre Haute, Indiana, and one in Gardena, California - both of which may have been using Tesla's semi-autonomous Autopilot function. There were several unique aspects to the Gardena crash that are likely to change the conversation around the semi-automated driving enabled by Autopilot. Among the unique aspects of the Gardena crash were the following:
  • Tesla CEO Elon Musk chose not to comment after the crash.
  • The two fatalities in Gardena were passengers in another vehicle which was hit by the Tesla vehicle.
  • This was the first occasion of two fatal Tesla crashes in a single day.
After previous crashes of Teslas that took the lives of the Tesla drivers, Musk had been quick to implicate the drivers' misuse or abuse of the Autopilot function (taking advantage of Tesla's remote access to vehicle operational data), after confirming it was in use. Musk has said nothing in regard to either the Gardena crash or the crash in Indiana. The Gardena crash, which occurred at a traffic light located at the junction of Route 91 where it becomes Artesia Boulevard, caused injuries to the driver of the Tesla and a passenger in the car, while killing the driver and passenger of a Honda Civic. According to reports from the crash scene, the Tesla ran a red light and crashed into the Honda. In the Indiana crash, the Tesla crashed into a parked firetruck. The driver survived. The passenger in the Tesla was killed. The National Transportation Safety Board (NTSB) and the National Highway Traffic Safety Administration (NHTSA) both indicated publicly at the time of the two crashes that they would be investigating. The deafening silence from Musk is telling. It tells us that Musk has learned to keep his mouth and his Twitter account quiet when NTSB and NHTSA are investigating fatal crashes. There are multiple potential causal scenarios in both fatal crashes. It is quite possible that Autopilot was not engaged in either crash, in which case the likely culprit will be driver inattention or distraction. Or it may be that Autopilot was engaged, in which case, in Indiana, the system failed to identify a fire engine parked in a travel lane with its flashing lights on, and, in Gardena, the Tesla vehicle failed to recognize the transition from Route 91 to Artesia Boulevard – a transition market by an intersection with a traffic light. The impact of the crash in Gardena is likely to be felt sometime later in 2020. If the existing pattern holds, the investigations of both the NTSB and NHTSA are likely to require nearly a year to complete, so there is a long, delayed fuse to the detonation of their findings which are likely to alter Tesla’s operations. What has changed this time around for Tesla is that a Tesla vehicle is responsible for the deaths of other road users. Where, in the past, Tesla vehicles operating on Autopilot had failed Daimler’s key rule of autonomous technology: to first protect the driver. In this case, in Gardena, the Tesla did indeed protect the driver while taking the lives of occupants of another vehicle. In effect, the Tesla vehicle appears to have adhered to the Daimler AV principle with disastrous results. Researchers have sometimes compared the behavior and driving characteristics of distracted drivers to the behavior of drunk drivers. This comparison is notable as a drunk might argue that his behavior is benign at least up to and until he or she decides to drive a car. Tesla Motors’ Autopilot, too, could be considered to be benign, that is up to and until it is asked to perform in inappropriate circumstances and without the supervision of a human driver. In the Gardena case, the Tesla vehicle, if it is determined to have been operating in Autopilot, appears to have failed to recognize:
  • Thee transition from highway to surface streets;
  • The existence of a traffic light;
  • The fact that the light was actually red;
  • And the presence in the intersection of another vehicle.
The two fatalities in the Honda completely change the conversation regarding Autopilot and will give rise to the question of Federal intervention. After the fatal crash of a Tesla in Mountain View, California, two years ago the NTSB’s investigation, only recently concluded, delivered a set of recommendations to NHTSA, SAE International, the Occupational Safety and Health Administration, Manufacturers of Portable Electronic Devices (Apple, Google, HTC, Lenovo, LG, Motorola, Nokia, Samsung, and Sony), Apple, Tesla Motors, the Consumer Technology Association, and the California State Transportation Authority. Those recommendations in their entirety can be found here: https://www.ntsb.gov/news/events/Documents/2020-HWY18FH011-BMG-abstract.pdf It appears that the NTSB either lacks the authority or has not chosen to assert the authority to interfere in Tesla’s operations. It has issued recommendations and, in the latest report, reiterated some recommendations which Tesla has thus far ignored. The fundamentally unique nature of the latest crash has raised the stakes for the NHTSA, the NTSB, and for Tesla Motors, which now has more than 700,000 of its vehicles on the road equipped with Autopilot, according to some estimates. Musk has long asserted, as he did during the latest NTSB investigation, that Autopilot remains a beta product – still in development and subject to ongoing refinement. Without an immediate and affirmative effort to respond to the NTSB’s recommendations, Tesla can no longer expect the kind of NTSB wrist slap it received earlier this year following the Mountain View investigation. NTSB, NHTSA, and the public cannot countenance routine fatal crashes from Teslas - especially now that we know that it isn't just Tesla drivers that are at risk.
[post_title] => Tesla’s 2019 Turning Point [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => teslas-2019-turning-point [to_ping] => [pinged] => [post_modified] => 2020-03-29 21:14:52 [post_modified_gmt] => 2020-03-30 04:14:52 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=284250 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [4] => WP_Post Object ( [ID] => 283986 [post_author] => 11830 [post_date] => 2020-03-27 06:00:45 [post_date_gmt] => 2020-03-27 13:00:45 [post_content] => It started slowly at first.  Then it began picking up steam. I’m referring to consolidation in the semiconductor sector. I had a front-row seat for what consolidation did to the ASIC part of semiconductor and that is the topic of this discussion. I was the VP of marketing at eSilicon, the company that invented the fabless ASIC model. I was there for the first five years and the last six years. In between, I was chasing other dreams – that’s a story for another day. The evolution of the ASIC business is actually a long story. Again, I’ll save that for another day. The “ASIC void” situation we face is easier to describe. I’ll focus on two forces of nature in this market – LSI Corporation, AKA LSI Logic (LSI) and IBM Microelectronics (IBM). Of course, there are many more excellent companies that have served this market, but the fates of LSI and IBM will illustrate my point. Beyond eSilicon, I’ve worked in the ASIC sector for most of my career and I can tell you that both LSI and IBM were formidable competitors. Both had a substantial focus on the custom chip business. Both had an extensive library of differentiating semiconductor IP, access to and deep expertise with relevant manufacturing technologies, a bullet-proof design methodology and all the resources needed to get a chip through prototype and into production, repeatably and reliably. Both companies also had a flair for working closely with the customer, thanks to their extreme focus on the custom chip business. In short, they were both very, very hard to beat. Around 2013, there was a disruption in The Force and things started to change. First, Avago bought LSI. Then there were more acquisitions, with LSI ultimately being deep inside a large, substantial and diversified company called Broadcom. Singular focus on ASICs is hard to accomplish in such an environment. Two years later, GLOBALFOUNDRIES (GF) acquired IBM Microelectronics. Did that make GF a foundry, an ASIC vendor or both? There was debate on that topic. Then, three years later GF spun out its custom silicon business (the IBM part) as Avera Semiconductor. Then, last year Marvell acquired Avera. All this churn created a void in the ASIC market. At eSilicon, we heard the same thing from many customers – they were looking for a dedicated, focused ASIC company that had the IP, the right technology experience, a strong production track record and a willingness to be a partner to build game-changing, critically needed custom chips. Thanks to its deep expertise in 2.5D packaging and complex digital designs, eSilicon became a tier-1 ASIC supplier for the data center, high-performance networking, AI and 5G markets to help fill that void. A few months ago, eSilicon was acquired by Inphi with certain assets sold to Synopsys. Late last year Dan Nenni posted a discussion on this topic, Where has the ASIC Business Gone? In that post, Dan referenced DELTA Microelectronics, a company with a specific focus on ASIC. Then last month, Presto Engineering acquired DELTA.  I’ll discuss the relevance of these events in my next post on this topic. For now, I would like to catalog what it takes to be a contender to fill an ASIC void:
  • Design and manufacturing expertise in a market that requires custom chips
  • Differentiating IP and the skills to integrate it into a customer design
  • A solid design methodology and the discipline to enforce it
  • A willingness to partner with the customer – a shared vision for success is key
  • A solid track record of successful bring-up of designs in target systems
I invite you to ponder this list. Are these the right attributes to be a focused ASIC supplier and thus address potential gaps in this market? [post_title] => Filling the ASIC Void - Part 1 [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => filling-the-asic-void-part-1 [to_ping] => [pinged] => [post_modified] => 2020-03-27 07:27:01 [post_modified_gmt] => 2020-03-27 14:27:01 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=283986 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 1 [filter] => raw ) [5] => WP_Post Object ( [ID] => 284168 [post_author] => 14 [post_date] => 2020-03-26 10:00:24 [post_date_gmt] => 2020-03-26 17:00:24 [post_content] => Covid 19 Semiconductors SemiWiki 2 It is a demand driven downturn - harder to predict It may not be "business as usual" after this virus What systemic changes could the industry face? Trying to figure out another cycle-driven by inorganic catalyst Investors and industry participants in the semiconductor industry who are used to normal cyclical behavior of over and under supply driven by factors emanating from the technology industry itself now have to try to figure out the impact of an external damper unlike any we have previously seen. We are truly in uncharted waters as the tech industry in general has continued to grow, perhaps at varying rates, but we haven't seen a broad based, global downturn such as we may be in line for. Many would point to the economic crisis of 2008/2009 which was certainly negative but does not have the same "off a cliff with no skid marks" that the current global crisis has for its sudden sharp drop. We would also point out that the semiconductor industry is famous for self inflicted cycles based on over supply from building way too much capacity. In fact we would argue that most chip cycles are self inflicted and most are supply side initiated. The COVID-19 cycle is demand based as we haven't had a sudden change in global chip capacity, as fabs have kept running but we can expect a demand drop that has yet to fully manifest itself. Technology is always the first to get whacked When the economy goes south, technology buys are the first to suffer. Consumers continue to buy food, shelter, fuel and guns & ammo but don't buy the next gen Iphone or bigger flat screen. 5G can wait while I put food on the table. Given that smart phones are nothing more than containers of silicon, its clear that the chip industry will get it in the neck. There are also a lot of other things in addition to the virus such as the oil market issues and the election which has all but been forgotten about. The effects on the technology market will persist long after the virus has been arrested and controlled. There was a baseline assumption at one time that all the economic damage associated with COVID-19 would certainly be contained within the calendar year such that any business delayed by the virus out of H1 would just make H2 of 2020 that much stronger and it would all be a "wash" on an annualized basis. The current trajectory as to the the length and depth of the "COVID-19 Chip Cycle" is unknown as to whether it is "V", "U" or "L" shaped. Right now it feels at least like a "U" if not an extended "U" shape (a canoe...). The chip industry was barely a quarter out of a "U" shaped memory driven down cycle, having been pulled out by technology spending on the foundry/logic side when we were ambushed by COVID-19. Two types of spending cycles; Technology & Capacity There are two types of spending cycles in the chip industry, technology driven spending versus capacity driven spending. Capacity driven spending is the bigger part and technology spend is more consistent. The industry has been on a technology driven spending recovery that was just about to turn on a capacity driven push. While we think that technology driven spending to sustain Moore's Law and 5NM/3NM will continue, we think that capacity spending will likely slow again, especially on the memory side as a drop in demand will get us back into an oversupply condition that we were just starting to emerge from. The supply/demand balance in the chip industry remains a somewhat delicate balancing act and the COVID-19 elephant just jumped on one side. One could argue that foundry/logic which has been the driver of the current recovery could falter as 5G, which is a big demand driver, is a "nice to have" not a "gotta have" as we could see 5G phone demand slow before the Iphone 12 ever launches. On the plus side, work from home and remote learning for schools is clearly stressing demand for server capacity and overall cloud services which should bode well for Intel and AMD and associated chip companies China Chip Equipment embargo likely off the table for now At one point, not too long ago, it felt like we were only days away from imposing severe restrictions and licenses on the export of technology that could help China with 5G, such as semiconductor equipment. We think the likelihood of that happening any time soon is just about zero as the US can't do anything to upset China as China supplies 90% of our pharmaceuticals, the majority of our PPE (personal protective equipment) like masks, and probably a lot of ventilators. Politicians have bigger fish to fry with fighting over a trillion dollars of a rescue package and pointing fingers at one another. So at least COVID-19 has crowded out other things we had to worry about in the chip industry. Probably no one cares if the Chinese dominate 5G as there won't be a lot of demand to dominate. There may be permanent systemic changes There is a lot of complaining about corporate "bailouts", stock buy backs, executive pay etc; associated with any financial rescue package. While much of this may be focused on airlines and other more directly impacted industries, even if the chip industry never gets a dime of bailout money there will likely be increased scrutiny on corporate behavior in general and there could even be some legislation associated with it. Buy backs which have become very big in the chip industry during good times may become less popular. We would not be surprised to see an increased focus on semiconductor manufacturing moving to Asia as people have figured out we don't even make our own pharmaceuticals any more. Is an out sourced global supply chain a bad thing? The technology industry has prided itself on how far and wide the supply chain for a technology can be. An Iphone is perhaps a poster child for supply chain logistics. The problem is that broad and wide supply chains have been exposed as our soft underbelly, during COVID-19, that make us more susceptible to interruptions, even in some far away place, that can completely shut us down. These supply chains work like dominoes that can cause a cascading effect to bring things to a halt. Truly multinational companies that rely on the free movement of people and goods across borders with no friction might think twice about how they will deal with another global crisis as there is a high likelihood we will experience another one....not a question of if but rather when. That we haven't had a global disruption like COVID-19 before is probably just pure luck. Boards of large companies will start to ask and demand for plans to deal with global disruption just as they have local contingency plans today to deal with local disasters. Will the world get less interconnected? Maybe moving back to a more vertically integrated, local model is safer albeit a little more expensive. There is likely some political will for more isolationist economic behavior after COVID-19 is over. The semiconductor industry in the US is a shell of its former self as most production and much technology has been off shored with the primary driver being economic savings which mean less when you can't produce anything. Balance sheet safety We would point out that the semiconductor industry does seem to be relatively flush with cash as compared to cycles past. However there are some companies in the space that have a significant amount of debt (in some cases more than their cash) on their balance sheet. The US has over 7 Trillion dollars in corporate debt, now more than ever, and about a third of our GDP. In previous cycles in the chip industry we have seen some companies go under due to debt load. The popular model to lever up balance sheets with debt could potentially reverse itself as there are a long list of companies that will have their hand out for the government bailouts. If we slow down buy backs, getting out of debt should be easy for most but there still are some that are deeply in debt, just a little less so in the semiconductor industry. There are a handful of companies that could see COVID-19 related weakness push them closer to debt problems M&A rebound? Could we see the government loosen up its dislike of corporate mergers. If companies make the argument that getting together makes them stronger and more resistant to global issues then we could see a few more larger mergers happening under the right circumstances. There is probably not a lot left in the semiconductor industry but there are a few deals that didn't happen that could be revisited....after all , valuations are a lot more attractive now, especially for those companies that have dry powder in the form of cash. Stock valuations are attractive We are seeing stock valuations that are now looking attractive on a P/E basis much as the stocks were getting too expensive just a couple of months ago. We are seeing multiple contraction rather than expansion as some stocks are discounting an unrealistic level of contraction much as they were previously discounting too bright a future. Much of the sentiment will be determined on Q1 conference calls which are coming up. If we were management, we would probably take a very conservative view as going out on a limb will not likely be rewarded. Investors also want to see a company reset expectations in one swoop rather than a death by a thousand cuts over the next few quarters Investors will want some sort of comfort that we are at or near a COVID-19 bottom even though that may not be the real case... just lie to me and make me feel better..... [post_title] => COVID-19 Chip Cycle - How deep, long and what shape? [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => covid19-chip-cycle-how-deep-long-and-what-shape [to_ping] => [pinged] => [post_modified] => 2020-03-26 10:43:51 [post_modified_gmt] => 2020-03-26 17:43:51 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=284168 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 4 [filter] => raw ) [6] => WP_Post Object ( [ID] => 284060 [post_author] => 16 [post_date] => 2020-03-26 06:00:55 [post_date_gmt] => 2020-03-26 13:00:55 [post_content] => It’s a matter of pride to me and many others from Atrenta days that the brand we built in SpyGlass has been so enduring. It seems that pretty much anyone who thinks of static RTL checking thinks SpyGlass. Even after Synopsys acquired Atrenta, they kept the name as-is, I’m sure because the brand recognition was so valuable. VC SpyGlass Lint Even good things must evolve. Synopsys verification has a strong “VC” brand and it was natural that SpyGlass should fold in under this, still with a strong connection to its founding identity. So now we have VC SpyGlass, in line with VC LP and VC Formal. This isn’t just a rebranding. Synopsys have put a lot of work into this next generation SpyGlass, including 3X performance increase in half the memory, always a plus in any context and especially valuable when you want to screen full-chip RTL. But there are a number of other significant advantages which resonate all too clearly from my time at Atrenta. One is a 10X reduction noise. Anyone who’s ever used a static verification tool knows that noise can be a huge pain. Simulation will only catch bugs exercised and detected by the tests you run. Static verification will catch all bugs within the range of checks it performs. But the devil’s bargain you make for this completeness is that it will also catch many things that aren’t problems or are just different manifestations of a problem it already reported. You may have to wade through a whole bunch of spurious errors to find the one or two real problems you need to fix. Reducing this noise level is a very big deal. I remember the Atrenta team working on methods to compress errors by root cause as one approach to noise reduction. Other techniques used formal methods to weed out structurally apparent errors which are not functionally possible. It sounds like Synopsys has extended these methods further. Another key advantage I cannot over-emphasize is completing compatibility with the Synopsys implementation tools. This starts with synthesis compatibility. Under the hood, SpyGlass does a quick synthesis so it can run a lot of checks on an elaborated graph. How effective (or noisy) that is depends very much on how well it mirrors the ultimate real implementation. At a superficial level that’s not such a big deal. You use one of the standard open-source synthesis platforms and you’re good, right? Wrong. There are a number of places where using a different synthesis solution is likely to generate false errors or miss real errors: datapath and mux inferencing are just two examples. When a tool gets this stuff wrong, pretty soon it’s thrown out. We always wrestled with trying to match DC behavior as closely as we could, but you can never do as well as you can when using the real thing. No longer a problem in VC SpyGlass. Another related problem was matching behavior in constraints. There’s a lot of useful information in those constraints to flag clocks, resets and so on. Especially useful in CDC and reset analysis and can also be useful in other aspects of static analysis. When is a clock really a clock? You can try to infer this bottom-up by just looking at the RTL, tracing back from register clocks. But that’s not foolproof. Constraints fix the ambiguity, but you need to interpret them the same way the implementation tools do. Not so bad in vanilla SDC but potentially much more difficult in Tcl. Again, no longer a problem in VC SpyGlass. Finally, VC SpyGlass has unified debug with Verdi. Let’s face it, Verdi is the de facto standard for functional debug in the industry. Everybody uses it. We had an interface to Verdi when I was at Atrenta. But there are interfaces and then there are native integrations. Native integrations are invariably faster and more capable. You can switch back and forth between VC tools, retaining a consistent VC interface throughout. I’m happy to see VC SpyGlass fully integrated the VC family. It confirms the value we created and a continuing bright future for the technology. You can learn more about VC SpyGlass HERE. [post_title] => SpyGlass Gets its VC [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => spyglass-gets-its-vc [to_ping] => [pinged] => [post_modified] => 2020-03-23 09:35:24 [post_modified_gmt] => 2020-03-23 16:35:24 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=284060 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [7] => WP_Post Object ( [ID] => 283890 [post_author] => 11830 [post_date] => 2020-03-25 10:00:01 [post_date_gmt] => 2020-03-25 17:00:01 [post_content] => I got a chance to chat with Richard Solomon at Synopsys recently about a very real threat for all of us and what Synopsys is doing about it. No, the topic isn’t the Coronavirus, it’s one that has been around a lot longer and will continue to be a very real threat – data and interconnect security. First, a bit about Richard. He is the technical marketing manager for DesignWare PCI Express (PCIe) Controller IP at Synopsys. He previously worked at NCR Microelectronics, Symbios Logic and over two decades at LSI Logic, including the position of architect for host interfaces there. Richard has seen a lot of complex design challenges in his career, and we spent some time discussing data/interconnect security in the context of his experience and the plans Synopsys is developing. Richard began with a big picture view of the problems associated with a lack of security.  Looking through a “cost” lens, here are some facts:
  • 2013 – Target stores hacked; breach may have cost over $250 million
  • 2016 – Yahoo hacked, dropped sale price to Verizon by $350 million
  • 2017 – Equifax hacked, costs approaching $1.4 billion to date
  • Consumer confidence loss even more expensive
A lot of discussion around the issues above has centered on software. Things like encryption and establishing trusted sources. To make all this efficient and to add additional layers of protection requires a look at hardware.  This is where Richard spent the bulk of his time during our discussion. At a hardware level, the “attack vectors” become quite diversified. Consider the following:
  • Supply chain: substituting a compromised component before end delivery – e.g. NIC card, BMC controller, SSD, potentially even CPUs, etc.
  • In-system component compromise: reprogramming (“hacking”) the firmware of a “good” device for nefarious purposes
  • Physical access attack: using a logic analyzer, oscilloscope, or purpose-built “monitoring” hardware to snoop system operation
    • Edge devices are often in exposed areas subject to easy physical access
Do you have a headache yet? I did. All this can be quite subtle as well. Richard provided a good illustration: How many times have you plugged your phone into a USB port at an airport for a re-charge? Are you sure it was only charging your phone?  We all know a USB port can do a lot more than charge your phone. Next, Richard outlined the work going on at Synopsys to deal with these, and other security challenges. An effective approach requires a wide-ranging look at hardware security, from the SoC and its IP through the entire ecosystem. To begin with, one must consider servers, routers, individual PCs, tablets and smartphones. Getting into the details of each architecture is required as well. That opens up components such as CPUs, I/O controllers (NVMe, SAS, Ethernet, etc.) and even power and cooling units. At a lower level, IO interconnects (e.g. PCIe, CXL, etc.) need to adopt security features to provide a solid foundation for everything else. The bulk of our discussion was on security in I/O interconnects. How does one secure I/O interconnects reliably? There are a lot of parts to the answer. Here’s a short version of the list:
  • Authentication
    • Standard bodies are working on specs that leverage certificate concepts from the software world
    • Components provisioned at manufacturing time with certificate chain & key pairs that can be matched against their pre-provisioned expectations
  • Measurement
    • Run-time component checking of firmware, configuration, FPGA bit files, chip straps, etc.
    • Components send signed measurement data to host for comparison with allowed values
  • Integrity (data encryption)
    • Ensuring data on the wire is secure from observation *and* tampering
Getting all this done requires a lot of work from standards bodies and the associated implementation of those standards in hardware. Richard explained that Synopsys is active in many of these efforts and will be ready to support those standards in its IP and tools when they are announced. PCIe is the dominant I/O interconnect and this is likely where a lot of early work will be done across areas such as authentication, measurement and integrity. Compute Express Link (CXL) is a new high-speed CPU interconnect standard. Richard pointed out that it’s based on PCIe and will likely build on PCIe security additions. It turns out there are a lot of interlocking pieces to affect real improvements in network and data security; low-level key exchanges, measurement algorithms and packet definitions that support encryption and integrity information to name a few. The last one has the added complexity of handling replay mechanisms for link error recovery in a way that doesn’t weaken cryptographic strength. I have a new appreciation for the complexity of hardware-level security after my discussion with Richard. It’s comforting to know that Synopsys is active on many fronts and will be prepared to support early adopters. Expect to hear a lot more about these efforts over the coming months. Start thinking about how this impacts your future design work NOW and then talk to Synopsys. You can also learn more about the Synopsys DesignWare IP solutions for PCI Express here. You’ll find lots of information and resources there, including several good videos. [post_title] => Security in I/O Interconnects [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => security-in-i-o-interconnects [to_ping] => [pinged] => [post_modified] => 2020-03-25 10:17:01 [post_modified_gmt] => 2020-03-25 17:17:01 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=283890 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [8] => WP_Post Object ( [ID] => 284017 [post_author] => 19385 [post_date] => 2020-03-25 06:00:29 [post_date_gmt] => 2020-03-25 13:00:29 [post_content] => EUV lithography is widely perceived to be the obvious choice to replace DUV lithography due to the shorter wavelength(s) used. However, there's a devil in the details, or a catch if you will. Electrons have the last word The resist exposure is completed by the release of electrons following the absorption of the EUV photon. Photoelectrons initially released by EUV absorption are expected to be ~ 80 eV, and release energy by further ionization, producing secondary electrons [1]. The photoelectrons and secondary electrons can lose energy by plasmon generation as well [2]. Electrons with energies as low as 1.2 eV can still expose resists [3]. Dissociative electron attachment (DEA) can also occur at very low energies [4]. Consequently, the image is affected by the "blur" resulting from the spread of these electrons. An example is shown below in Figure 1. Even a few nm blur or a few nm blur difference can degrade the sub-20 nm image's sensitivity to dose variations.
Low Energy Electrons Set the Limits for EUV Lithography
Figure 1. Secondary electron blur is modeled as a Gaussian function involved with the original non-blurred image, fitted with a Gaussian as well [5]. How far can the electrons travel? A simple Monte Carlo simulation demonstrates that a fairly wide spread of electron paths is possible even with a low mean free path. In Figure 2, four simulation runs are shown, each representing 30 collisions of an electron, where the electron travels 1 nm in a random direction between collisions (including mostly elastic (no energy lost or gained) and inelastic low energy (<0.1 eV) transfers with phonons [6]), is shown to lead in some cases to travel distances approaching 10 nm. The "r" result is the net distance (regardless of direction) from the original starting point, treated here as (0, 0, 0) , i.e., r=sqrt(x^2+y^2+z^2). The distribution of distances is shown in Figure 3. The mean final travel distance was 5.1 nm with a standard deviation of 2.25 nm, while the mean max distance was 6.5 nm with a standard deviation of 1.5 nm. Even with a limited sampling (N=20), the distribution of travel distances covers a fairly wide range of nanometers.
Simulations of electrons going through 30 collisions
Figure 2. Simulations of electrons going through 30 collisions, mostly elastic, the remaining assumed to be low energy transfers to phonons [6].
Distribution of final and maximum travel distances after 20 simulation runs
Figure 3. Distribution of final and maximum travel distances after 20 simulation runs using the conditions of Figure 2. Increasing or decreasing the travel distance between collisions will naturally increase or decrease the net travel distance as well. The inter-collision distance of 1 nm is comparable to the step size used in other recent related work [7, 8]. Measurements of resist loss from low energy electrons are also in excess of 1 nm [3, 4]. Of course, more collisions accumulated will lead to a wider range of travel distances as well. Another possibility to consider is net positive charge at the starting position, which might slow down further migration by Coulomb force attraction. Recent work, however, suggests this could be negligible [8]. Takeaway Thoughts For a fully rigorous and complete EUV resist model, in addition to the aerial (photon-only) image input, we need to have the accurate representation of low energy electron blur. These simulation runs hint that it is somewhat oversimplified to have a fixed electron blur value. It is more prudent to consider a range of blur values. This is better for giving the process variation (PV) bands. Appendix (Technical Note): Simulations are run on an Excel sheet. Starting point (0, 0, 0). Random spherical coordinate system angle theta (0 to 180 deg) and phi (0 to 360 deg) selected using RANDBETWEEN function, while jump step is fixed (1 nm for this article). Jump = (jump step * sin(theta) * cos(phi), jump step * sin(theta) * sin(phi), jump step * cos(theta)). This is iterated 30 times for the runs in this article. References [1] J. Torok et al., "Secondary Electrons in EUV Lithography," J. Photopolym. Sci. and Tech. 26, 625 (2013). [2] G. Denbeaux et al., "The role of secondary electrons in EUV resist," EUVL Workshop 2014. [3] I. Bespalov et al., "Key Role of Very Low Energy Electrons in Tin-Based Molecular Resists for Extreme Ultraviolet Nanolithography," ACS Appl. Mater. Interfaces 12, 9881 (2020). [4] B. Sun, "Low-energy electron-induced chemistry of PMMA," Master of Science thesis, July 2014. [5] https://www.linkedin.com/pulse/from-shot-noise-stochastic-defects-dose-dependent-gaussian-chen/ [6] B. Ziaja, R. A. London, and J. Hajdu, "Ionization by Impact Electrons in Solids: Electron Mean Free Path Fitted Over a Wide Energy Range," J. Appl. Phys. 99, 033514 (2006). [7] H. Fukuda, "Localized and cascading secondary electron generation as causes of stochastic defects in extreme ultraviolet projection lithography," J. Micro/Nanolith. MEMS MOEMS 18(1), 013503 (2019). [8] L. Wiseheart et al., "Energy deposition and charging in EUV lithography: Monte Carlo studies," Proc. SPIE 9776, 97762O (2016). [post_title] => Low Energy Electrons Set the Limits for EUV Lithography [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => low-energy-electrons-set-the-limits-for-euv-lithography [to_ping] => [pinged] => [post_modified] => 2020-03-24 09:33:40 [post_modified_gmt] => 2020-03-24 16:33:40 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=284017 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [9] => WP_Post Object ( [ID] => 283798 [post_author] => 11830 [post_date] => 2020-03-24 10:00:18 [post_date_gmt] => 2020-03-24 17:00:18 [post_content] => I had the opportunity to preview an upcoming SemiWiki webinar on IR drop and power integrity. These topics, all by themselves, have real stopping power. Almost everyone I speak with has a story to tell about these issues in a recent chip design project. When you combine hot topics like this with a presentation that details the collaboration between Synopsys and ANSYS to solve them, you have a real winner in my view. The details of how industry-leading extraction and analysis tools from ANSYS are tied to industry-leading implementation tools from Synopsys are clearly worth a look. You can view this webinar on Tuesday, March 31, 2020 at 10AM Pacific time. Mark that on your calendar. The registration link is included, above.  I’ll repeat it later. Let’s first review who’s presenting at this webinar and what they’ll cover. The first speaker is Rahul Deokar, director of marketing and business development for the Synopsys Fusion Design Platform, with focus on signoff products, including RedHawk Analysis Fusion. Rahul begins his presentation with a review of the technology trends and associated challenges and dangers presented by things like dynamic voltage drop and power integrity. He then presents Redhawk-SC and discusses its capabilities to effectively deal with the problems under discussion. Rahul then describes RedHawk Analysis Fusion, a two-year project to combine the analysis capabilities of ANSYS RedHawk with the implementation capabilities of Synopsys ICC II/Fusion Compiler. Signoff quality analysis with a native integration to an industry-leading implementation flow at the block, subsystem and full-chip levels. This really got my attention. Getting into more details, Rahul explains the benefits of block-level signoff accuracy, robust place & route optimization and the ability to access the latest distributed processing capabilities of RedHawk-SC. Rahul then summarizes the added features in the new release of RedHawk Fusion. The list is quite extensive and impressive. He also covers the power integrity design flow that is enabled by RedHawk Fusion. To give you a feeling for the what’s included, I’ll just mention one of the many capabilities covered: Dynamic Power Shaping: optimizes peak current and reduces dynamic voltage drop via clock scheduling. All the capabilities presented are illustrated with real design examples, including case studies of a 7nm design. To whet your appetite further, machine learning is also employed in the release. Marc Swinnen then presents the details of ANSYS RedHawk-SC, their next-generation product for 7nm and below. Marc is the director of product marketing at ANSYS. The next-generation architecture for RedHawk was developed about four years ago and it’s called SeaScape – RedHawk-SC is based on it. Marc explains that the motivation for this new platform was two-fold:
  • Address the capacity requirements resulting from the dramatic increase in analysis at advanced nodes
  • Extend IR-drop analysis to handle the multi-physics considerations of new effects such as electromigration, inductance and thermal gradients
Marc explains that SeaScape uses the same approach for data organization that is used by big data and artificial intelligence tools. Marc goes on to detail the distributed architecture of SeaScape. The discussion is quite impressive and improvements in speed, capacity and efficiency are substantial. Marc also discusses chip-package co-analysis, a critical item for advanced 2.5 and 3D packaging. Rahul then presents the results of actual customer designs using RedHawk Fusion. Several application areas, all at advanced nodes and from different parts of the world are covered. The webinar concludes with a Q&A session that shines more light on the types of designs this flow can be used on. The depth of detail presented during this webinar, along with the unique collaboration of two major design tool suppliers make this webinar a must-see. You can register for the webinar here. Don’t miss this one. [post_title] => Prevent and Eliminate IR Drop and Power Integrity Issues Using RedHawk Analysis Fusion [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => prevent-and-eliminate-ir-drop-and-power-integrity-issues-using-redhawk-analysis-fusion [to_ping] => [pinged] => [post_modified] => 2020-03-25 10:58:12 [post_modified_gmt] => 2020-03-25 17:58:12 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=283798 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) ) [post_count] => 10 [current_post] => -1 [in_the_loop] => [post] => WP_Post Object ( [ID] => 284107 [post_author] => 3 [post_date] => 2020-03-30 06:00:51 [post_date_gmt] => 2020-03-30 13:00:51 [post_content] => Having the right tool for the job at hand is always a joy, and when your IC project involves RTL code, gates, transistors and even parasitic interconnect, then you need some EDA tool help for debugging and finding out why your design behaves the way it is. An FAE named Sujit Roy did a conference call with me last week to show what StarVision Pro can do with mixed-signal design debug. Sujit works at EDA Direct, a company started in 1997 providing EDA tools from Mentor, Cliosoft and Concept Engineering, along with training and services. The StarVision Pro tool comes from Concept Engineering, an EDA company from Germany that has been in business for three decades now. I first heard about Concept Engineering about 18 years ago, because the EDA company that I worked at had a need to visualize SPICE netlists as schematics to better understand circuit simulation results from a Fast SPICE tool. It's been rewarding to see the growth of features as StarVision Pro has expanded its scope to cover so many input file formats: [caption id="attachment_284108" align="alignnone" width="960"]starvision pro StarVision Pro[/caption] The wow moment is when you read in a file format and then quickly visualize an automatic schematic, neatly laid out with inputs on the left and outputs on the right showing you all of the interconnect, cell instances and hierarchy. Circuit designers, logic designers and even DFT engineers can each benefit from quickly seeing how an SoC is assembled. For logic verification you can even see the logic state on each net in a design as a function of time. During a live demo on a laptop running Linux I saw Sujit read in a digital design, and this works even if your design is incomplete, missing IP or has syntax errors. Just look at how neat the auto-generated schematic appears: [caption id="attachment_284112" align="alignnone" width="850"]rtl schematic 850 min Auto-generated schematic[/caption] Useful debugging features include:
  • Click any net and dynamically expand a cone of logic
  • Cross-probe between schematic and RTL source code
  • Search for nets by filtering a name
  • Trace an internal net to an IO pin
In the screenshot above we've loaded in logic simulation results from a VCD file, then moved to a specific time point in the simulation run, and finally visualize the logic state on our nets. This kind of visual debug really speeds up the functional verification process to find and fix bugs. The next design file to be read in was from a parasitic extraction tool as a SPEF file, so we can quickly see the RC values that make up a net.  This screenshot shows how you can click on the schematic and cross-probe into the source file: [caption id="attachment_284117" align="alignnone" width="850"]parasitic cross probe min Parasitic Interconnect Cross-Probing[/caption] An engineer can then find which nets are the heaviest loaded, and Sujit ran a pre-built script that allowed him to filter and remove all capacitors below a threshold value. A SPICE netlist was loaded, and we viewed the MOS transistors, along with some parasitic capacitors: [caption id="attachment_284119" align="alignnone" width="850"]spice netlist min SPICE netlist[/caption] Next, we wanted to know what had changed in a SPICE netlist over time, so a DIFF script quickly highlight where the differences were located by showing that net n6 was modified: [caption id="attachment_284120" align="alignnone" width="850"]n6 min Net n6 was modified[/caption] StarVision Pro comes with some 100 scripts, so I got the idea that they had automated most debugging tasks for me, saving me time from having to write my own scripts. Of course, you can always just view the Tcl source code for the scripts, and create new derivatives and combinations to make your debugging happen faster. Videos On YouTube there's a channel for EDA Direct, and they've recorded over a dozen intro videos on specific StarVision Pro topics, and each video is brief at under 2 minutes of viewing time: https://www.youtube.com/watch?v=0uKj0GOb08c&t=24s Summary Designing, verifying and re-using mixed-signal chips and IP blocks can be a tedious and error-prone task, especially since most of the file formats are textual, which makes them difficult to understand as part of a larger or hierarchical design. Using an automatic visualization tool like StarVision Pro is sure to save you hours and days of engineering effort, because now you can see the structure of your IC design, along with simulation values in an intuitive schematic format. Circuit designers, logic designers, DFT engineers and verification engineers can all benefit by adding a tool like this to their methodology. Related Blogs [post_title] => Mixed-Signal Debugging Gets a Boost [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => mixed-signal-debugging-gets-a-boost [to_ping] => [pinged] => [post_modified] => 2020-03-26 10:56:02 [post_modified_gmt] => 2020-03-26 17:56:02 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=284107 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [comment_count] => 0 [current_comment] => -1 [found_posts] => 6914 [max_num_pages] => 692 [max_num_comment_pages] => 0 [is_single] => [is_preview] => [is_page] => [is_archive] => [is_date] => [is_year] => [is_month] => [is_day] => [is_time] => [is_author] => [is_category] => [is_tag] => [is_tax] => [is_search] => [is_feed] => [is_comment_feed] => [is_trackback] => [is_home] => 1 [is_privacy_policy] => [is_404] => [is_embed] => [is_paged] => [is_admin] => [is_attachment] => [is_singular] => [is_robots] => [is_posts_page] => [is_post_type_archive] => [query_vars_hash:WP_Query:private] => 443e714a5290f77b0df02e2f78f50560 [query_vars_changed:WP_Query:private] => [thumbnails_cached] => [stopwords:WP_Query:private] => [compat_fields:WP_Query:private] => Array ( [0] => query_vars_hash [1] => query_vars_changed ) [compat_methods:WP_Query:private] => Array ( [0] => init_query_flags [1] => parse_tax_query ) [tribe_is_event] => [tribe_is_multi_posttype] => [tribe_is_event_category] => [tribe_is_event_venue] => [tribe_is_event_organizer] => [tribe_is_event_query] => [tribe_is_past] => )

Mixed-Signal Debugging Gets a Boost

Mixed-Signal Debugging Gets a Boost
by Daniel Payne on 03-30-2020 at 6:00 am

starvision pro

Having the right tool for the job at hand is always a joy, and when your IC project involves RTL code, gates, transistors and even parasitic interconnect, then you need some EDA tool help for debugging and finding out why your design behaves the way it is. An FAE named Sujit Roy did a conference call with me last week to show what StarVisionRead More


Newsflash Chip Equip Blockade back on!

Newsflash Chip Equip Blockade back on!
by Robert Maire on 03-29-2020 at 2:00 pm

US China Blockade


Blocking chip sales to Huawei back on front burner
Covid19 & China Trade are equally bad
Long lived Uncertainty could “plague” industry sales going forward
Political Predictability worse than Disease Predictability

Reuters broke a story today that the proposed licensing of chip equipment to prevent “bad… Read More


Shut Uber Down Now

Shut Uber Down Now
by Roger C. Lanctot on 03-29-2020 at 12:00 pm

Shut Uber Down Now

By now it is pretty clear that everywhere outside of China and South Korea human beings are doing a lousy job of “social distancing,” locking down, and sheltering in place. This is unfortunate because experts agree that only a complete lockdown will stop COVID-19 from infecting millions, continuing to kill thousands,

Read More

Tesla’s 2019 Turning Point

Tesla’s 2019 Turning Point
by Roger C. Lanctot on 03-29-2020 at 10:00 am

Tesla’s 2019 Turning Point

2019 will be remembered as the year the automotive industry decided to right-size its autonomous vehicle ambitions. Multiple auto makers tempered their vaunted claims for delivering fully autonomous cars within a few years and Daimler Chairman of the Board Ola Kälenius declared in December that the pursuit of autonomous “robotaxi

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Filling the ASIC Void – Part 1

Filling the ASIC Void – Part 1
by Mike Gianfagna on 03-27-2020 at 6:00 am

shutterstock 235025512

It started slowly at first.  Then it began picking up steam. I’m referring to consolidation in the semiconductor sector. I had a front-row seat for what consolidation did to the ASIC part of semiconductor and that is the topic of this discussion. I was the VP of marketing at eSilicon, the company that invented the fabless ASIC model.… Read More


COVID-19 Chip Cycle – How deep, long and what shape?

COVID-19 Chip Cycle – How deep, long and what shape?
by Robert Maire on 03-26-2020 at 10:00 am

Covid 19 Semiconductors SemiWiki 1

It is a demand driven downturn – harder to predict
It may not be “business as usual” after this virus
What systemic changes could the industry face?

Trying to figure out another cycle-driven by inorganic catalyst

Investors and industry participants in the semiconductor industry who are used to normal cyclical… Read More


SpyGlass Gets its VC

SpyGlass Gets its VC
by Bernard Murphy on 03-26-2020 at 6:00 am

VC SpyGlass Lint

It’s a matter of pride to me and many others from Atrenta days that the brand we built in SpyGlass has been so enduring. It seems that pretty much anyone who thinks of static RTL checking thinks SpyGlass. Even after Synopsys acquired Atrenta, they kept the name as-is, I’m sure because the brand recognition was so valuable.

Even good… Read More


Security in I/O Interconnects

Security in I/O Interconnects
by Mike Gianfagna on 03-25-2020 at 10:00 am

shutterstock 1221815029

I got a chance to chat with Richard Solomon at Synopsys recently about a very real threat for all of us and what Synopsys is doing about it. No, the topic isn’t the Coronavirus, it’s one that has been around a lot longer and will continue to be a very real threat – data and interconnect security.

First, a bit about Richard. He is the technical… Read More


Low Energy Electrons Set the Limits for EUV Lithography

Low Energy Electrons Set the Limits for EUV Lithography
by Fred Chen on 03-25-2020 at 6:00 am

Low Energy Electrons Set the Limits for EUV Lithography

EUV lithography is widely perceived to be the obvious choice to replace DUV lithography due to the shorter wavelength(s) used. However, there’s a devil in the details, or a catch if you will.

Electrons have the last word
The resist exposure is completed by the release of electrons following the absorption of the EUV photon.… Read More


Prevent and Eliminate IR Drop and Power Integrity Issues Using RedHawk Analysis Fusion

Prevent and Eliminate IR Drop and Power Integrity Issues Using RedHawk Analysis Fusion
by Mike Gianfagna on 03-24-2020 at 10:00 am

Screen Shot 2020 03 14 at 5.36.37 PM

I had the opportunity to preview an upcoming SemiWiki webinar on IR drop and power integrity. These topics, all by themselves, have real stopping power. Almost everyone I speak with has a story to tell about these issues in a recent chip design project. When you combine hot topics like this with a presentation that details the collaboration… Read More