Sirish Munipalli is Co-Founder and CTO of Moores Lab AI, where he leads the development of agentic AI for chip design verification, including SpecAgent(tm), the company’s specification and modeling platform. He has spent about 15 years designing and verifying complex silicon: FPGA prototyping at Intel, post-silicon validation… Read More
DAC 2027 Opens Call for Contributions as AI Reshapes Chip DesignThe Design Automation Conference is the premier semiconductor…Read More
TSMC 2026 OIP Ecosystem Forum SummaryTSMC’s 2026 Open Innovation Platform Forum presented artificial…Read More
Data Center Energy Trends Force a Rethink of Chip Power DeliveryIntel Foundry published a two article series on…Read MoreWhat DARPA Taught Me About Building Trust into Silicon
By Sajeed Mohammad
The most memorable slide I ever saw in a chip design review didn’t show a floorplan. It showed a target. The Defense Advanced Research Projects Agency (DARPA) program manager running AISS, Automatic Implementation of Secure Silicon, the program that funded my majority of PhD research, had put a target… Read More
Delivering Silicon Systems Through AI Disruption, Part 1: Writing the Score
Score: the written music for an orchestra, with every section’s part laid out on the same page so they play together. In this article, it’s your designed workflows.
Is AI helping you hit your tape-out date, or putting it at risk? How would you know?
Every Director I talk to is being asked to use AI to deliver faster, or better,… Read More
A Migration Feasibility Study Can Turn an Uncertain Re-Design into a Measurable Engineering Project
Moving semiconductor IP to a new process technology is often treated as a redesign problem. For analog and mixed-signal designs, however, starting again from the schematic can overlook an asset: the engineering knowledge embedded in the existing physical layout.
Device sizing, matching, symmetry, routing, shielding, placement,… Read More
Interview with Eric Hong, VP of Engineering at Mixel, a Silvaco Company
Eric Hong is Vice President of Engineering at Mixel, a Silvaco company, where he leads the development of analog and mixed-signal IP, including high-speed PHY and SerDes solutions. Prior to Mixel, he held engineering leadership and technical roles at Nvidia, eSilicon, Samsung Electro-Mechanics, and Intel, leading the development… Read More
Teradyne Unveils Magnum E2 for the Next Wave of AI Memory
Teradyne has announced Magnum E2, a memory test system designed to address the increasingly demanding interfaces used in artificial intelligence and high performance computing. The platform targets advanced DRAM and flash technologies, including LPDDR6, DDR6, GDDR7, and NAND flash, while combining engineering and production… Read More
VSORA’s Sandra Rivera on the Inference Era: Demand Is Real, But Not Everyone Survives
Sandra Rivera, Chair of VSORA, joined Bloomberg’s The Close in July for an interview on the current state of AI. What follows is a summary of that conversation.
When a Silicon Valley veteran who once ran Intel’s Data Center and AI Group, and now chairs a French inference-chip challenger, sits down with a tech journalist from Bloomberg,… Read More
Intel’s Open Software Blueprint: Why Production AI Needs More Than GPUs
Intel’s strategic argument about enterprise AI is that the value of a model depends on the system that surrounds it. In an article by executives Bill Pearson and Anil Nanduri, the company positions open software as the connective tissue linking CPUs, GPUs, data, and business applications. The message is straightforward: accelerator… Read More
CTO Interview with Dr. Zakir Syed of ClockEdge
Dr. Zakir Syed is Co-founder and Chief Technology Officer of ClockEdge, where he has played a central role in developing specialized simulation technology for advanced semiconductor clock networks. He brings more than 30 years of experience in electronic design automation and semiconductor verification. He joined Simplex… Read More
Chips&Media targets AI memory bottlenecks with new compression IP
Chips&Media has announced a data compression technology aimed at one of the constraints in artificial intelligence hardware: moving data fast enough to keep processors busy. The South Korean semiconductor intellectual property supplier says its new Feature Map Compression IP marks an expansion beyond video applications… Read More



The silent killer of analog reliability: Why SPICE misses floating net