I spent a significant part of my career in the ASIC business. This segment of semiconductors has always been challenging, difficult and invigorating. There is something special about delivering a working custom chip that enables your customer to bring a world-changing product to market. It has always been a highly competitive… Read More
From Frontend to the Frontiers of Silicon with Moores Lab AIAlex Navarro is a Principal Software Engineer at…Read More
Synopsys Announces AgentEngineer Solutions and Autopilot Platform for Autonomous EngineeringSynopsys today announced its AgentEngineerTM solutions portfolio and…Read More
PDF Solutions CONNECT, the Premier Event for Semiconductor Analytics and AI, October 15 and 16 in San FranciscoOn October 15 and 16, 2026, in San…Read More
CEO Interview with Sunghyun Park of RebellionsDr. Sunghyun Park earned his B.S. from KAIST…Read MoreThe Pivotal Moments That Gave Rise to Silicon Valley
The little-known decisions and breakthroughs—and the remarkable role of Robert Noyce—that helped shape the modern semiconductor industry
by Sunil Mehta
When people tell the story of how Silicon Valley came into being, they usually begin with a familiar sequence of events.
The transistor was invented at Bell Labs. William Shockley… Read More
SiFive and AMD Bring ROCm to RISC-V Datacenter Servers—and Why It Matters
SiFive and AMD demonstrated an AI workload that brings together two open technologies: the RISC-V processor architecture and AMD’s ROCm GPU software platform. At the AI Infra Summit on September 15, 2026, the companies showed ROCm 10.0 running on SiFive’s BigSky datacenter development server. SiFive P870-D CPUs served as the… Read More
Quantum Equivalence Checking. Innovation in Verification
Can quantum computing have any relevance to EDA? This month’s paper suggests it might have a role someday, in accelerating one of the most fundamental of EDA algorithms: SAT. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A)… Read More
Why Advanced Chip Packaging Is Becoming a Design Problem
As chipmakers put more computing power into a single system, the challenge extends beyond making individual chips faster. They must connect multiple chips, memory stacks, power supplies, and sometimes optical components in a compact package. In the2026 TSMC OIP Forum talk “Addressing Inter-Die Complexity for 3D Multi-Die… Read More
Pollen Metrology: From a Decade-Long Bet to a Proven AI Platform for Semiconductor Manufacturing
Recently, I had the opportunity to speak with Johann Foucher, founder and CEO of Pollen Metrology, a French company whose journey offers a rare vantage point on how artificial intelligence is reshaping semiconductor manufacturing from the inside out. What makes Pollen Metrology’s story compelling isn’t just … Read More
Managing Power, Performance and Reliability in the Chiplet Era
Next-gen AI accelerators, high-performance processors, and complex computing architectures depend heavily on advanced packaging. Bringing multiple dies, chiplets, high-bandwidth memory, and advanced interconnects together into a single 2.5D or 3D package yields massive performance gains. However, this design evolution… Read More
Siemens and TSMC push AI deeper into chip design
Siemens and TSMC are expanding their collaboration on semiconductor design tools, with a focus on AI assisted workflows, advanced chip packaging and support for newer manufacturing processes. Their announcement centers on an AI agent intended to find and fix design rule violations: errors that can prevent a chip layout from… Read More
Agentic AI Can Reach GDS. What Must It Prove Before Engineers Trust It for Tapeout?
Agentic AI is beginning to move semiconductor engineering beyond copilots and isolated task automation.
From Agentrys’ public material and recent discussion, its architecture points toward a broader engineering flow:
Specification → RTL → verification → synthesis / physical design → PPA optimization → physical verification… Read More
TSMC OIP Ecosystem Forum 2026: Opening Remarks
The 2026 TSMC Open Innovation Platform (OIP) Ecosystem Forum was held on September 23, 2026, in Santa Clara, CA. This is the event where TSMC showcases the substantial progress made with its massive semiconductor ecosystem. As one would expect, AI was a key topic throughout the day, with some very impressive results reported and… Read More



Why ASML Is Racing to Build 110 EUV Machines