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                    [post_date] => 2020-01-28 10:00:14
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                    [post_content] => Our friends at Threshold Systems have a new class that may be of interest to you. It's an updated version of the Advanced CMOS Technology class held last May. As part of the previous class we did a five part series on The Evolution of the Extension Implant which you can see on the Threshold Systems SemiWiki landing page HERE. And here is the updated course description:
Date: Feb. 5, 6, 7, 2020
Location: SEMI Headquarters, 673 South Milpitas Blvd., Milpitas, California, 94035, USA
Class Schedule: Wednesday: 8:30 AM - 5:00 PM Thursday: 9:00 AM - 5:00 PM Friday: 9:00 AM - 5:00 PM
Tuition: $1,895
Course Description: The relentless drive in the semiconductor industry for smaller, faster and cheaper integrated circuits has driven the industry to the 10 nm node and ushered in a new era of high-performance three-dimensional transistor structures. The speed, computational power, and enhanced functionality of ICs based on this advanced technology promise to transform both our work and leisure environments. However, the implementation of this technology has opened a Pandora’s box of manufacturing issues as well as set the stage for a range of manufacturing challenges that require revolutionary new process methodologies as well as innovative, new equipment for the 10/7/5nm nodes and the upcoming 3nm node. This seminar addresses all of these manufacturing issues with technical depth and conceptual clarity, and presents leading-edge process solutions to the new and novel set of problems presented by 10nm and 7 nm FinFET technology and previews the upcoming manufacturing issues of the 5 nm Nanowire. The central theme of this seminar is an in-depth presentation of the key 10/7/5 nm node technical issues for Logic and Memory, including detailed process flows for these technologies. A key part of the course is a visual survey of leading-edge devices in Logic and Memory presented by the Fellow Emeritus of the world’s leading reverse engineering firm, TechInsights. His lecture is a visual feast of TEMs and SEMs of all of the latest and greatest devices being manufactured and is one of the highlights of the course. An update on the status of EUV lithography will be also be presented by a world-class lithographer who manages an EUV tool. His explanations of how this technology works, and the latest EUV breakthroughs, are enlightening as they are insightful. Finally, a detailed technology roadmap for the future of Logic, SOI, Flash Memory and DRAM process integration, as well as 3D packaging and 3D Monolithic fabrication will also be discussed. Each section of the course will present the relevant technical issues in a clear and comprehensible fashion as well as discuss the proposed range of solutions and equipment requirements necessary to resolve each issue. In addition, the lecture notes are profusely illustrated with extensive 3D illustrations rendered in full-color. What’s Included:
  • Three days of instruction by industry experts with comprehensive, in-depth knowledge of the subject material
  • A high quality set of full-color lecture notes (a $495 value), including SEM & TEM micrographs of real- world IC structures that illustrate key points
  • Continental breakfast, hot buffet lunch, and coffee, beverages, & snacks served at both morning and afternoon breaks

Who is the seminar intended for:

  • Equipment Suppliers & Metrology Engineers
  • Fabless Design Engineers and Managers
  • Foundry Interface Engineers and Managers
  • Device and Process Engineers
  • Design Engineers
  • Product Engineers
  • Process Development & Process Integration Engineers
  • Process Equipment Marketing Managers
  • Materials Supplier Marketing Managers  & Applications Engineers
Course Topics:

1. Process integration. The 10/7nm technology nodes represent a landmark in semiconductor manufacturing and they employs transistors that are faster and smaller than anything previously fabricated. However, such performance comes at a significant increase in processing complexity and requires the solution of some very fundamental scaling and fabrication issues, as well as the introduction of radical, new approaches to semiconductor manufacturing. This section of the course highlights the key changes introduced at the 10/7nm nodes and describes the technical issues that had to be resolved in order to make these nodes a reality.

  • The enduring myth of a technology node
  • Market forces: the shift to mobile
  • The Idsat equation
  • The motivations for High-k/Metal gates, strained Silicon
  • Sevice scaling metrics
  • Ion/Ioff curves, scaling methodology

2. Detailed 10nm Fabrication Sequence. The FinFET represents a radical departure in transistor architecture. It also presents dramatic performance increases as well as novel fabrication issues. The 10nm FinFET is the 3rd generation of non-planar transistor and involves some radical changes in manufacturing methodology. The FinFET’s unusual structure makes its architecture difficult for even experienced processing engineers to understand. This section of the course drills down into the details of 10nm FinFet structure and its fabrication, highlighting the novel manufacturing issues this new type of transistor presents. A detailed step-by-step 10nm fabrication sequence is presented (Front-end and Backend) that employs colorful 3D graphics to clearly and effectively communicate the novel FinFET architecture at each step of the fabrication process. Attention to key manufacturing pitfalls and specialty material requirements are pointed out at each phase of the manufacturing process, as well as the chemistries used.

  • Self-Aligned Quadruple Patterning (SAQP)
  • Fin-first and Fin-last integration strategies
  • Multiple Vt Hi-/Metal Gate integration strategies
  • Cobalt Contacts & Cobalt metallization
  • Contact over Active Gate methodology
  • Advanced Metallization strategies
  • Air-gap dielectrics

3. Nanowire Fabrication - the 5nm Node. Waiting in the wings is the Nanowire. The advent of this new and radically different 3D transistor features gate-all-around control of short channel effects and a high level of scalability. A detailed process flow of a Horizontal Nanowire fabrication process will be presented that is beautifully illustrated with colorful 3D graphics and which is technically accurate.

  • A step-by-step Horizontal Nanowire fabrication process flow
  • Key fabrication details and manufacturing problems
  • Nanowire SCE control and scaling
  • Resolving Nanowire capacitive coupling issues
  • Vertical versus Horizontal Nanowire architecture: advantages and disadvantages

4. DRAM Memory. DRAM memory haS evolved through many generations and multiple incarnations. Despite claims that DRAM memory is nearing its scaling limit, new technological developments keep pushing the scaling envelope to extremes. This part of the course examines the evolution of DRAM memory and presents a detailed DRAM process fabrication flow.

  • DRAM memory function and nomenclature
  • DRAM scaling limits
  • A DRAM process flow
  • The capacitor-less DRAM memory cell

5. 3D NAND Flash Memory. The advent of 3D NAND Flash memory is a game changer. 3D NAND Flash not only dramatically increases non-volatile memory capacity, it will also add at least three generations to the life of this memory technology. However, the structure and fabrication of this type of memory is radically different, even alien, to any traditional semiconductor fabrication methodology. This section of the course presents a step-by-step visual description of the unusual manufacturing methodology used to create 3D Flash memory, focusing on key problem areas and equipment opportunities. The fabrication methodology is presented as a series of short videos that clearly demonstrate the fabrication operations at each step of the process flow.

  • staircase fabrication methodology
  • the role of ALD in 3D Flash fabrication
  • controlling CDs in tall, vertical structures
  • detailed sequential video presentation of Samsung 3D NAND Flash
  • Intel-Micron 3D NAND Flash fabrication sequence
  • Toshiba BICS NAND Flash fabrication sequence

6. Advanced Lithography. Lithography is the “heartbeat” of semiconductor manufacturing and is also the single most expensive operation in any fabrication process. Without further advances in lithography continued scaling would difficult, if not impossible. Recently there have been significant breakthroughs in Extreme Ultra Violet (EUV) lithography that promise to radically alter and greatly simplify the way chips are manufactured. This section of the course begins with a concise and technically correct introduction to the subject and then provides in-depth insights into the latest developments in photolithography. Special attention is paid to EUV lithography, its capability, characteristics and the recent developments in this field.

  • Physical Limits of Lithography Tools
  • Immersion Lithography – principles and practice
  • Double, Triple and Quadruple patterning
  • EUV Lithography: status, problems and solutions
  • Resolution Enhancement Technologies
  • Photoresist: chemically amplified resist issues

7. Emerging Memory Technologies. There are at least three novel memory technologies waiting in the wings. Unlike traditional memory technologies that depend on electronic charge to store data, these memory technologies rely on resistance changes. Each type of memory has its own respective advantages and disadvantages and each one has the potential to play an important role in the evolution of electronic memory.

This section of the course will examine each type memory, discuss how it works, and what its relative advantages are in comparison with other new memory types.

  • Phase Change Memory (PCRAM), Cross-point memory; separating the hype from the reality
  • Resistive RAM (ReRAM) – a novel approach that comes in two variations
  • Spin Torque Transfer RAM (STT-RAM) – the brightest prospect?

8. Survey of leading edge devices. This part of the course presents a visual feast of TEMs and SEMs of real-world, leading edge devices for Logic, DRAM and Flash memory. The key architectural characteristics for a wide range of key devices will be presented and the engineering trade-offs and compromises that resulted in their specific architectures will be discussed. The Fellow Emeritus representative of the world’s leading chip reverse engineering firm will present the section of the course.

  • How to interpret Scanning and Transmission Electron microscopy images
  • A visual evolution of replacement gate metallization
  • DRAM structural analysis
  • 3D FLASH structural analysis
  • Currently available 14nm/10nm/7nm Logic offerings from various manufacturers

9. 3D Packaging Versus 3D Monolithic Fabrication. Unlike all other forms of advanced packaging that communicate by routing signals off the chip, 3D packaging permits multiple chips to be stacked on top of each other, and to communicate with each other using Thru-Silicon Vias (TSVs), as if they were all one unified microchip. An alternate is the 3D Monolithic approach, in which a second device layer is fabricated on a pre-existing device layer and electrically connected together employing standard nano-dimensional interconnects. Both approaches have advantages and disadvantages and promise to create a revolution in the functionality, performance and the design of electronic systems.

This part of the course identifies the underlying technological forces that have driven the development of Monolithic fabrication and 3D packaging, how they are designed and manufactured, and what the key technical hurdles are to the widespread adoption of these revolutionary technologies.

  • TSV technology: design, processing and production
  • Interposers: the shortcut to 3D packaging
  • The 3D Monolithic fabrication process
  • Annealing 3D Monolithic structures
  • The Internet of Things (IoT)

10. The Way forward: a CMOS technology forecast. Ultimately, all good things must come to an end, and the end of FinFET technology appears to be within sight. No discussion of advanced CMOS technology is complete without a peek into the future, and this final section of the course looks ahead to the 5/3.5/2.5 nm CMOS nodes and forecasts the evolution of CMOS device technology for Logic, DRAM and Flash memory.

  • Is Moore’s law finally coming to an end?
  • New nanoscale effects and their impact on CMOS device architecture and materials
  • The transition to 3D devices
  • Future devices: Quantum well devices, Nanowires, Tunnel FETs, Quantum Wires
  • The next ten years …
  • Is Moore’s law finally coming to an end?
  • New nanoscale effects and their impact on CMOS device architecture and materials
  • The transition to 3D devices
  • Future devices: Quantum well devices, Nanowires, Tunnel FETs, Quantum Wires
  • The next ten years …
Register Now
[post_title] => Advanced CMOS Technology 2020 (The 10/7/5 NM Nodes) [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => advanced-cmos-technology-2019-the-10-7-5-nm-nodes [to_ping] => [pinged] => [post_modified] => 2020-01-28 12:31:58 [post_modified_gmt] => 2020-01-28 20:31:58 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=275191 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [1] => WP_Post Object ( [ID] => 282068 [post_author] => 28497 [post_date] => 2020-01-28 06:00:45 [post_date_gmt] => 2020-01-28 14:00:45 [post_content] => Semiconductor Weekly Summary 2 Happy Chinese New Year.  Let’s hope the Year of the Rat brings a recovery for the semiconductor industry.  The initial signs are all good with many positive indications in the news this week, but let’s hope the Wuhan coronavirus doesn’t derail the recovery by becoming a global emergency.  To all those based in China stay safe and healthy. Here is my weekly summary of all the key semiconductor and technology news from around the world this week. In IC Insights 2020 edition of The McClean Report they predict that 26 out of the 33 IC product categories will show positive growth in 2020 with 5 products expected to enjoy double digit growth.  This is much more positive than 2019 where only 6 categories had positive growth, but still not as good as 2018.  Product categories expecting double growth, are NAND, Automotive special purpose IC,  DRAM, display drivers and embedded MPU. This week several major companies reported quarterly earnings, with a very optimistic message being given by all. Texas Instruments earnings report pointed to a recovery across the IC industry.  They said “most markets showed signs of stabilising” and forecast Q1 revenue midpoint of US$3.25billion. Last quarter they posted better than expected earnings of US$3.35billion, but this was still down 10% on a year ago and down 11% sequentially.  As Texas Instruments have a very broad portfolio across all markets it is a good indicator of the general market so it is quite optimistic that they see the market stabilising after 5 quarters of decline. STMicro also posted solid results for Q4 reporting revenue of US$2.75billion, up 7.9% sequentially on strong sales for low emission cars and next generation smartphones, though traditional older generation automotive products were down. The poor sales of established automotive products will also impact next quarter where they forecast up to 14% drop in sales.  STM did also announce they will invest $1.5billion in 2020 direct at capital expenditure. Intel also gave a very upbeat message at their Q4 earnings call.  Intel reported that strong cloud computing demand drove revenue in Q4 to US$20.2, up 8% on Q3.  For the year they reported revenue of $71.965billion, up 1.3% on 2018.  For the coming year they forecast revenue to be up a further 2% at $73.5billion, with revenue in Q1 at $19billion.  In addition Intel plans to spend $17 billion on capex to increase capacity to Ensure they can support customer demand and build inventory.. TSMC also gave a bullish message at their investors conference.  CC Wei, TSMC’s CEO said he expected revenue for 2020 to grow by more than 17% driven by demand for smartphones, high performance computer devices, the Internet of Things related applications and automotive electronics this year. In December the Global Purchasing Managers Index was neutral with a PMI of 50 on average, however this varies by country significantly with China, Taiwan and South Korea all showing modest expansion. Several 3rd party foundry vendors are entering or expanding their efforts in the silicon carbide (SiC) foundry business amid booming demand for the technology especially from automotive applications.  However the entrance of these new comers may not be so easy as the traditional IDM companies like Cree and Rohm use proprietary processes to differentiate their products. Finally, with many different variants of 7nm technology being made available here is a concise summary of the differences between the variants and the benefits. [post_title] => The Tech Week that was January 20th [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => the-tech-week-that-was-january-20th [to_ping] => [pinged] => [post_modified] => 2020-01-27 12:22:19 [post_modified_gmt] => 2020-01-27 20:22:19 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=282068 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [2] => WP_Post Object ( [ID] => 281970 [post_author] => 13 [post_date] => 2020-01-27 10:00:21 [post_date_gmt] => 2020-01-27 18:00:21 [post_content] => The use of machine learning (ML) to solve complex problems that could not previously be addressed by traditional computing is expanding at an accelerating rate. Even with advances in neural network design, ML’s efficiency and accuracy are highly dependent on the training process. The methods used for training evolved from CPU based software, to GPUs and FPGAs – which offer big advantages because of their parallelism. However, there are significant advantages to using specially designed domain specific computing solutions. Because training is so compute intensive, both total performance and performance per watt are both extremely important. It has been shown that domain specific hardware can offer several orders of magnitude improvement over GPUs and FPGAs when running training operations. [caption id="attachment_281972" align="aligncenter" width="919"]AI Domain Specific Processor AI Domain Specific Processor[/caption] On December 12th GLOBALFOUNDRIES (GF) and Enflame Technology announced a deep learning accelerator solution for training in data centers. The Enflame Cloudblazer T10 uses a Deep Thinking Unit (DTU) on GF’s 12LP FinFET platform with 2.5D packaging. The T10 has more than 14 billion transistors. It uses PCIe 4.0 and Enflame Smart Link for communication. The AI accelerator supports a wide range of data types, including FP32, FP16, BF16, Int8, Int16, Int32 and others. The Enflame DTU core features 32 scalable intelligent processors (SIP). Groups of 8 SIPs each are used to create 4 scalable intelligent clusters (SIC) in the DTU. HBM2 is used to provide high speed memory for the processing elements. The DTU and HBM2 are integrated with 2.5D packaging. This design highlights some of the interesting advantages of GF’s 12LP FinFET process. Because of high SRAM utilization in ML training, SRAM power consumption can play a major role in power efficiency. GF’s 12LP low voltage SRAM offers a big power reduction for this design. Another advantage of 12LP is much higher level of interconnect efficiency compared to 28nm or 7nm. While 7nm offers smaller feature size, there is no commensurate improvement in routing density for higher level metals. This means that for a highly connected design like the DTU, 12LP offers a uniquely efficient process node. Enflame is taking advantage of GF’s comprehensive selection of IP libraries for this project. The Enflame T10 has been sampled and is scheduled for production in early 2020 on GF’s Fab 8 in Malta New York. A company like Enflame has to walk a very fine line in designing an accelerator like the T10. The specific requirements for machine learning determine many of the architectural decisions for the design. On-chip communication and reconfigurability are essential elements. The T10 excels in this area with its on-chip reconfiguration algorithm. Their choice in selecting 12LP means optimal performance without the risk and expense of going to a more advanced node. GF is able to offer HBM2 and 2.5D packaging in an integrated solution, further reducing risk and complexity for the project. It is widely understood that increasing training data set size improves the operation and performance of ML applications. The only way to handle these increasing workloads is with fast and efficient accelerators that are designed specifically for the task. The CloudBlazer T10 looks like it should be an attractive solution. The full announcement and more information about both companies is available on the GLOBALFOUNDRIES website. [post_title] => Specialized Accelerators Needed for Cloud Based ML Training [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => specialized-accelerators-needed-for-cloud-based-ml-training [to_ping] => [pinged] => [post_modified] => 2020-01-23 15:14:44 [post_modified_gmt] => 2020-01-23 23:14:44 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=281970 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 1 [filter] => raw ) [3] => WP_Post Object ( [ID] => 281945 [post_author] => 28 [post_date] => 2020-01-27 06:00:57 [post_date_gmt] => 2020-01-27 14:00:57 [post_content] => New Family of FPGAs Speedster7tFPGAs, today and throughout the history of semiconductors, play a critical role in design enablement and electronic systems. Which is why we included the history of FPGAs in our book “Fabless: The Transformation of the Semiconductor Industry” and added a new chapter in the 2019 edition on the history of Achronix. In a recent blog post “FPGAs in the 2020s – The New Old Thing” Achronix reminds us that even though FPGAs are 35 years old the coming age of AI in the cloud represents a new FPGA growth opportunity to which I agree to 100%. In fact, during our first webinar series last year the Achronix ML webinar broke analytic records. Whether on the edge (eFPGA) or in the cloud (FPGA), programmable technology will play a critical role with the explosive data growth of the 5G era which has just begun.  We started tracking AI on SemiWiki in Q4 of 2015 and have published 182 blogs that have garnered close to one million views which is quite good. We also get to see who reads what, when, and where. Just to net it out, AI is everywhere and companies big and small are consuming AI design enablement information as fast as we can publish it, absolutely.

Back to the Achronix blog post “FPGAs in the 2020s – The New Old Thing”, it is full of interesting data and links that will be of great use if you are investigating FPGA use in the 5G era. I have also spent many hours researching AI and have finished several AI projects in collaboration with some big name companies and SemiWiki partners. Hit me up in the comments section if you want to talk more. AI is coming, there is no stopping it, and it is exciting so let’s talk.

FPGAs in the 2020s – The New Old Thing, January 8, 2020 FPGAs are the new old thing in semiconductors today. Even though FPGAs are 35 years old, the next decade represents a growth opportunity that hasn’t been seen since the early 1990s. Why is this happening now? There continues to be a data explosion in the world, with IDC predicting over 175 zetabytes of data will be generated annually by 2025. With this much data, there is a tremendous opportunity to analyze it for insights that can change and influence the world. AI will play a huge role in this data mining operation, and companies are growing their workforce with deep skills in machine learning and data analytics to meet the challenges of the future... And don't miss the upcoming Achronix webinar: New Block Floating Point Arithmetic Unit for processing AI/ML Workloads in FPGA Abstract: Block Floating Point (BFP) is a hybrid of floating-point and fixed-point arithmetic where a block of data is assigned a common exponent. We describe a new arithmetic unit that natively performs Block Floating Point for common matrix arithmetic operations and creates floating-point results. The BFP arithmetic unit supports several data formats with varying precision and range. BFP offers substantial power and area savings over traditional floating-point arithmetic units by trading off some precision. This new arithmetic unit has been implemented in the new family of 7nm FPGAs from Achronix. We cover the architecture and supported operations of the BFP unit. In this presentation, artificial intelligence and machine learning workloads are benchmarked to demonstrate the performance improvement and power savings of BFP as compared to half-precision (FP16) operations. About the presenter Dr. Mike Fitton is senior director, strategy and planning at Achronix. He has 25+ years of experience in the signal processing domain, including system architecture, algorithm development, and semiconductors across wireless operators, network infrastructure and most recently in machine learning. [post_title] => FPGAs in the 5G Era! [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => fpgas-in-the-5g-era [to_ping] => [pinged] => [post_modified] => 2020-01-26 21:06:29 [post_modified_gmt] => 2020-01-27 05:06:29 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=281945 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [4] => WP_Post Object ( [ID] => 281987 [post_author] => 19 [post_date] => 2020-01-26 10:00:23 [post_date_gmt] => 2020-01-26 18:00:23 [post_content] => Tesla is Teaching Us to Move Over Believe it or not, Tesla Motors is teaching us to be better drivers. One of the most remarkable lessons we are learning is that motor vehicles on public roadways ought to stay away from emergency and other service vehicles. In the U.S., we can all expect to hear more about “Move Over” laws – now enacted in all 50 states. It sometimes seems as if Tesla vehicles have an uncanny ability, while operating in Autopilot mode, to collide with emergency vehicles parked on highways while on official business. The latest incident occurred on December 29th in Cloverdale, Ind., when a Tesla Model 3 collided with a fire truck on Interstate 70. The fire truck reportedly had its lights flashing while parked in the left lane. A passenger in the vehicle was killed. (Coincidentally on the same day in Gardena, Ca., a Tesla Model S also reportedly operating on Autopilot ran a stoplight and crashed into the side of a Honda Civic, killing its two occupants.) Let’s be clear about one thing. Non-Tesla vehicles get into crashes every day in the U.S. (and around the world) resulting in 100 lives lost daily in the U.S. (3,500 globally). Highway fatalities have become sufficiently routine as to be accepted as the cost of owning and operating our own cars on public rights of way. Tesla crashes and the associated injuries and fatalities, on the other hand, are news events because the company has introduced computer-based driving into the equation in such a manner as to appear reckless and inspire opposition and outrage. Tesla crashes are also news events because they remain relatively rare. The unique inclination of Tesla’s operating on Autopilot to collide with emergency vehicles, though, has shown a spotlight on a big problem for which a solution may be in the offing. Last week, U.S. Department of Transportation Secretary Elaine Chao announced the commitment of $38M to equip emergency response vehicles and infrastructure with life-saving V2X technology in the 5.9GHz band. Chao noted that emergency response vehicles are involved in roughly 46,000 crashes, causing 17,000 injuries and 150 fatalities annually. The First Responder Safety Technology Pilot Program described by Chao will provide funding to equip emergency response vehicles, transit vehicles, and related infrastructure including traffic signals and highway-rail grade crossings with V2X technology. Chao did not specify the nature of the V2X wireless technology but her comments were interpreted to be technology agnostic – though she did note the agency’s preference that 5.9GHz be preserved for transportation applications regardless of the technology. Chao’s announced plans mirror legislation sponsored by U.S. Senators Dick Durbin (D-IL), and Tammy Duckworth (D-IL) and introduced in 2019 intended to establish a new national safety priority within an existing federal grant program to increase public awareness of “Move Over” laws and encourage implementation of life-saving digital alert technology. The USDOT’s announcement of these initiatives also follows appropriations language secured by Durbin, establishing a $5M pilot program to test and deploy these digital alert technologies to protect law enforcement, first responders, roadside crews, and others while on the job. (Worth noting a demonstration at CES2020 by Veoneer and Verizon equipping roadside workers with 5G infused safety vests for communication with oncoming vehicles.) Chicago-based HAAS Alert supports the Senate bill. The company has spent years implementing its vision of a “Safety Cloud” intended to aggregate digital alerts derived from tracking devices mounted on emergency response and service vehicles. The effort by HAAS Alert to create its safety cloud has taken many forms, but progress has been steady. The goal is to deliver a driver alerting system that might integrate with embedded in-vehicle infotainment systems and or smartphones to warn drivers of emergency vehicles stopped in the road ahead or approaching from behind or even approaching perpendicularly at an upcoming intersection. On January 6, Haas Alert announced a deal with Oshkosh-Pierce Manufacturing whereby HAAS Alert digital alerting technology will be included as a standard safety feature at no additional cost in Pierce's custom fire apparatus and as an available aftermarket solution for apparatus currently in service. HAAS Alert struck a similar deal with vehicle maker RevGroup in 2018. Other HAAS Alert deals and initiatives include:
  • Signed a partnership with Code3, one of the largest emergency vehicle and work truck market light manufacturers
  • Performed a Sprint "5G" test for emergency vehicle to emergency vehicle communication
  • Surpassed 100M driver alerts in September 2019; now in use in more than 90 cities
  • Fire Standards committees: NFPA950/951 added Digital Alerting language into standards. NFPA1901 is in public comment to have a standard for Digital Alerting into the fire space.
  • Integrated head unit digital alerting pilots with multiple automotive OEMs and suppliers
  • First DOT fleets added in 2019 along with utility trucks, a major U.S. Turnpike, DOT snowplows, a large state tollway. All with flashing light vehicles which will send out Digital Alerts to drivers.
  • Awarded Department of Homeland Security contractor for First Responder V2X - already commercialized and deployed
  • NHTSA funded Digital Alerting grant in 2019 for deployment and a study, Michigan's PlanetM funded deployment of digital alerting
  • Awarded an Air Force SBIR Contract for fleets
  • Co-founder of non-profit (https://www.arrowcoalition.org/ ) to bring awareness of Move Over Laws
HAAS Alert has learned that it isn’t easy to “do the right thing” when it comes to saving lives with driver alerting technology. Secretary Chao’s announcement has created confusion emphasizing, as it does, V2X technology. The HAAS Alert safety cloud is not yet a V2X solution – it is a V-2-cloud-2-V solution today. HAAS Alert has had to create a chipset swappable solution capable of supporting 3G, 4G, LTE, 5G, FirstNet, DSRC, and AT&T and Verizon SIMs. (The HAAS Alert solution does provide for inter-vehicle communications between first responder vehicles.) To help spread the word on its safety cloud HAAS Alert has published a guide describing both the safety cloud and something the company calls FleetFusion (https://tinyurl.com/tthyd3z). The company also integrates with Geotab and ESRI/ArcGIS platforms: https://www.prnewswire.com/news-releases/haas-alert-launches-on-the-geotab-marketplace-to-offer-enhanced-safety-service-300937015.html By now it’s clear that first responder fatalities are a problem for all road users, not just drivers of Tesla’s with Autopilot. There were 49 first responders killed in 2019 as a result of 90,000 collisions – the greatest single source of fatalities for this community. Illinois, alone, saw three state troopers die in roadside crashes. The numbers are already on the rise in 2020. Tesla is teaching us to Move Over. HAAS Alert is showing us how… and when. [post_title] => Tesla is Teaching Us to Move Over [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => tesla-is-teaching-us-to-move-over [to_ping] => [pinged] => [post_modified] => 2020-01-24 18:27:34 [post_modified_gmt] => 2020-01-25 02:27:34 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=281987 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 2 [filter] => raw ) [5] => WP_Post Object ( [ID] => 281878 [post_author] => 19 [post_date] => 2020-01-26 06:00:37 [post_date_gmt] => 2020-01-26 14:00:37 [post_content] => Woven City Smashing Toyotas Looms
Car companies are interesting creatures in a corporate world increasingly dominated by Internet-centric behemoths from Silicon Valley, Seattle, and China. While the denizens of the Internet have demonstrated their ability to create billions of dollars in shareholder value from the whims and whimsy of browsing consumers, car companies have built their valuations on approximating the desires of their potential customers and selling expensive hardware one unit at a time – usually through networks of dealers. While Internet-centric companies thrive on instant gratification, building solid foundations of value upon instant consumer feedback, car companies can be seen to be more or less “guessing” what consumers will want or need years in the future – due to the long product development cycle. When car companies get it right they, too, can create massive shareholder value from strong positive responses to their products: the Volkswagen Beetle, the Ford Model T, the Toyota Corolla. At CES2020, just a few weeks ago, maximum car maker consternation at the future vehicular desires of consumers was on full display with an emphasis on autonomous vehicles and even flying cars. As the maker of the single most popular vehicle of all time, the Toyota Corolla, Toyota was notable for touting its Woven City concept for a living environment enabled by artificial intelligence and ruled by robots and autonomous vehicles. CES2020 - Toyota presentation of Woven City concept - https://www.youtube.com/watch?v=NME7pGh-7rk This utopian or dystopian vision, depending on your point of view, reflected Toyota’s  desire to both segregate and weave together different forms of human transportation moving at different speeds: from pedestrians on foot to low-speed micro-mobility systems, to e-Pallette autonomous shuttles. Toyota intends to break ground on this vision at a 175-acre former manufacturing facility in the shadow of Mt. Fuji in 2021. In a press event at CES2020 Toyota’s CEO, Akio Toyoda, described the Toyota Woven City vision as a testing facility populated with as many as 2,000 citizens and accessible to scientists from Toyota as well as third parties to test new urban dwelling and transportation concepts. An appreciative audience warmly greeted Toyoda’s conceptual vision, but perhaps they were simply being polite. The implications of Toyota’s Woven City are both troubling and promising and CES2020 attendees can be forgiven for recognizing innovation. Toyota is to be applauded for affirmatively proposing a solution to the challenges of supporting human life with all of the economic, energy, and ecological concerns currently confronting policy makers and governments. It is no surprise that Toyota emphasizes hydrogen fuel cells at the heart of its vision along with e-Palette autonomous shuttles. Toyota was kind enough to create a CGI-type rendering of life in the Woven City showing a complete absence of individually owned and operated vehicles – which have been replaced by e-Pallette shuttles. E-Pallette shuttles are also used as delivery vehicles and mobile retail and service delivery platforms in this city of the future. Perhaps the strangest aspect of the Woven City video is that the kind of walkable urban space that is imagined looks almost identical to the existing walkable spaces created in the typical Tokyo landscape of today. Tokyo itself is a highly walkable city, with wider pedestrian areas – above and below ground – created for shopping, dining or nightlife. It is almost as if Toyota is trying to compete with and/or replace a cityscape that is already functioning effectively. We can forgive Toyota for focusing so narrowly on the promotion of its e-Pallette concept in addition to hydrogen propulsion. There are many experts and analysts forecasting a future dominated by autonomous shuttles – but few such visions have suggested the complete exclusion of individually owned vehicles. More remarkable, from the video shared at CES2020, was the division of transportation below and above ground. In the Woven City vision, utilities and product deliveries are managed below ground, while all people moving appears to take place above ground. In fact, the video shows very little people moving taking place. It is hard to accept this Toyota vision of the future from a nation where the subway system in the nation’s capital, Tokyo, moves more than eight million riders daily. The Woven City has no such subway system in addition to having no cars. But let’s assume, for a moment, that e-Pallette’s will take on the role of people moving. This raises the question of what the future of Toyota’s vehicle marketing will become. Does the Woven City suggest a future of Toyota selling commercial vehicles in the form of autonomous e-Pallette’s to developers and cities? It is worth bearing in mind that Toyota has a majority owned subsidiary – Toyota Housing Corporation – that is in the business of building detached houses and housing products for Japanese consumers. It’s not clear whether the Woven City vision represents an extension of this corporate vision, but it is worth noting – especially given the fact that Toyota Home stores can be found in most Japanese cities. The only criticism of the Woven City expressed in press reports came in reference to potential privacy violations or to the process of selecting the up-to-2,000 residents of the city. All in all, the entire venture appears far too artificial to address relevant challenges facing urban leaders around the world today. Transportation is at the core of many of the woes facing cities today. Many of the largest urban centers on the planet have maxed out their ability to accommodate individually owned and operated motor vehicles and are putting policies in place to pry people out of their cars. The latest initiatives include selling transportation as a subscription or service packaged in segments of hours or days or weeks and aggregated across multiple means of transportation – with an emphasis on public/shared resources. Some cities in the U.S., Europe, and elsewhere have gone further by making public transportation of one kind or another – buses in particular – entirely free. These strategies, intended to leverage existing infrastructure at minimal cost and maximum impact, are beginning to alter consumer behavior – de-emphasizing the automotive default. Toyota’s Woven City, like its hydrogen propulsion obsession, appears completely detached from current realities with no evolutionary path to adoption. And the exclusion of existing mass people movement solutions is particularly glaring coming from a country that is arguably a leader in the massive and high speed movement of people. Near the end of his presentation, CEO Toyoda notes Toyota’s legacy as a manufacturer of looms, a heritage shared by many other large Japanese electronics companies some of which, like Nakajima and Brother, first made sewing machines. Sad for me to say, the Woven City looms as a detached dystopian vision of future living that must be reconsidered in the context of current mass public transportation needs. More compelling, though arguably more complex, is the almost simultaneous announcement from Toyota of the launch of its Kinto car subscription and mobility portfolio in Europe. This multifaceted approach to expanding transportation options offers the prospect of having an immediate impact on the ownership and usage of existing vehicles. This is probably worth a closer look and more attention than the Woven City. More details can be found here: https://newsroom.toyota.eu/toyota-launches-kinto-a-single-brand-for-mobility-services-in-europe/
[post_title] => Woven City: Smashing Toyota's Looms [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => woven-city-smashing-toyotas-looms [to_ping] => [pinged] => [post_modified] => 2020-01-26 08:55:28 [post_modified_gmt] => 2020-01-26 16:55:28 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=281878 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [6] => WP_Post Object ( [ID] => 281956 [post_author] => 14 [post_date] => 2020-01-24 06:00:15 [post_date_gmt] => 2020-01-24 14:00:15 [post_content] => ASML 2020 Logic Memory
  • Good Q4 & 2019 despite weak memory
  • 2020 will be up year but memory an unknown
  • EUV ramp is on track - no China or memory impact
ASML reports an "in line" Q4 despite industry weak 2019
ASML reported sales of 4B Euros and a nice gross margin of 48% resulting in 2.70 Euros per share in earnings.  Orders came in at 2.4B Euros with roughly 80% coming from logic. Despite 2019 being a down year for semiconductor equipment as a whole, ASML managed to have 8% growth during 2019 as spending in the industry shifted back towards lithography purchases,  We expect this trend of enhanced litho spending to hold true in 2020 as the industry continues its EUV adoption. Logic (TSMC) remains the biggest driver at roughly 80% It is interesting to note that ASML was able to keep up its growth despite the fact that memory spend went from the majority of sales in 2019 down to roughly 20% of sales at the close of the year. Despite this huge shift in end market demand the company has maintained good growth. It obviously helps a lot to have strong backlog and a strong order book to be able to more efficiently manage the ebbs and flows of customer mix as 2019 was not an ebb and flow but more of a stampede away from memory to logic/foundry. It also helps that EUV is obviously focused on foundry/logic so the stampede was to ASML's benefit as well. "Focus" changes from making EUV work to making more EUV..... It is also very clear that now that we are well over the acceptance and HVM hurdle of EUV, attention is now turning to turning out more systems faster. Getting down cycle times and getting the supply chain cranked up while still hard is not as hard as working out the kinks has been over the last few years. 2020 looks to be about 35 EUV tools with an eye towards 50 in 2021.  These seem like reasonable, "doable" targets.  We don't think we need a full blown memory recovery to get to this years goal of 35 and memory will likely recover soon enough to support a 2021 goal of 50. There is still a lot of work to be done on high NA but less critical than the original work as high NA is an improvement rather than wholesale change. Multibeam delay helps KLA One of the few negative points raised, although minor, was the delay of multibeam.  While not totally unexpected given the complexity, it does give KLA a bit of time to work on their products and counter measures. In our view now that the war has been won on EUV, ASML can and should shift some more focus and spend to metrology & yield related issues and tools and products as it will also support the infrastructure for EUV going forward. Memory still an unknown It was clear from the call and clear in our view that the recovery of the memory industry is very much unclear. While NAND will no doubt recover first and DRAM some time later, the company gave no indication other than "just hoping" that memory recovers.  There was no evidence given nor implied of improved order activity or any other indication of memory spend coming back any time soon. Like the rest of the industry, the key to a strong up cycle is memory along with foundry/logic both working at the same time....we remain with foundry/logic at roughly 80% of business with memory barely plodding along. This is obviously more of a negative for players like Lam who are much more memory centric.  Even though business at Lam and Applied has picked up of late, its not like the rip roaring memory love fest. China is a non-issue There remains a lot of discussion in the press about poor ASML being the ping pong ball in a game between China and the US.  So far we see zero impact from any sales restriction to China.  We expect no near term ill effects on ASML and the real issues and impact are more political than financial.  Though ASML may not be happy to be a pawn it hasn't impacted their profitability or overall sales. We think there is a higher level of risk of the embargo spreading to US equipment companies that would see more financial impact. The stocks Given that the quarter was just in line with no surprises, we expect little movement in an already fully priced stock. There was also nothing surprising nor significantly impactful on other stocks that would drive the group one way or another.  The lack of any sign of memory recovery is a little bit disappointing for the group that has seen its shares on a tear despite the weakness. All in all no impact and we are not motivated to run out and chase stocks that have already run up nor are we tempted to short stocks that have such unusual support.
[post_title] => ASML "A Swing to Memory Looms" Nice performance while awaiting Memory bounce [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => asml-a-swing-to-memory-looms-nice-performance-while-awaiting-memory-bounce [to_ping] => [pinged] => [post_modified] => 2020-01-23 03:48:06 [post_modified_gmt] => 2020-01-23 11:48:06 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=281956 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 1 [filter] => raw ) [7] => WP_Post Object ( [ID] => 281814 [post_author] => 28686 [post_date] => 2020-01-23 06:00:59 [post_date_gmt] => 2020-01-23 14:00:59 [post_content] => China US Trade deal Will it Work A signed trade deal between the US and China has finally been signed. How much does this settle down the relationship and what will continue to cause problems? Given that in the same week as the deal was signed, the US government confirmed their new tough restrictions on allowing Chinese investment at any level into technology and many other sectors deemed sensitive in the US, clearly not all is well. For companies manufacturing in China, we have the benefit of certainty of what tariff levels we need to deal with.  If exports are in the 7.5% tariff category that’s low enough that we might just keep manufacturing in China. For multinationals with sophisticated supply chains and factories all around the world, their executives simply put the tariff costs into their models and determine whether Mexico, Turkey, Vietnam or China is now the best place to produce products for China. The losers in all this are smaller companies that perhaps only had 1 factory in China and who sold most of their output in the US. Shifting production is enormously disruptive and they may not even have the skills to do so. With clarity on tariffs, expect an uptick in investment in factories in China as companies move ahead with investments that had been on hold. China has agreed to purchase US$200bn over a 2017 base line from the US. How hard will that be and who wins and loses? ·        Manufactured goods: Provided Boeing is able to get the 737Max recertified in China sometime in the next 2 years, simply clearing the backlog on these planes ordered by China will generate many billions of incremental sales. Certainly, China will be willing to buy more technology products such as semiconductors from the US – but there may be friction on this if the US restricts the ability of Chinese companies to buy these products. China can buy more oil from the US, if the US actually has the capacity in its ports to enable this. China has a surplus of refining capacity and could import US oil to fill these refineries who will simply turnaround their output and export it. Winners – Chinese refineries, losers – refineries elsewhere in Asia. Automotive exports from the US to China are modest and not likely to grow much. Chinese consumers aren’t very interested in US style pick-up trucks. GM makes China specific cars in China; Tesla manufactures in China. The largest exporter of auto from the US to China is probably Mercedes. ·        Agricultural products. Probably the most important category for the Trump administration to see progress on in 2020. Soya beans and other cereals, beef and pork, premium fruit and vegetables. Winners US agricultural producers, losers South American producers and possibly Chinese consumers who may end up paying higher prices if US goods are not cost competitive in global markets. ·        Services. Again, there could be much friction here. China could say: “We are encouraging more Chinese tourists to visit the US and students to study in the US, but you, the US, won’t give them visas”. Chinese companies will be very willing to license US technologies, brands and other IP, but will CFIUS allow them to do so? So yes, there is a path to achieving the $200B – but it requires constructive engagement from the US, as much as from China. China also agreed to accelerate opening up financial services and other sectors to US companies, with faster issuance of licenses to operate. China made clear today that this opening is to companies of any nationality, not just American. Many of the announced moves on IP protection and technology transfer were contained in the new Foreign Investment Law which went into effect a few weeks ago. The trade deal does nothing to address the growing separation in many areas that both governments seem to be pushing for. In brief, restrictions on Chinese investments in US technology startups, in financial services, in any business that capture personally identifiable information will all be harder. Exports of technology products and IP from the US to China will be harder and China will continue to seek to become more self-sufficient. Market access in the US for Chinese technology companies will diminish further. China’s “secure and control” policy domestically will likewise reserve more of its technology market for Chinese companies. Chinese researchers will find it harder to obtain and retain positions at US universities or even in leading US tech companies. Chinese and US versions of product standards will emerge. The Chinese and US internets will continue to diverge and may eventually even lose interconnectivity. The threat to delist Chinese businesses currently trading on US stock exchanges remains real. The trade deal does remove some uncertainties, allowing companies to move forward with their investment plans for manufacturing. It will lead to greater purchases by China from the US, but not without creating significant frictions. And it does nothing to shift the direction of travel towards separation on flows of capital, of talent, of IP and of technology based goods [post_title] => US China Trade Deal - Will it Work? [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => us-china-trade-deal-will-it-work [to_ping] => [pinged] => [post_modified] => 2020-01-22 13:40:52 [post_modified_gmt] => 2020-01-22 21:40:52 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=281814 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [8] => WP_Post Object ( [ID] => 281806 [post_author] => 28 [post_date] => 2020-01-22 10:00:24 [post_date_gmt] => 2020-01-22 18:00:24 [post_content] =>
Ceva Webinar iRobot SemiWiki There is a live CEVA webinar coming up that you will NOT want to miss. We have been working with CEVA since 2012 and have posted 130 collaborative blogs. Those blogs have earned 927,901 views thus far and counting. The average blog on SemiWiki.com gets 5,885 views so they are ahead of the game.
One of the reasons CEVA is so popular on SemiWiki is due to the rising interest in commercial semiconductor IP from the electronics systems companies who are now doing their own chips.  Another reason is that CEVA provides some of the best background materials we get on SemiWiki. Additionally, CEVA is staffed by some of the smartest and most humble semiconductor professionals that we have the fortune to work with. A very good combination for a media portal partner, absolutely. REGSTRATION
Abstract
Robotics is a field that is growing rapidly. In particular, consumer ground-roving robots are becoming mainstream now that they commonly incorporate more intelligent navigation to operate more autonomously. Inertial measurement units (IMUs) are sensors that are essential for achieving precise navigation. IMUs can be used as a primary sensor for navigation or as a complementary sensor that helps VSLAM systems achieve robust performance. But making use of IMUs requires deep understanding of their idiosyncrasies and modeling to assess their impact. In this webinar, engineers will learn about the challenges when working with IMUs, how IMUs are applied in different robotics applications, and what is necessary to test IMU-based robots to achieve great performance. Join CEVA's experts to learn about:
  • Consumer Robot Vacuum Industry Overview
  • Common home robot navigation paradigms
  • Sensor idiosyncrasies and the importance of qualifying sensors
  • How to maintain accuracy over time, temperature, and environment
  • How to create robust algorithms and verify performance
Target Audience
Design, system, and product engineers looking to enhance their understanding of IMUs, sensor fusion, and how they relate to SLAM. Robot OEMs interested in navigation for their ground-roving robots. Speakers Charles Pao Sr. Marketing Specialist, Sensor fusion BU, CEVA Steve Scheirey Sr. Director, Software, Sensor fusion BU, CEVA About CEVA, Inc. CEVA is the leading licensor of wireless connectivity and smart sensing technologies. We offer Digital Signal Processors, AI processors, wireless platforms and complementary software for sensor fusion, image enhancement, computer vision, voice input and artificial intelligence, all of which are key enabling technologies for a smarter, connected world. We partner with semiconductor companies and OEMs worldwide to create power-efficient, intelligent and connected devices for a range of end markets, including mobile, consumer, automotive, robotics, industrial and IoT. Our ultra-low-power IPs include comprehensive DSP-based platforms for 5G baseband processing in mobile and infrastructure, advanced imaging and computer vision for any camera-enabled device and audio/voice/speech and ultra-low power always-on/sensing applications for multiple IoT markets. For sensor fusion, our Hillcrest Labs sensor processing technologies provide a broad range of sensor fusion software and IMU solutions for AR/VR, robotics, remote controls, and IoT. For artificial intelligence, we offer a family of AI processors capable of handling the complete gamut of neural network workloads, on-device. For wireless IoT, we offer the industry's most widely adopted IPs for Bluetooth (low energy and dual mode), Wi-Fi 4/5/6 (802.11n/ac/ax) and NB-IoT. Visit us at www.ceva-dsp.com and follow us on TwitterYouTube, FacebookLinkedIn and Instagram.
[post_title] => Using IMUS and SENSOR FUSION to Effectively Navigate Consumer Robotics [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => using-imus-and-sensor-fusion-to-effectively-navigate-consumer-robotics [to_ping] => [pinged] => [post_modified] => 2020-01-22 05:25:13 [post_modified_gmt] => 2020-01-22 13:25:13 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=281806 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [9] => WP_Post Object ( [ID] => 281122 [post_author] => 16 [post_date] => 2020-01-22 06:00:26 [post_date_gmt] => 2020-01-22 14:00:26 [post_content] => Formal verification has made significant inroads in RTL and gate-level verification because it provides complementary strengths to conventional dynamic verification methods; using both provides higher levels of coverage and confidence in the correctness of an implementation. I haven’t heard as much about formal use in high-level synthesis (HLS) flows so was interested to see a white paper from Renesas on how they use Catapult formal tools in this context. SLEC verification First, why even use formal in such a flow? One reason is obvious. When you synthesize from one format to another, from C++ to RTL or from RTL to gates, no amount of simulation is going to prove conclusively that synthesis didn’t introduce some subtle error along the way. That’s why equivalence checking was invented, to prove that at minimum the input and output implementations are functionally equivalent at a cycle-level. Another reason is to do some level of formal checking on the C++ itself. A couple of examples are out-of-range-accesses on arrays and uninitialized memory reads. You might catch these in C++ simulation, but you might not. Experienced programmers know that behind rarely taken branches can lurk dragons; formal is a good way to expose such problems. And the beauty of these methods is that they not only discover that a problem is possible, but they also show you how to create that problem, which should make it easier to figure out a fix. Still, the bulk of Renesas’ usage is in equivalence checking and this starts with C++ to C++ checks. Renesas talks about image processing IP and communication IP, both natural applications for HLS. Both types of design are intrinsically complex and will evolve through multiple iterations. Equivalence checking between C++ revs can assure as completely as possible that unintended functional changes are not introduced. This is sequential equivalence checking and will not always get to a proof of equivalence (or no-equivalence) without a little assistance. What will push a proof towards convergence in these cases is more hints (constraints) on behavior, such as bounding the range of an apparently unbound array index. The best-known application of equivalence checking in HLS flows is in comparing the source C++ with the synthesized RTL. There’s an advantage here (I’m guessing) in having the HLS synthesizer and the SLEC equivalence checker come from the same product group. The checker knows what kinds of transformations the synthesizer can make, such as how it inserts pipeline stages, and can factor these in when looking for a complete proof. I believe based on my reading of the Renesas white paper that they only edit the source C++, so all RTL changes are based on re-synthesis from source updates. They run equivalence checking on each RTL drop to establish either that they can get to a full proof or to find any bottlenecks to getting to proofs. This is with the goal of ensuring a full proof by the time they get to the final RTL drop. Methods to help along full-proofs at this level are pretty familiar – help in identifying equivalence points between the two designs, along with some level of abstraction and hierarchical proving. Renesas results are impressive in comparison with verification through extensive simulation. They show one example, for an image processor IP, in which they were able to reduce turnaround time from 260 days (simulation-based) to 4 days using equivalence checking. Of course you still want to do lots and lots of simulation (in C+) to prove functionality and performance. Catapult SLEC removes the need to worry about implementation bugs being introduced in mapping from C++ to RTL. You can read the Renesas white paper HERE. [post_title] => Formal and High-Level Synthesis [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => formal-and-high-level-synthesis [to_ping] => [pinged] => [post_modified] => 2020-01-07 09:38:56 [post_modified_gmt] => 2020-01-07 17:38:56 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=281122 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) ) [post_count] => 10 [current_post] => -1 [in_the_loop] => [post] => WP_Post Object ( [ID] => 275191 [post_author] => 28 [post_date] => 2020-01-28 10:00:14 [post_date_gmt] => 2020-01-28 18:00:14 [post_content] => Our friends at Threshold Systems have a new class that may be of interest to you. It's an updated version of the Advanced CMOS Technology class held last May. As part of the previous class we did a five part series on The Evolution of the Extension Implant which you can see on the Threshold Systems SemiWiki landing page HERE. And here is the updated course description:
Date: Feb. 5, 6, 7, 2020
Location: SEMI Headquarters, 673 South Milpitas Blvd., Milpitas, California, 94035, USA
Class Schedule: Wednesday: 8:30 AM - 5:00 PM Thursday: 9:00 AM - 5:00 PM Friday: 9:00 AM - 5:00 PM
Tuition: $1,895
Course Description: The relentless drive in the semiconductor industry for smaller, faster and cheaper integrated circuits has driven the industry to the 10 nm node and ushered in a new era of high-performance three-dimensional transistor structures. The speed, computational power, and enhanced functionality of ICs based on this advanced technology promise to transform both our work and leisure environments. However, the implementation of this technology has opened a Pandora’s box of manufacturing issues as well as set the stage for a range of manufacturing challenges that require revolutionary new process methodologies as well as innovative, new equipment for the 10/7/5nm nodes and the upcoming 3nm node. This seminar addresses all of these manufacturing issues with technical depth and conceptual clarity, and presents leading-edge process solutions to the new and novel set of problems presented by 10nm and 7 nm FinFET technology and previews the upcoming manufacturing issues of the 5 nm Nanowire. The central theme of this seminar is an in-depth presentation of the key 10/7/5 nm node technical issues for Logic and Memory, including detailed process flows for these technologies. A key part of the course is a visual survey of leading-edge devices in Logic and Memory presented by the Fellow Emeritus of the world’s leading reverse engineering firm, TechInsights. His lecture is a visual feast of TEMs and SEMs of all of the latest and greatest devices being manufactured and is one of the highlights of the course. An update on the status of EUV lithography will be also be presented by a world-class lithographer who manages an EUV tool. His explanations of how this technology works, and the latest EUV breakthroughs, are enlightening as they are insightful. Finally, a detailed technology roadmap for the future of Logic, SOI, Flash Memory and DRAM process integration, as well as 3D packaging and 3D Monolithic fabrication will also be discussed. Each section of the course will present the relevant technical issues in a clear and comprehensible fashion as well as discuss the proposed range of solutions and equipment requirements necessary to resolve each issue. In addition, the lecture notes are profusely illustrated with extensive 3D illustrations rendered in full-color. What’s Included:
  • Three days of instruction by industry experts with comprehensive, in-depth knowledge of the subject material
  • A high quality set of full-color lecture notes (a $495 value), including SEM & TEM micrographs of real- world IC structures that illustrate key points
  • Continental breakfast, hot buffet lunch, and coffee, beverages, & snacks served at both morning and afternoon breaks

Who is the seminar intended for:

  • Equipment Suppliers & Metrology Engineers
  • Fabless Design Engineers and Managers
  • Foundry Interface Engineers and Managers
  • Device and Process Engineers
  • Design Engineers
  • Product Engineers
  • Process Development & Process Integration Engineers
  • Process Equipment Marketing Managers
  • Materials Supplier Marketing Managers  & Applications Engineers
Course Topics:

1. Process integration. The 10/7nm technology nodes represent a landmark in semiconductor manufacturing and they employs transistors that are faster and smaller than anything previously fabricated. However, such performance comes at a significant increase in processing complexity and requires the solution of some very fundamental scaling and fabrication issues, as well as the introduction of radical, new approaches to semiconductor manufacturing. This section of the course highlights the key changes introduced at the 10/7nm nodes and describes the technical issues that had to be resolved in order to make these nodes a reality.

  • The enduring myth of a technology node
  • Market forces: the shift to mobile
  • The Idsat equation
  • The motivations for High-k/Metal gates, strained Silicon
  • Sevice scaling metrics
  • Ion/Ioff curves, scaling methodology

2. Detailed 10nm Fabrication Sequence. The FinFET represents a radical departure in transistor architecture. It also presents dramatic performance increases as well as novel fabrication issues. The 10nm FinFET is the 3rd generation of non-planar transistor and involves some radical changes in manufacturing methodology. The FinFET’s unusual structure makes its architecture difficult for even experienced processing engineers to understand. This section of the course drills down into the details of 10nm FinFet structure and its fabrication, highlighting the novel manufacturing issues this new type of transistor presents. A detailed step-by-step 10nm fabrication sequence is presented (Front-end and Backend) that employs colorful 3D graphics to clearly and effectively communicate the novel FinFET architecture at each step of the fabrication process. Attention to key manufacturing pitfalls and specialty material requirements are pointed out at each phase of the manufacturing process, as well as the chemistries used.

  • Self-Aligned Quadruple Patterning (SAQP)
  • Fin-first and Fin-last integration strategies
  • Multiple Vt Hi-/Metal Gate integration strategies
  • Cobalt Contacts & Cobalt metallization
  • Contact over Active Gate methodology
  • Advanced Metallization strategies
  • Air-gap dielectrics

3. Nanowire Fabrication - the 5nm Node. Waiting in the wings is the Nanowire. The advent of this new and radically different 3D transistor features gate-all-around control of short channel effects and a high level of scalability. A detailed process flow of a Horizontal Nanowire fabrication process will be presented that is beautifully illustrated with colorful 3D graphics and which is technically accurate.

  • A step-by-step Horizontal Nanowire fabrication process flow
  • Key fabrication details and manufacturing problems
  • Nanowire SCE control and scaling
  • Resolving Nanowire capacitive coupling issues
  • Vertical versus Horizontal Nanowire architecture: advantages and disadvantages

4. DRAM Memory. DRAM memory haS evolved through many generations and multiple incarnations. Despite claims that DRAM memory is nearing its scaling limit, new technological developments keep pushing the scaling envelope to extremes. This part of the course examines the evolution of DRAM memory and presents a detailed DRAM process fabrication flow.

  • DRAM memory function and nomenclature
  • DRAM scaling limits
  • A DRAM process flow
  • The capacitor-less DRAM memory cell

5. 3D NAND Flash Memory. The advent of 3D NAND Flash memory is a game changer. 3D NAND Flash not only dramatically increases non-volatile memory capacity, it will also add at least three generations to the life of this memory technology. However, the structure and fabrication of this type of memory is radically different, even alien, to any traditional semiconductor fabrication methodology. This section of the course presents a step-by-step visual description of the unusual manufacturing methodology used to create 3D Flash memory, focusing on key problem areas and equipment opportunities. The fabrication methodology is presented as a series of short videos that clearly demonstrate the fabrication operations at each step of the process flow.

  • staircase fabrication methodology
  • the role of ALD in 3D Flash fabrication
  • controlling CDs in tall, vertical structures
  • detailed sequential video presentation of Samsung 3D NAND Flash
  • Intel-Micron 3D NAND Flash fabrication sequence
  • Toshiba BICS NAND Flash fabrication sequence

6. Advanced Lithography. Lithography is the “heartbeat” of semiconductor manufacturing and is also the single most expensive operation in any fabrication process. Without further advances in lithography continued scaling would difficult, if not impossible. Recently there have been significant breakthroughs in Extreme Ultra Violet (EUV) lithography that promise to radically alter and greatly simplify the way chips are manufactured. This section of the course begins with a concise and technically correct introduction to the subject and then provides in-depth insights into the latest developments in photolithography. Special attention is paid to EUV lithography, its capability, characteristics and the recent developments in this field.

  • Physical Limits of Lithography Tools
  • Immersion Lithography – principles and practice
  • Double, Triple and Quadruple patterning
  • EUV Lithography: status, problems and solutions
  • Resolution Enhancement Technologies
  • Photoresist: chemically amplified resist issues

7. Emerging Memory Technologies. There are at least three novel memory technologies waiting in the wings. Unlike traditional memory technologies that depend on electronic charge to store data, these memory technologies rely on resistance changes. Each type of memory has its own respective advantages and disadvantages and each one has the potential to play an important role in the evolution of electronic memory.

This section of the course will examine each type memory, discuss how it works, and what its relative advantages are in comparison with other new memory types.

  • Phase Change Memory (PCRAM), Cross-point memory; separating the hype from the reality
  • Resistive RAM (ReRAM) – a novel approach that comes in two variations
  • Spin Torque Transfer RAM (STT-RAM) – the brightest prospect?

8. Survey of leading edge devices. This part of the course presents a visual feast of TEMs and SEMs of real-world, leading edge devices for Logic, DRAM and Flash memory. The key architectural characteristics for a wide range of key devices will be presented and the engineering trade-offs and compromises that resulted in their specific architectures will be discussed. The Fellow Emeritus representative of the world’s leading chip reverse engineering firm will present the section of the course.

  • How to interpret Scanning and Transmission Electron microscopy images
  • A visual evolution of replacement gate metallization
  • DRAM structural analysis
  • 3D FLASH structural analysis
  • Currently available 14nm/10nm/7nm Logic offerings from various manufacturers

9. 3D Packaging Versus 3D Monolithic Fabrication. Unlike all other forms of advanced packaging that communicate by routing signals off the chip, 3D packaging permits multiple chips to be stacked on top of each other, and to communicate with each other using Thru-Silicon Vias (TSVs), as if they were all one unified microchip. An alternate is the 3D Monolithic approach, in which a second device layer is fabricated on a pre-existing device layer and electrically connected together employing standard nano-dimensional interconnects. Both approaches have advantages and disadvantages and promise to create a revolution in the functionality, performance and the design of electronic systems.

This part of the course identifies the underlying technological forces that have driven the development of Monolithic fabrication and 3D packaging, how they are designed and manufactured, and what the key technical hurdles are to the widespread adoption of these revolutionary technologies.

  • TSV technology: design, processing and production
  • Interposers: the shortcut to 3D packaging
  • The 3D Monolithic fabrication process
  • Annealing 3D Monolithic structures
  • The Internet of Things (IoT)

10. The Way forward: a CMOS technology forecast. Ultimately, all good things must come to an end, and the end of FinFET technology appears to be within sight. No discussion of advanced CMOS technology is complete without a peek into the future, and this final section of the course looks ahead to the 5/3.5/2.5 nm CMOS nodes and forecasts the evolution of CMOS device technology for Logic, DRAM and Flash memory.

  • Is Moore’s law finally coming to an end?
  • New nanoscale effects and their impact on CMOS device architecture and materials
  • The transition to 3D devices
  • Future devices: Quantum well devices, Nanowires, Tunnel FETs, Quantum Wires
  • The next ten years …
  • Is Moore’s law finally coming to an end?
  • New nanoscale effects and their impact on CMOS device architecture and materials
  • The transition to 3D devices
  • Future devices: Quantum well devices, Nanowires, Tunnel FETs, Quantum Wires
  • The next ten years …
Register Now
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Advanced CMOS Technology 2020 (The 10/7/5 NM Nodes)

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