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Siemens EDA is Applying Machine Learning to Back-End Wafer Processing Simulation

Siemens EDA is Applying Machine Learning to Back-End Wafer Processing Simulation
by Mike Gianfagna on 01-18-2021 at 6:00 am

Siemens EDA is Applying Machine Learning to Back End Wafer Processing Simulation

There’s a lot to unpack in the title of this post. First, Siemens EDA is the new name for Mentor, a Siemens Business. The organization continues to operate as part of Siemens Digital Industries Software.  The organization has released a white paper that describes research done with the American University of Armenia. The work examines… Read More


CEO Interview: Arun Iyengar of Untether AI

CEO Interview: Arun Iyengar of Untether AI
by Daniel Nenni on 01-15-2021 at 8:00 am

Arun Iyengar Chief Executive Officer

I had a chance to catch up with Arun Iyengar, CEO of Untether AI.  Untether AI recently unveiled its tsunAImi accelerator cards powered by the company’s runAI devices. Using at-memory computation, Untether AI breaks through the barriers of traditional von Neumann architectures, offering industry-leading compute density … Read More


ESL Expertise when You Need It. Spinning Up Faster

ESL Expertise when You Need It. Spinning Up Faster
by Bernard Murphy on 12-30-2020 at 6:00 am

CircuitSutra min

System-level expertise, once the domain a few architecture specialists, is now shouldering its way everywhere into chip design and verification. In virtual modeling together with OS and application software certainly. That now couples into mixed-level system-verification, using different levels of abstraction for different… Read More


ML plus formal for analog. Innovation in Verification

ML plus formal for analog. Innovation in Verification
by Bernard Murphy on 11-30-2020 at 6:00 am

innovation min

Can machine learning be combined with formal to find rare failures in analog designs? ML plus formal for analog – neat! Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I continue our series on research ideas. Here an idea from analog simulation sampling. Feel free to comment.

The Innovation

This month’s pick… Read More


Low Power SRAM Register Files for IoT, AI and Wearables

Low Power SRAM Register Files for IoT, AI and Wearables
by Tom Simon on 11-26-2020 at 10:00 am

SRAM register files

SRAM is the workhorse for on-chip memories, valued for its performance and easy integration with standard processes. The needs of wearable, IoT and AI SOCs have put a lot of pressure on the requirements for all on-chip memories. This is perhaps most evident in the area of power. AI chips that rely heavily on SRAM register files are… Read More


The Impact of AI-enabled EDA Tools on the Semiconductor Industry

The Impact of AI-enabled EDA Tools on the Semiconductor Industry
by Richard Wawrzyniak on 11-22-2020 at 10:00 am

AI Tools Blog 111820

The semiconductor industry today is faced with several substantial issues—the continuing rise in design costs for complex SoCs, the decrease in the incidence of first-time-right designs and the increase in the design cycle time against shrinking market windows and decreasing product life cycles. An additional factor has … Read More


Better Speech Recognition by Reducing Babble

Better Speech Recognition by Reducing Babble
by Bernard Murphy on 11-17-2020 at 6:00 am

I’ve become a bit of a connoisseur of voice-based control, so when Chris Rowen did a pitch on Babble Labs at Arm Dev Summit last month, I wanted to listen in.  Chris was the CEO of Babble Labs, recently acquired by the Cisco Webex group where he’s now listed as VP Engineering of the Voice Technology Group. You should expect to see this… Read More


The History and Significance of Power Optimization, According to Jim Hogan

The History and Significance of Power Optimization, According to Jim Hogan
by Mike Gianfagna on 11-13-2020 at 10:00 am

Jim Hogan

Power seems to be on everyone’s mind these days. Hyperscale data centers worry about operating costs unless power is optimized. The AI accelerators in the Edge can’t be effective without optimized power. Advanced 2.5 and 3D packages simply can’t remove the heat unless power is optimized.  And then there’s all those gadgets we … Read More


SiFive Expands RISC-V Technology and its Ecosystem at the Fall Linley Processor Conference

SiFive Expands RISC-V Technology and its Ecosystem at the Fall Linley Processor Conference
by Mike Gianfagna on 11-11-2020 at 10:00 am

SiFive Expands RISC V Technology and its Ecosystem at the Fall Linley Processor Conference

 

As the Linley Fall Processor Conference winds down, there are certain presenting companies that left a lasting impression.  SiFive is one of those companies. On October 21, SiFive introduced the newest member of the SiFive Intelligence family of processor coresSiFive Intelligence family of processor cores, based on… Read More


Achronix is Driving the Fourth FPGA Wave

Achronix is Driving the Fourth FPGA Wave
by Mike Gianfagna on 11-09-2020 at 8:00 am

Achronix and the Fourth FPGA Wave

Technology typically evolves in waves. Sometimes it’s referred to as a “revolution” or an “age”. The industrial revolution and the information age are examples. These kinds of categorizations help to clarify the impact of innovation in ways that are relevant to everyone – you can’t look away if the world is changing around you.… Read More