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White Paper: A Closer Look at Aging on Clock Networks

White Paper: A Closer Look at Aging on Clock Networks
by Tom Simon on 01-02-2022 at 6:00 am

Transistor Aging

We all know that designers work hard to reach design closure on SOC designs. However, what gets less attention from consumers is the effort that goes into ensuring that these chips will be fully operational and meeting timing specs over their projected lifetime. Of course, this is less important for chips used in devices with projected… Read More


WEBINAR: Overcome Aging Issues in Clocks at Sub-10nm Designs

WEBINAR: Overcome Aging Issues in Clocks at Sub-10nm Designs
by Daniel Nenni on 11-10-2021 at 6:00 am

Infinisim Webinar

We all know that designers work hard to reach design closure on SOC designs. However, what gets less attention from consumers is the effort that goes into ensuring that these chips will be fully operational and meeting timing specs over their projected lifetime. Of course, this is less important for chips used in devices with projected… Read More


WEBNAR: Challenges in analyzing High Performance clocks at 7nm and below process nodes

WEBNAR: Challenges in analyzing High Performance clocks at 7nm and below process nodes
by Tom Simon on 08-05-2021 at 10:00 am

Clock analysis rail to rail

Proper clock functionality and performance are essential for SoC operation. Static timing analysis (STA) tools have served well for verifying clocks, yet with new advanced process nodes, lower operating voltages, higher clock speeds and higher reliability requirements, STA tools alone can’t perform the kinds of analysis… Read More