WP_Term Object
(
    [term_id] => 18712
    [name] => Keysight EDA
    [slug] => keysight-eda
    [term_group] => 0
    [term_taxonomy_id] => 18712
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 3
    [filter] => raw
    [cat_ID] => 18712
    [category_count] => 3
    [category_description] => 
    [cat_name] => Keysight EDA
    [category_nicename] => keysight-eda
    [category_parent] => 157
    [is_post] => 
)
            
PW2022 Signature Banner 02
WP_Term Object
(
    [term_id] => 18712
    [name] => Keysight EDA
    [slug] => keysight-eda
    [term_group] => 0
    [term_taxonomy_id] => 18712
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 3
    [filter] => raw
    [cat_ID] => 18712
    [category_count] => 3
    [category_description] => 
    [cat_name] => Keysight EDA
    [category_nicename] => keysight-eda
    [category_parent] => 157
    [is_post] => 
)

Unlocking PA design with predictive DPD

Unlocking PA design with predictive DPD
by Don Dingee on 05-23-2022 at 10:00 am

Predictive DPD virtual test bench

Next up in this series on modulated signals is an example of multi-dimensional EM design challenges: RF power amplifiers (PAs). Digital pre-distortion (DPD) is a favorite technique for linearizing PA performance. Static effects are easy to model and correct, but PAs are notorious for interrelated dynamic effects spoiling … Read More


Shift left gets a modulated signal makeover

Shift left gets a modulated signal makeover
by Don Dingee on 03-31-2022 at 6:00 am

Modulated signals uncover combined effects in a shift left approach

Everyone saw Shift Left, the EDA blockbuster. Digital logic design, with perfect 1s and 0s simulated through perfect switches, shifted into a higher gear. But the dark arts – RF systems, power supplies, and high-speed digital – didn’t shift smoothly. What do these practitioners need in EDA to see more benefits from shift left? … Read More


WEBINARS: Board-Level EM Simulation Reduces Late Respin Drama

WEBINARS: Board-Level EM Simulation Reduces Late Respin Drama
by Don Dingee on 02-01-2022 at 6:00 am

Flat Z design and voltage ripple example in board-level EM simulation

Advanced board designs are fertile ground for misbehavior in time and frequency domains. Relying on intuition, then waiting until near-final product for power integrity (PI) or EMI testing almost guarantees board respins are coming. Lumped-parameter simulations of on-board power delivery networks (PDNs) struggle with … Read More