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Podcast EP374: How proteanTecs Tames Multi-Die Packaging Challenges with Nir Server

Podcast EP374: How proteanTecs Tames Multi-Die Packaging Challenges with Nir Server
by Daniel Nenni on 10-16-2026 at 10:00 am
Categories: Analytics, Chiplet, proteanTecs

Daniel is joined by Nir Sever, an industry veteran with over 30 years of technological and managerial experience in advanced VLSI engineering. Before joining proteanTecs, Nir served for 10 years as the COO of Tehuti Networks, a pioneer in the area of high-speed networking Semiconductors. Prior to that, he served for 9 years as … Read More

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TSMC’s AI Expansion Signals a Broader Shift in Computing

TSMC’s AI Expansion Signals a Broader Shift in Computing
by Daniel Nenni on 10-16-2026 at 8:00 am
Categories: Events, Semiconductor, TSMC

TSMC’s AI expansion

TSMC is describing an artificial intelligence boom that reaches beyond accelerator chips into the wider computing infrastructure needed to support increasingly capable AI systems. On the recent investor call, Chairman and CEO Dr. C.C. Wei presents strong demand, persistent supply constraints and an ambitious expansion … Read More

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Terafab’s Single Roof: Why Packaging, Not Lithography, Decides High Volume

Terafab’s Single Roof: Why Packaging, Not Lithography, Decides High Volume
by Admin on 10-16-2026 at 6:00 am
Categories: Semiconductor

Single Roof, Connected Silicon

By Shaurya Seth

Terafab is one of the most ambitious projects of the decade: $16.8 billion for phase one and up to $119 billion across four phases. A research fab in Austin iterates on process recipes, transistor designs, and packaging variants at a few thousand wafers per month. A volume fab in Grimes County targets 100,000 wafer… Read More

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Design the Right Chip: Why Prototyping Has to Be Easy

Design the Right Chip: Why Prototyping Has to Be Easy
by Daniel Nenni on 10-15-2026 at 10:00 am
Categories: EDA, Prototyping, S2C EDA

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Design the right chip. Design the chip right.

Every verification methodology in mainstream use answers the second half of that sentence and assumes the first. Simulation, emulation, formal, constrained-random testbenches, coverage closure — all of them take a specification as given and ask whether the implementation matches… Read More

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Why Semiconductor AI Starts with Data, Not Algorithms

Why Semiconductor AI Starts with Data, Not Algorithms
by Admin on 10-15-2026 at 8:00 am
Categories: AI, Semiconductor

Fig1 context

The next gains from AI in semiconductors will come less from models and more from making fab and test data reliable, connected and tied to engineering decisions.

By Sriram Nithin Gopal Lanka

Every few months there is a new AI model that can do more and semiconductor manufacturers are under pressure to put them to work. But ask the engineers… Read More

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Why AI Security Starts at the Chip Level

Why AI Security Starts at the Chip Level
by Daniel Nenni on 10-15-2026 at 6:00 am
Categories: AI, Chiplet, EDA, Security, Synopsys

Luminous Shield Over an AI Chip

Artificial intelligence is becoming part of the infrastructure that powers healthcare, transportation, finance, manufacturing, and everyday digital services. As these systems grow more capable, they also process more sensitive information and depend on increasingly complex hardware. The Synopsys white paper, “Securing… Read More

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CTO Interview with Sirish Munipalli of Moores Lab AI

CTO Interview with Sirish Munipalli of Moores Lab AI
by Daniel Nenni on 10-14-2026 at 12:00 pm
Categories: CEO Interviews, EDA, Moores Lab (AI)

Agentic AI for chip verification

Sirish Munipalli is Co-Founder and CTO of Moores Lab AI, where he leads the development of agentic AI for chip design verification, including SpecAgent(tm), the company’s specification and modeling platform. He has spent about 15 years designing and verifying complex silicon: FPGA prototyping at Intel, post-silicon validation… Read More

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What DARPA Taught Me About Building Trust into Silicon

What DARPA Taught Me About Building Trust into Silicon
by Admin on 10-14-2026 at 10:00 am
Categories: EDA, Semiconductor

semiwiki fig1 pass tradeoff

By Sajeed Mohammad

The most memorable slide I ever saw in a chip design review didn’t show a floorplan. It showed a target. The Defense Advanced Research Projects Agency (DARPA) program manager running AISS, Automatic Implementation of Secure Silicon, the program that funded my majority of PhD research, had put a target… Read More

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Delivering Silicon Systems Through AI Disruption, Part 1: Writing the Score

Delivering Silicon Systems Through AI Disruption, Part 1: Writing the Score
by Joel Jorgensen on 10-14-2026 at 8:00 am
Categories: AI, Flow Accel, Semiconductor Services, TSMC

Writing the Score SemiWiki

Score: the written music for an orchestra, with every section’s part laid out on the same page so they play together. In this article, it’s your designed workflows.

Is AI helping you hit your tape-out date, or putting it at risk? How would you know?

Every Director I talk to is being asked to use AI to deliver faster, or better,… Read More

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A Migration Feasibility Study Can Turn an Uncertain Re-Design into a Measurable Engineering Project

A Migration Feasibility Study Can Turn an Uncertain Re-Design into a Measurable Engineering Project
by Mike Gianfagna on 10-14-2026 at 6:00 am
Categories: IN2FAB, Semiconductor Services

A Migration Feasibility Study Can Turn an Uncertain Re Design into a Measurable Engineering Project

Moving semiconductor IP to a new process technology is often treated as a redesign problem. For analog and mixed-signal designs, however, starting again from the schematic can overlook an asset: the engineering knowledge embedded in the existing physical layout.

Device sizing, matching, symmetry, routing, shielding, placement,… Read More