The Next LLM Architecture? Innovation in VerificationLLMs have amazing capabilities but inference run times…Read More
Defect-Pattern Leveraged Inherent Fingerprinting of Advanced IC Package with TRIIn the quest to secure the authenticity and…Read More
LRCX- Coulda been worse but wasn't so relief rally- Flattish is better than downLam put in good quarter with flattish guide-…Read More
The demand for high-performance computing (HPC), data centers, and AI-driven applications has fueled the rise of 2.5D and 3D multi-die designs, offering superior performance, power efficiency, and packaging density. However, these benefits come with myriads of challenges, such as multi-physics, which need to be addressed.… Read More
Dan is joined by John Kibarian, president, chief executive officer and co-founder of PDF Solutions. He has served as president since 1991 and CEO since 2000.
John explains the evolution of PDF Solutions from its beginnings in 1992 to the present day. John describes moving from TCAD tools for design teams to a yield optimization … Read More
Systolic arrays, with their ability to highly parallelize matrix operations, are at the heart of many modern AI accelerators. Their regular structure is ideally suited to matrix/matrix multiplication, a repetitive sequence of row-by-column multiply-accumulate operations. But that regular structure is less than ideal … Read More
Formal For All!
“Do I need a PhD to use formal verification?”
“Can formal methods really scale?”
“Is it too difficult to write formal properties that actually prove something?”
“If I can’t get a proof, should I just hope for the best?”
“Do formal methods even offer useful coverage metrics?”
Discouraging words to say the least, but… Read More
The annual ITC event is happening this week in San Diego as semiconductor test professionals gather from around the world to discuss their emerging challenges and new approaches, so last week I had the opportunity to get an advance look at something new from Siemens named Tessent In-System Test software. Jeff Mayer, Product Manager,… Read More
I just read an interesting white paper on functional verification of analog blocks using SV-RNM (SystemVerilog real number modeling). The content is worth the effort to read closely as it elaborates a functional verification flow for RNM matching expectations for digital logic verification, from randomization to functional… Read More
Flexible LCD technology has spurred a wave of creativity in device design, including a new class of foldable phones and an update to the venerable flip phone. Besides the primary display inside the fold – sometimes taking the entire inside area – a smaller secondary display is often found outside the fold. Introducing the secondary… Read More
The 2024 DVCon (Design and Verification) Europe conference took place on October 15 and 16, in its traditional location at the Holiday Inn Munich City Centre. Artificial intelligence and software were prominent topics, along with the traditional DVCon topics like virtual platforms, RTL verification, and validation.
KLA reported… Read More
Dan is joined by Dr. Emre Ozer, Senior Director of Processor Development at Pragmatic Semiconductor. With 67 worldwide patents, and over 60 peer-reviewed publications to his name, he has extensive experience in CPU microarchitecture with particular expertise in performance modelling, fault tolerant CPUs, embedded machine… Read More
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