ASML’s decision to collaborate with Xanadu targets one of photonic quantum computing’s most unforgiving engineering constraints: photon loss. The companies will investigate advanced lithography processes for Xanadu’s photonic quantum hardware, focusing on whether tighter patterning control can suppress loss mechanisms… Read More
CTO Interview with Sirish Munipalli of Moores Lab AISirish Munipalli is Co-Founder and CTO of Moores…Read More
What DARPA Taught Me About Building Trust into SiliconBy Sajeed Mohammad The most memorable slide I…Read More
Delivering Silicon Systems Through AI Disruption, Part 1: Writing the ScoreScore: the written music for an orchestra, with…Read More
A Migration Feasibility Study Can Turn an Uncertain Re-Design into a Measurable Engineering ProjectMoving semiconductor IP to a new process technology…Read More
Teradyne Unveils Magnum E2 for the Next Wave of AI MemoryTeradyne has announced Magnum E2, a memory test…Read MoreSir Arthur C. Clarke Deserves a Nobel Prize
By Richard Curtin
Ever since the Silicon Catalyst 2023 Semiconductor Industry Forum (“Welcome to our AI Wonderland”) I’ve been convinced that the Nobel Prize committee needs to consider awarding a posthumous award to Sir Arthur.
To remind you, Sir Arthur’s “2001: A Space Odyssey” movie was released in 1968. At that point in time… Read More
Moving Beyond AI-Assisted Design – Agentrys Shows the Way with Agentic Loop Engineering
At Hot Chips 2026, OpenAI presented Jalapeño, an inference ASIC built with AI in the design loop. As reported from the session by ServeTheHome and Tom’s Hardware, OpenAI showed measured block-level wins over a human baseline — 56% on a BF16 multiply, alongside a 10% smaller matrix-unit area — within a roughly nine-month path from… Read More
ChipAgents Expands AI Across Chip Design. The Test Is Faster, Verified Results
ChipAgents is expanding its agentic AI platform across digital and analog semiconductor engineering, aiming to connect fragmented design workflows through a common system that can plan tasks, operate engineering tools and evaluate results.
The Santa Clara company says its IC-Star engine combines organizational design … Read More
Rethinking Phase Jitter: An Algorithmic Approach to Signal Integrity
Byline: Richard Shreiner
Modern semiconductor architectures are pushing the absolute limits of physical scaling. As data rates climb into sub-picosecond regimes across high-performance computing, 5G/6G infrastructure, and advanced AI clusters, physical layer (Layer 1) signal integrity has shifted from an engineering… Read More
Siemens and NVIDIA Accelerate Lithography for Next-Generation AI Chips
Siemens has announced advances in its collaboration with NVIDIA to accelerate computational lithography, addressing a demanding step in manufacturing advanced AI semiconductors. By integrating NVIDIA’s cuLitho library with Siemens Calibre manufacturing software, the companies aim to make sophisticated photomask optimization… Read More
CEO Interview with Francisco Almada Lobo of Critical Manufacturing
Francisco Almada Lobo is CEO and co-founder of Critical Manufacturing. He began his career at a CIM research institute and joined Siemens Semiconductors in 1997. In 2004 he led the migration of an MES in a running high-volume facility, and from 2005 to 2009 he managed the Porto Development Center for Infineon and Qimonda, responsible… Read More
Maskless EUV Lithography: An Alternative to E-Beam
Semiconductor manufacturing depends on lithography: the process of transferring tiny circuit patterns onto a silicon wafer. Conventional extreme-ultraviolet (EUV) lithography projects light with a wavelength of 13.5 nanometers through a reflective optical system, using a custom photomask to define each layer. It can … Read More
CEO Interview with Dr. Raj Talluri of Kulicke & Soffa
Dr. Talluri joined K&S in August 2026 as a member of the Board and assumed the role of President and Chief Executive Officer of K&S in September 2026. Prior to joining K&S, Dr. Talluri served as President, Chief Executive Officer and a member of the Board of Directors at Enovix Corporation, a Nasdaq-listed advanced … Read More
Podcast EP374: How proteanTecs Tames Multi-Die Packaging Challenges with Nir Server
Daniel is joined by Nir Sever, an industry veteran with over 30 years of technological and managerial experience in advanced VLSI engineering. Before joining proteanTecs, Nir served for 10 years as the COO of Tehuti Networks, a pioneer in the area of high-speed networking Semiconductors. Prior to that, he served for 9 years as … Read More


Rethinking Phase Jitter: An Algorithmic Approach to Signal Integrity