As a 45 year semiconductor professional born and raised in Silicon Valley I grew up with Nvidia and Jensen Huang. Jensen has been my #1 semiconductor CEO for many years and he still is today. My wife and I have met Jensen and his wife Lori at different social occasions and we were always struck by how down to earth they were. I also married… Read More
Golden Testcases You Can Check With a CalculatorTwo timing tools that agree can still both…Read More
Curvilinear OPC and next-gen photomask optimizationA vector-based approach for semiconductor manufacturing By Sagar…Read More
ChipNexus Brings Agentic AI into Established Analog Design FlowsChipNexus has introduced its NEX Analog Agent, bringing…Read More
Delivering Silicon Systems Through AI Disruption, Part 2: The ConductorConductor: the person who keeps every section of…Read MoreCTO Interview With Juan Rey, senior VP and general manager of Calibre and CTO of Siemens EDA
By Juan Rey, Chief Technology Officer, Siemens
Juan Rey is Head of Technology and Innovation for Electronic Design Automation (EDA) at Siemens and Vice President and General Manager for Calibre. He joined Mentor Graphics, now Siemens EDA, in 2001 and led engineering, research, development, and quality for Calibre before retiring… Read More
What 1,000 Arteris Design Starts Reveal About Semiconductor Innovation
Arteris has surpassed 1,000 customer silicon design starts using its interconnect intellectual property, a milestone that highlights an increasingly consequential shift in chip design: moving data efficiently is becoming as important as processing it.
The company’s November 5 announcement accompanies a report, The State… Read More
Bring Your Innovation to Silicon Valley at DAC 2027
The next generation of electronic systems starts with conversations between people solving difficult design challenges. For companies developing EDA tools, semiconductor IP, design services, and supporting technologies, DAC 2027 offers an opportunity to turn those conversations into customer relationships, partnerships,… Read More
CTO Interview Kevin Robinson, VP of Operations, yieldHUB
Kevin Robinson is VP of Operations at yieldHUB, where he leads global operations, program delivery, and customer execution. He oversees structured onboarding, customer delivery, and the scalability of yieldHUB’s operations worldwide.
Kevin brings more than 25 years of semiconductor experience across product and test engineering.… Read More
Semiconductors and SOI: From Bulk Wafers to Engineered Substrates
1. Why the substrate matters
Every transistor sits in, or on, a few hundred nanometres of crystal; the rest of the wafer is mechanical support and, often, a liability. Silicon won because it combines a moderate bandgap (1.12 eV), a native oxide (SiO2) of excellent quality, and the ability to be grown as near-perfect single crystals… Read More
NVHBM: Can Custom HBM Change Who Builds the Memory Stack?
NVIDIA’s NVHBM could change more than how memory connects to an AI accelerator. It could also change how the semiconductor industry divides responsibility for designing, manufacturing, and qualifying high-bandwidth memory.
According to October 18 reporting from Seoul Economic Daily, NVIDIA has asked Samsung, SK … Read More
Why Video Processing Matters for the Next Generation of Robots
Mobilint has begun mass production of next-generation edge AI chips that incorporate video codec technology from Chips&Media, the companies announced on November 4. The South Korean partners are targeting robotics applications, including humanoids, where several cameras can generate more video than a system can easily… Read More
CXO Interview with Solaiman Rahim of ChipAgents
Dr. Solaiman Rahim is a multidisciplinary technology executive with over 25 years of experience driving innovation in the chip automation space at the intersection of systems, semiconductors, high-performance computing, and AI. As Chief Product Officer at ChipAgents, he leads the scaling of the Agentic and Native AI platform… Read More
CPO’s Next Challenge: Turning Optical Performance into Manufacturable Systems
Why integration boundaries, assembly strategies, and manufacturing yield must be engineered together
The Shift from Optical Performance to Manufacturing Scale
Co-packaged optics (CPO) is moving beyond laboratory demonstrations toward commercial deployment in AI infrastructure. As switch bandwidth continues to increase,… Read More



The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival