You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!

Already a member? Log In

WP_Term Object
(
    [term_id] => 51
    [name] => RISC-V
    [slug] => risc-v
    [term_group] => 0
    [term_taxonomy_id] => 51
    [taxonomy] => category
    [description] => 
    [parent] => 178
    [count] => 44
    [filter] => raw
    [cat_ID] => 51
    [category_count] => 44
    [category_description] => 
    [cat_name] => RISC-V
    [category_nicename] => risc-v
    [category_parent] => 178
    [is_post] => 
)

November 14, 2019November 14, 2019

SiFive is Teaming with Many of the Most Prestigious Universities in South America to Engage Academia in the RISC-V Ecosystem!

SiFive is Teaming with Many of the Most Prestigious Universities in South America to Engage Academia in the RISC-V Ecosystem!
by Swamy Irrinki on 11-14-2019 at 2:00 pm
Categories: IP, RISC-V, SiFive

Image RemovedWe’re confirming seats in São Paulo, Porto Alegre, Montevideo, Buenos Aires and Bucaramanga for the South American leg of our worldwide 2019 SiFive Tech Symposiums and Workshops. These five events will be focused heavily on academia, which is a key focus for SiFive. In fact, we are co-hosting these events with many… Read More

October 30, 2019October 22, 2019

Arm Reveals Custom Instructions, Mbed Partner Governance

Arm Reveals Custom Instructions, Mbed Partner Governance
by Bernard Murphy on 10-30-2019 at 6:00 am
Categories: ARM, IoT, IP, RISC-V
1 Comment

At TechCon Arm announced two more advances against competitive threats, one arguably tactical and the other strategic, at least in this writer’s view. The tactical move was to add support for custom instructions, the ability to collapse multiple instructions into a single instruction through customer-added logic which hooks… Read More

October 17, 2019October 17, 2019

The SiFive Tech Symposiums are Heading To Portland and Seattle Next Week!

The SiFive Tech Symposiums are Heading To Portland and Seattle Next Week!
by Swamy Irrinki on 10-17-2019 at 2:00 pm
Categories: IP, RISC-V, SiFive

Image RemovedWe’re confirming seats in Portland and Seattle for the Pacific Northwest leg of our worldwide 2019 SiFive Tech Symposiums. We are pleased to have Mentor, A Siemens Business as our co-host, and Lauterbach, a leader in microprocessor development tools, as our partner in both cities. The Portland symposium will take… Read More

October 5, 2019October 12, 2019

SiFive Continues to Foster RISC-V in the Middle East With Tech Symposiums

SiFive Continues to Foster RISC-V in the Middle East With Tech Symposiums
by Swamy Irrinki on 10-05-2019 at 8:00 am
Categories: IP, RISC-V, SiFive

Workshops Coming to Istanbul, Amman, Cairo and Abu Dhabi

Image Removed

SiFive is continuing its tour through the Middle East with highly educational RISC-V Tech Symposiums and Workshops in the key locations of Istanbul, Amman and Cairo. These cities are some of the most technologically advanced in the region, and we are eager … Read More

September 3, 2019September 17, 2019

SiFive to Host its Tech Symposium on RISC-V in Israel on September 5

SiFive to Host its Tech Symposium on RISC-V in Israel on September 5
by Swamy Irrinki on 09-03-2019 at 10:00 pm
Categories: IP, RISC-V, SiFive

There’s no question that the RISC-V ISA is revolutionizing the semiconductor ecosystem around the world. We see Israel as the epicenter of RISC-V based development and innovation in the Middle East. For the second year in a row, SiFive will be hosting its Tech Symposium on RISC-V in Israel to help foster the growth and momentum that�… Read More

July 27, 2019August 1, 2019

SiFive Fosters RISC-V Collaboration and Education in India and Bangladesh Via Symposiums, Tutorials and Workshops

SiFive Fosters RISC-V Collaboration and Education in India and Bangladesh Via Symposiums, Tutorials and Workshops
by Swamy Irrinki on 07-27-2019 at 4:00 am
Categories: Events, IP, RISC-V, SiFive

Image Removed

Last year we hosted several SiFive Tech Symposiums in India to help promulgate the RISC-V ecosystem in the region. The enthusiastic reception from those in industry as well as students and faculty at India’s most esteemed universities was inspiring. This July and August, we’re bringing the SiFive Tech Symposium… Read More

June 28, 2019June 28, 2019

2019 GSA Silicon Summit and SiFive

2019 GSA Silicon Summit and SiFive
by Daniel Nenni on 06-28-2019 at 8:00 am
Categories: Events, IP, RISC-V, SiFive
2 Comments

Naveed Sherwani, President and CEO of SiFive, did the keynote for this year’s Silicon Summit. This is one of the premier events for the C level executives in Silicon Valley, absolutely. Naveed is one of the top visionaries for the semiconductor industry and he certainly did not disappoint this time or any other time in my experience.… Read More

June 17, 2019June 19, 2019

Considering SiFive: What Should I Get to Implement a RISC-V Core?

Considering SiFive: What Should I Get to Implement a RISC-V Core?
by Randy Smith on 06-17-2019 at 10:00 am
Categories: IP, RISC-V, SiFive

Image RemovedI have an old weathered leather-clad black notebook with a National Semiconductor logo on its face that I have used since 2001. It has sentimental value to me. First, it reminds me of where I was on 9/11, having breakfast with a group of attendees to National Semiconductor’s executive event in Laguna Niguel, CA. We were… Read More

June 14, 2019June 13, 2019

#56thDAC SerDes, Analog and RISC-V sessions

#56thDAC SerDes, Analog and RISC-V sessions
by Eric Esteve on 06-14-2019 at 5:00 am
Categories: Events, IP, IPnest, RISC-V, Semiconductor Services
2 Comments

The good news is that the next five DAC events will take place in Moscone Center in San Francisco! If going to Las Vegas from the Bay area is an easy trip, coming from Europe to Las Vegas makes it a 24+hours journey… One obvious consequence was the poor attendance to the exhibition floor. But let’s be positive and notice that the number… Read More

June 10, 2019June 10, 2019

The RISC-V Revolution is Sweeping Across the APAC Region and Australia

The RISC-V Revolution is Sweeping Across the APAC Region and Australia
by Daniel Nenni on 06-10-2019 at 9:14 pm
Categories: Events, IP, RISC-V, SiFive

Join SiFive Tech Symposiums in Tokyo, Daejeon, Pangyo, Hsinchu, Singapore and Sydney

Image Removed

As we make our way around the world meeting and engaging with others in the semiconductor and hardware design community, we are seeing an increased interest in RISC-V based hardware innovation. This is due in large part to the emergence… Read More

Instance

Array
(
    [node_name] => RISC-V
    [node_id] => Array
        (
            [0] => 2
            [1] => 283
        )

)

Nodes

Threads

Array ( [0] => tribe-events-list-widget-5 [1] => search-2 [2] => media_image-2 [3] => text-6 ) WP_Term Object ( [term_id] => 51 [name] => RISC-V [slug] => risc-v [term_group] => 0 [term_taxonomy_id] => 51 [taxonomy] => category [description] => [parent] => 178 [count] => 44 [filter] => raw [cat_ID] => 51 [category_count] => 44 [category_description] => [cat_name] => RISC-V [category_nicename] => risc-v [category_parent] => 178 [is_post] => )

Tribe__Events__List_Widget Instance: 5Array ( [title] => Upcoming Events [limit] => 5 [no_upcoming_events] => [featured_events_only] => [jsonld_enable] => 1 [rw_opt] => Array ( [widget_select] => 1 [cpt_page] => 1 [others_author_archive] => 1 [others_404_page] => 1 [others_blog_page] => 1 ) [display_widget_mobile] => 1 )

Array ( [title] => Upcoming Events [limit] => 5 [no_upcoming_events] => [featured_events_only] => [jsonld_enable] => 1 [rw_opt] => Array ( [widget_select] => 1 [cpt_page] => 1 [others_author_archive] => 1 [others_404_page] => 1 [others_blog_page] => 1 ) [display_widget_mobile] => 1 )

WP_Widget_Search Instance: 2Array ( [display_widget_title] => on [title] => Search Semiwiki [rw_opt] => Array ( [widget_select] => 1 [others_blog_page] => 1 [others_author_archive] => 1 [others_404_page] => 1 [cpt_page] => 1 ) [display_widget_mobile] => 1 [rw_opt_exclude] => Array ( [pageid_274495] => 1 ) )

Array ( [display_widget_title] => on [title] => Search Semiwiki [rw_opt] => Array ( [widget_select] => 1 [others_blog_page] => 1 [others_author_archive] => 1 [others_404_page] => 1 [cpt_page] => 1 ) [display_widget_mobile] => 1 [rw_opt_exclude] => Array ( [pageid_274495] => 1 ) )

WP_Widget_Media_Image Instance: 2Array ( [display_widget_title] => on [attachment_id] => 280135 [url] => https://semiwiki.com/wp-content/uploads/2019/12/SemiWiKi-Ad-07.jpg [title] => Home/Default Page Advertisement 1 [size] => full [width] => 400 [height] => 400 [caption] => [alt] => [link_type] => custom [link_url] => https://secure.thresholdsystems.com/Training/AdvancedCMOSTechnology.aspx [image_classes] => [link_classes] => [link_rel] => [link_target_blank] => 1 [image_title] => Home/Default Page Advertisement 1 [rw_opt] => Array ( [widget_select] => 1 [pageid_196276] => 1 [category_96] => 1 [category_13] => 1 [category_95] => 1 [category_12] => 1 [category_7] => 1 [category_50] => 1 [category_90] => 1 [category_89] => 1 [category_94] => 1 [category_97] => 1 [category_22] => 1 [category_6435] => 1 [category_3611] => 1 [others_blog_page] => 1 ) [display_widget_mobile] => )

WP_Widget_Text Instance: 6Array ( [title] => [text] =>

Prototyping with Intel's New 80M Gate FPGA and S2C! Analyzing PowerMOS Devices to Reduce Power Loss and Improve Reliability REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation REPLAY: Avoiding CDM (Charged Device Model) ESD Failures REPLAY: eFPGA – "What a great idea! But I have no idea how I’d use it!" REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification REPLAY: Fabless: The Transformation of the Semiconductor Industry REPLAY: The Brave New World of Customized Memory REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning REPLAY: VLSI Design Methodology Development REPLAY: Lightspeed Data Sync - Design Workspace Problems Solved! REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats? REPLAY: How ASIC/SoC Prototyping Solutions Can Help You! REPLAY: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso® REPLAY: Taiwan ESD Workshop Recording REPLAY: Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction REPLAY: Text: A Year of Breakfast Bytes by Paul McLellan (Free PDF Version) REPLAY: Finding Your Way Through Verification REPLAY: Concerned about IP security threats for your SoCs? REPLAY: Achronix: Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip REPLAY: PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior REPLAY: Thermal-induced Reliability Challenges and Solutions for Advanced IC Design REPLAY: Choose the Right ASIC Manufacturing Model for Your Business [filter] => 1 [visual] => 1 [rw_opt] => Array ( [widget_select] => 1 [others_front_page] => 1 [cpt_page] => 1 [others_blog_page] => 1 ) [display_widget_mobile] => 1 )

Array ( [title] => [text] =>

Array ( [0] => rpwe_widget-9 [1] => gtranslate-3 [2] => media_image-8 [3] => xfrp_widget-2 [4] => better_recent_comments-2 ) WP_Term Object ( [term_id] => 51 [name] => RISC-V [slug] => risc-v [term_group] => 0 [term_taxonomy_id] => 51 [taxonomy] => category [description] => [parent] => 178 [count] => 44 [filter] => raw [cat_ID] => 51 [category_count] => 44 [category_description] => [cat_name] => RISC-V [category_nicename] => risc-v [category_parent] => 178 [is_post] => )

Recent_Posts_Widget_Extended Instance: 9Array ( [title] => Trending Now [title_url] => [ignore_sticky] => 1 [exclude_current] => 1 [limit] => 5 [offset] => 10 [order] => DESC [orderby] => date [post_type] => Array ( [0] => post ) [post_status] => publish [cat] => Array ( ) [tag] => Array ( ) [taxonomy] => [excerpt] => [length] => 10 [date] => [date_relative] => [date_modified] => [readmore] => [readmore_text] => Read More [comment_count] => [thumb] => [thumb_height] => 55 [thumb_width] => 55 [thumb_default] => http://images/semiwiki-small.png [thumb_align] => rpwe-alignleft [styles_default] => 1 [cssID] => [css_class] => [css] => .rpwe-block ul{ list-style: none !important; margin-left: 0 !important; padding-left: 0 !important; } .rpwe-block li{ border-bottom: 1px solid #eee; margin-bottom: 10px; padding-bottom: 10px; list-style-type: none; } .rpwe-block a{ display: inline !important; text-decoration: none; } .rpwe-block h3{ background: none !important; clear: none; margin-bottom: 0 !important; margin-top: 0 !important; font-weight: 400; font-size: 12px !important; line-height: 1.5em; } .rpwe-thumb{ border: 1px solid #eee !important; box-shadow: none !important; margin: 2px 10px 2px 0; padding: 3px !important; } .rpwe-summary{ font-size: 12px; } .rpwe-time{ color: #bbb; font-size: 11px; } .rpwe-comment{ color: #bbb; font-size: 11px; padding-left: 5px; } .rpwe-alignleft{ display: inline; float: left; } .rpwe-alignright{ display: inline; float: right; } .rpwe-aligncenter{ display: block; margin-left: auto; margin-right: auto; } .rpwe-clearfix:before, .rpwe-clearfix:after{ content: ""; display: table !important; } .rpwe-clearfix:after{ clear: both; } .rpwe-clearfix{ zoom: 1; } [before] => [after] => [rw_opt] => Array ( [widget_select] => 1 [others_front_page] => 1 [others_author_archive] => 1 [others_404_page] => 1 [pageid_275979] => 1 ) [display_widget_mobile] => )

GTranslateWidget Instance: 3Array ( [title] => Google Translate [rw_opt] => Array ( [pageid_275979] => 1 [others_front_page] => 1 [others_author_archive] => 1 [others_404_page] => 1 [widget_select] => 1 ) [display_widget_mobile] => )

WP_Widget_Media_Image Instance: 8Array ( [display_widget_title] => on [attachment_id] => 280148 [url] => https://semiwiki.com/wp-content/uploads/2019/12/Intel-80M-Webinar-300x300.jpg [title] => [size] => medium [width] => 400 [height] => 400 [caption] => [alt] => [link_type] => custom [link_url] => https://register.gotowebinar.com/register/1882953647871074061?source=SemiWIki+S2C [image_classes] => [link_classes] => [link_rel] => [link_target_blank] => [image_title] => Home/Default Page Advertisement 4 [display_widget_mobile] => [rw_opt] => Array ( [widget_select] => 1 [others_front_page] => 1 [pageid_275979] => 1 ) )

XF2_Latest_Posts_Widget Instance: 2Array ( [title] => Recent Forum Threads [title_url] => [ignore_sticky] => 0 [exclude_current] => 0 [limit] => 10 [offset] => 0 [order] => [orderby] => ID [post_type] => Array ( [0] => post ) [post_status] => [cat] => Array ( ) [tag] => Array ( ) [taxonomy] => [excerpt] => [length] => 0 [date] => [date_relative] => [date_modified] => [readmore] => [readmore_text] => [comment_count] => [thumb] => [thumb_height] => 0 [thumb_width] => 0 [thumb_default] => [thumb_align] => [styles_default] => [cssID] => [css_class] => [css] => [before] => [after] => [display_widget_mobile] => 1 [rw_opt] => Array ( [widget_select] => 1 [others_front_page] => 1 [pageid_274495] => 1 [pageid_275979] => 1 ) [sluglist] => ["jobs-dashboard"] [rw_opt_exclude] => Array ( [pageid_274493] => 1 ) )

Array ( [title] => Recent Forum Threads [title_url] => [ignore_sticky] => 0 [exclude_current] => 0 [limit] => 10 [offset] => 0 [order] => [orderby] => ID [post_type] => Array ( [0] => post ) [post_status] => [cat] => Array ( ) [tag] => Array ( ) [taxonomy] => [excerpt] => [length] => 0 [date] => [date_relative] => [date_modified] => [readmore] => [readmore_text] => [comment_count] => [thumb] => [thumb_height] => 0 [thumb_width] => 0 [thumb_default] => [thumb_align] => [styles_default] => [cssID] => [css_class] => [css] => [before] => [after] => [display_widget_mobile] => 1 [rw_opt] => Array ( [widget_select] => 1 [others_front_page] => 1 [pageid_274495] => 1 [pageid_275979] => 1 ) [sluglist] => ["jobs-dashboard"] [rw_opt_exclude] => Array ( [pageid_274493] => 1 ) )

Widget_Better_Recent_Comments Instance: 2Array ( [title] => Recent Article Comments [number] => 10 [avatar] => [date] => 1 [comment] => 1 [link] => 1 [display_widget_mobile] => 1 [rw_opt] => Array ( [widget_select] => 1 [others_front_page] => 1 [pageid_275979] => 1 ) [rw_opt_exclude] => Array ( [pageid_274493] => 1 ) )

Array ( [title] => Recent Article Comments [number] => 10 [avatar] => [date] => 1 [comment] => 1 [link] => 1 [display_widget_mobile] => 1 [rw_opt] => Array ( [widget_select] => 1 [others_front_page] => 1 [pageid_275979] => 1 ) [rw_opt_exclude] => Array ( [pageid_274493] => 1 ) )

SiFive is Teaming with Many of the Most Prestigious Universities in South America to Engage Academia in the RISC-V Ecosystem!

Arm Reveals Custom Instructions, Mbed Partner Governance

The SiFive Tech Symposiums are Heading To Portland and Seattle Next Week!

SiFive Continues to Foster RISC-V in the Middle East With Tech Symposiums

SiFive to Host its Tech Symposium on RISC-V in Israel on September 5

SiFive Fosters RISC-V Collaboration and Education in India and Bangladesh Via Symposiums, Tutorials and Workshops

2019 GSA Silicon Summit and SiFive

Considering SiFive: What Should I Get to Implement a RISC-V Core?

#56thDAC SerDes, Analog and RISC-V sessions

The RISC-V Revolution is Sweeping Across the APAC Region and Australia

Sponsor

Upcoming Events

IEDM 2019

Open FinTech Forum

Seminar: Domain-Specific Processor Design...

Early AXI4 SOC Performance Verification...

Improving the throughput of volume scan...

Search Semiwiki

Recent RISC-V Press

Imperas model and simulator certified by Andes as a reference for the new vector processor NX27V

Imperas delivers highest quality RISC-V RV32I compliance test suites to implementers and adopters of RISC-V

Semico Forecasts Strong Growth for RISC-V

The RISC-V Foundation Announces the “Student of the Year” and “Educator of the Year” Awards

RISC-V EMEA Roadshow Spotlight: AdaCore

RISC-V Gains Momentum as Industry Demands Custom Processors for New, Innovative Workloads

RISC-V EMEA Roadshow Spotlight: OneSpin Solutions

How the European Processor Initiative is Leveraging RISC-V for the Future of Supercomputing

RISC-V EMEA Roadshow Spotlight: MINRES Technologies

Recent Article Comments

Intel vs AMD vs Google vs Amazon vs NUVIA

Put Uber out of Our Misery

Put Uber out of Our Misery

Put Uber out of Our Misery

Put Uber out of Our Misery

Put Uber out of Our Misery

Why is Intel still short on chips?

Evolving Landscape of Self-Driving Safety Standards

2020 Semiconductor Foundry Landscape Update!

Is the ASIC Business Dead?