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October 16, 2019October 13, 2019

Automating Timing Arc Prediction for AMS IP using ML

Automating Timing Arc Prediction for AMS IP using ML
by Daniel Payne on 10-16-2019 at 6:00 am
Categories: EDA, Empyrean

NVIDIA designs some of the most complex chips for GPU and AI applications these days, with SoCs exceeding 21 billion transistors. They certainly know how to push the limits of all EDA tools, and they have a strong motivation to automate more manual tasks in order to quicken their time to market. I missed their Designer/IP Track Poster… Read More

September 19, 2019September 18, 2019

WEBINAR: AI-Powered Automated Timing Arc Prediction for AMS IP’s

WEBINAR: AI-Powered Automated Timing Arc Prediction for AMS IP’s
by Daniel Nenni on 09-19-2019 at 6:00 am
Categories: EDA, Empyrean

A directed approach to reduce Risk and improve Quality

Safety and reliability are critical for most applications of integrated circuits (ICs) today. Even more so when they serve markets like ADAS, autonomous driving, healthcare and aeronautics where they are paramount. Safety and reliability transcend all levels of an integrated… Read More

August 22, 2019September 17, 2019

Speeding up Circuit Simulation using a GPU Approach

Speeding up Circuit Simulation using a GPU Approach
by Daniel Payne on 08-22-2019 at 10:00 am
Categories: EDA, Empyrean, Events

The old adage that “Time is Money” certainly rings true in the semiconductor world where IC designers are being challenged with getting their new designs to market quickly, and correctly in the first spin of silicon. Circuit designers work at the transistor-level, and circuit simulation is one of the most time-consuming… Read More

August 1, 2019August 4, 2019

GPU-Powered SPICE – Understanding the Cost

GPU-Powered SPICE – Understanding the Cost
by Daniel Nenni on 08-01-2019 at 10:00 am
Categories: EDA, Empyrean, Events
2 Comments

To deploy a GPU-based SPICE solution, you need to understand the costs involved. To get your hands on this new report analyzing this specific issue, all you need to do is attend Empyrean’s upcoming webinar, “GPU-Powered SPICE: The Way Forward for Analog Simulation,” which will be held on Thursday, August 8, 2019, at 10:00 am (PDT).… Read More

July 10, 2019July 10, 2019

WEBINAR: GPU-Powered SPICE – The Way Forward for Analog Simulation

WEBINAR: GPU-Powered SPICE – The Way Forward for Analog Simulation
by Randy Smith on 07-10-2019 at 9:37 am
Categories: EDA, Empyrean, Events

Several years ago, I was a consultant to a company called Gauda, Inc. I enjoyed working with Gauda as the technology was interesting. On June 3, 2014, Gauda, Inc. was acquired by D2S, Inc. so their technology lives on. Gauda was focused on optical proximity correction (OPC) and optical proximity verification solutions utilizing… Read More

May 27, 2019October 8, 2019

The Changing Landscape for SPICE Circuit Simulators

The Changing Landscape for SPICE Circuit Simulators
by Daniel Payne on 05-27-2019 at 5:00 am
Categories: EDA, Empyrean

I first started using a SPICE circuit simulator in 1978 while at Intel and have followed that market ever since then. Back at DAC in 2012 I first heard of a Chinese EDA company called IC Scape with a SPICE circuit simulator called Aeolus, so I blogged about it. Fast forward to 2019 and I heard from Ravi Ravikumar, a former co-worker from… Read More

September 9, 2015June 14, 2019

Explore Your Interconnect the ICScape Way

Explore Your Interconnect the ICScape Way
by Paul McLellan on 09-09-2015 at 7:00 am
Categories: EDA, Empyrean

One of the surprises at DAC for ICScape was to be listed on Gary Smith’s list of companies to see. Surprised, since ICScape had never presented their products to him. They were listed under design debug. They don’t have a single product that really falls under that description, but rather a family of tools under the ICExplorer… Read More

May 26, 2015June 14, 2019

How Good Is Your Library? Are You Sure?

How Good Is Your Library? Are You Sure?
by Paul McLellan on 05-26-2015 at 7:00 am
Categories: EDA, Empyrean

One task that is not very exciting but is critical is that of library quality assurance. Many design groups have created their own procedures, often having been burned in the past, to ensure that the libraries that they use are good. Failure to do so has resulted in:… Read More

April 29, 2015June 14, 2019

How Good Are Your Clocks?

How Good Are Your Clocks?
by Paul McLellan on 04-29-2015 at 7:00 am
Categories: EDA, Empyrean

One of the trickiest tasks in designing a modern SoC is getting the clock tree(s) right. The two big reasons for this:

the clocks can consume 30% or more of the power of the whole chip, so minimizing the number of buffers inserted is critical to keeping power under control
the clock insertion delay and clock skew have a major impact on

April 1, 2015June 14, 2019

What is Skipper?

What is Skipper?
by Paul McLellan on 04-01-2015 at 1:00 am
Categories: EDA, Empyrean

What is Skipper? Well, it seems it’s a penguin in the movie Madagascar. And one of Barbie’s sisters. Who knew? But for Semiwiki readers it’s an integrated chip finishing platform from ICScape. Skipper can read in full-chip layout extremely fast, examine it and manipulate it in various ways, and write it out again.… Read More

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Analyzing PowerMOS Devices to Reduce Power Loss and Improve Reliability REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation REPLAY: Avoiding CDM (Charged Device Model) ESD Failures REPLAY: eFPGA – "What a great idea! But I have no idea how I’d use it!" REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification REPLAY: Fabless: The Transformation of the Semiconductor Industry REPLAY: The Brave New World of Customized Memory REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning REPLAY: VLSI Design Methodology Development REPLAY: Lightspeed Data Sync - Design Workspace Problems Solved! REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats? REPLAY: How ASIC/SoC Prototyping Solutions Can Help You! REPLAY: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso® REPLAY: Taiwan ESD Workshop Recording REPLAY: Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction REPLAY: Text: A Year of Breakfast Bytes by Paul McLellan (Free PDF Version) REPLAY: Finding Your Way Through Verification REPLAY: Concerned about IP security threats for your SoCs? REPLAY: Achronix: Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip REPLAY: PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior REPLAY: Thermal-induced Reliability Challenges and Solutions for Advanced IC Design REPLAY: Choose the Right ASIC Manufacturing Model for Your Business REPLAY: Prototyping with Intel's New 80M Gate FPGA and S2C! [filter] => 1 [visual] => 1 [rw_opt] => Array ( [widget_select] => 1 [others_front_page] => 1 [cpt_page] => 1 [others_blog_page] => 1 ) [display_widget_mobile] => 1 )

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Automating Timing Arc Prediction for AMS IP using ML

WEBINAR: AI-Powered Automated Timing Arc Prediction for AMS IP’s

Speeding up Circuit Simulation using a GPU Approach

GPU-Powered SPICE – Understanding the Cost

WEBINAR: GPU-Powered SPICE – The Way Forward for Analog Simulation

The Changing Landscape for SPICE Circuit Simulators

Explore Your Interconnect the ICScape Way

How Good Is Your Library? Are You Sure?

How Good Are Your Clocks?

What is Skipper?

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