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Empyrean Logo SemiWiki
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GPU-Powered SPICE – Understanding the Cost

GPU-Powered SPICE – Understanding the Cost
by Daniel Nenni on 08-01-2019 at 10:00 am

To deploy a GPU-based SPICE solution, you need to understand the costs involved. To get your hands on this new report analyzing this specific issue, all you need to do is attend Empyrean’s upcoming webinar, “GPU-Powered SPICE:  The Way Forward for Analog Simulation,” which will be held on Thursday, August 8, 2019, at 10:00 am (PDT).… Read More


WEBINAR: GPU-Powered SPICE – The Way Forward for Analog Simulation

WEBINAR: GPU-Powered SPICE – The Way Forward for Analog Simulation
by Randy Smith on 07-10-2019 at 9:37 am

Several years ago, I was a consultant to a company called Gauda, Inc.  I enjoyed working with Gauda as the technology was interesting. On June 3, 2014, Gauda, Inc. was acquired by D2S, Inc. so their technology lives on. Gauda was focused on optical proximity correction (OPC) and optical proximity verification solutions utilizing… Read More


56th DAC Empyrean Stepping Up ALPS with GPU Implementation

56th DAC Empyrean Stepping Up ALPS with GPU Implementation
by Daniel Nenni on 05-27-2019 at 11:00 am

As a testament to the technology advances developed and implemented into Empyrean ALPS™ by the engineering team, the product has seen a steady growth in the adoption by users. In addition, hearing directly from the users at DAC 2018 turned out to be an all-around success for the product as well as the product team to see ALPS beating… Read More


The Changing Landscape for SPICE Circuit Simulators

The Changing Landscape for SPICE Circuit Simulators
by Daniel Payne on 05-27-2019 at 5:00 am

Empyrean - ALPS

I first started using a SPICE circuit simulator in 1978 while at Intel and have followed that market ever since then. Back at DAC in 2012 I first heard of a Chinese EDA company called IC Scape with a SPICE circuit simulator called Aeolus, so I blogged about it. Fast forward to 2019 and I heard from Ravi Ravikumar, a former co-worker from… Read More


Explore Your Interconnect the ICScape Way

Explore Your Interconnect the ICScape Way
by Paul McLellan on 09-09-2015 at 7:00 am

One of the surprises at DAC for ICScape was to be listed on Gary Smith’s list of companies to see. Surprised, since ICScape had never presented their products to him. They were listed under design debug. They don’t have a single product that really falls under that description, but rather a family of tools under the ICExplorer… Read More


How Good Is Your Library? Are You Sure?

How Good Is Your Library? Are You Sure?
by Paul McLellan on 05-26-2015 at 7:00 am

One task that is not very exciting but is critical is that of library quality assurance. Many design groups have created their own procedures, often having been burned in the past, to ensure that the libraries that they use are good. Failure to do so has resulted in:… Read More


How Good Are Your Clocks?

How Good Are Your Clocks?
by Paul McLellan on 04-29-2015 at 7:00 am

One of the trickiest tasks in designing a modern SoC is getting the clock tree(s) right. The two big reasons for this:

  • the clocks can consume 30% or more of the power of the whole chip, so minimizing the number of buffers inserted is critical to keeping power under control
  • the clock insertion delay and clock skew have a major impact on
Read More

What is Skipper?

What is Skipper?
by Paul McLellan on 04-01-2015 at 1:00 am

What is Skipper? Well, it seems it’s a penguin in the movie Madagascar. And one of Barbie’s sisters. Who knew? But for Semiwiki readers it’s an integrated chip finishing platform from ICScape. Skipper can read in full-chip layout extremely fast, examine it and manipulate it in various ways, and write it out again.… Read More


Efficient Handling of Timing ECOs

Efficient Handling of Timing ECOs
by Daniel Nenni on 05-29-2013 at 8:00 pm

Today, in the design of any type of system on chip (SoC), timing closure is a major problem and it only gets worse with each new, and more advanced process technology. Timing closure is closely inter-leaved with power and clock design. The complexity of achieving closure rises sharply with increasing design density and advancing… Read More