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Cerebrus, the ML-based Intelligent Chip Explorer from Cadence

Cerebrus, the ML-based Intelligent Chip Explorer from Cadence
by Kalar Rajendiran on 07-29-2021 at 10:00 am

Screen Shot 2021 07 21 at 4.39.06 PM

Electronic design automation (EDA) has come a long way from its beginnings. It has enabled chip engineers from specifying designs directly in layout format during the early days to today’s capture in RTL format. Every advance in EDA has made the task of designing a chip easier and increased the design team productivity, enabling… Read More


SoC Vulnerabilities

SoC Vulnerabilities
by Daniel Payne on 07-29-2021 at 6:00 am

side channel attack

As I read both the popular and technical press each week I often see articles about computer systems being hacked, and here’s just a few vulnerabilities from this week:

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Optimize RTL and Software with Fast Power Verification Results for Billion-Gate Designs

Optimize RTL and Software with Fast Power Verification Results for Billion-Gate Designs
by Johannes Stahl on 07-28-2021 at 10:00 am

ZeBu Empower diagram

In every chip, power is a progressive problem to be solved. Designers have long had to rely on a combination of experience and knowledge to tackle this dilemma, typically having to wait until after silicon availability to perform power analysis with realistic software workloads. However, this is too late in the game, as it becomes… Read More


Instrumenting Post-Silicon Validation. Innovation in Verification

Instrumenting Post-Silicon Validation. Innovation in Verification
by Bernard Murphy on 07-28-2021 at 6:00 am

Instrumenting Post-Silicon Validation

Instrumenting post-silicon validation is not a new idea but here’s a twist. Using (pre-silicon) emulation to choose debug observation structures to instrument in-silicon. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO) and I continue our series on research… Read More


EDA in the Cloud – Now More Than Ever

EDA in the Cloud – Now More Than Ever
by Kalar Rajendiran on 07-27-2021 at 10:00 am

Screen Shot 2021 07 14 at 4.32.16 PM

A decade ago, many of us heard commentaries on how entrepreneurs were turned down by venture capitalists for not including a cloud strategy in their business plan, no matter what the core business was. Humorous punchlines such as, “It’s cloudy without any clouds” and “Add some cloud to your strategy and your future will be bright… Read More


Ansys Multiphysics Platform

Ansys Multiphysics Platform
by Tom Dillinger on 07-26-2021 at 10:00 am

platform communication

Background
Traditionally, the interface between chip designers and system power, packaging, reliability, and mechanical engineering teams was a relatively straightforward exchange of specifications.  Chip designers developed preliminary power dissipation estimates, often based on a simplifying power/mm**2 value. … Read More


A Custom Layout Environment for SOC Design Closure

A Custom Layout Environment for SOC Design Closure
by Tom Simon on 07-22-2021 at 10:00 am

custom layout environment

Throughout the process of physical design and verification there are many groups working on the design. Most often these groups are working independently or in parallel but separately, using their own specialized tools, such as P&R, DRC, custom layout, DFM, etc. At the end of the process there is an inevitable requirement… Read More


A Closer Look at Aging on Clock Networks

A Closer Look at Aging on Clock Networks
by Tom Simon on 07-20-2021 at 10:00 am

Transistor Aging

We all know that designers work hard to reach design closure on SOC designs. However, what gets less attention from consumers is the effort that goes into ensuring that these chips will be fully operational and meeting timing specs over their projected lifetime. Of course, this is less important for chips used in devices with projected… Read More


EDA Flows for 3D Die Integration

EDA Flows for 3D Die Integration
by Tom Dillinger on 07-20-2021 at 6:00 am

future integration

Background

The emergence of 2.5D heterogeneous die integration using a silicon (or organic) interposer has enabled unique system architectures.  The term “More than Moore” has been used to describe the circuit density and cost advantages of leveraging multiple die in the package, the die potentially in different process technologies. … Read More


Cadence Tensilica FloatingPoint DSPs

Cadence Tensilica FloatingPoint DSPs
by Kalar Rajendiran on 07-15-2021 at 10:00 am

Tensilica FP DSPs

Being engrossed in the digital information world, it is easy to forget that the real world is comprised of mostly analog signals and data. Digital Signal Processors (DSP) take digitized forms of these worldly signals and manipulate them mathematically. Although floating-point is a more relevant and accurate way of representing… Read More