Emulation Webinar SemiWiki
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HCL Webinar Series – HCL VersionVault Delivers Version Control and More

HCL Webinar Series – HCL VersionVault Delivers Version Control and More
by Mike Gianfagna on 08-06-2020 at 10:00 am

Screen Shot 2020 08 02 at 9.23.20 PM

HCL is an interesting organization. You may know them as an Indian company that provides software and hardware services.  At about $10B US and over 110,000 employees working around the world, they are indeed a force in the industry. They’ve also created a software company called HCL Software that develops tools and technologies… Read More


Structural CDC Analysis Signoff? Think Again.

Structural CDC Analysis Signoff? Think Again.
by Bernard Murphy on 08-05-2020 at 6:00 am

strainer min

Talking not so long ago to a friend from my Atrenta days, I learned that the great majority of design teams still run purely structural CDC analysis. You should sure asynchronous clock domains are suitably represented in the SDC, find all places where data crosses between those domains that require a synchronizer, gray-coded FIFO… Read More


Cadence on Automotive Safety: Without Security, There is no Safety

Cadence on Automotive Safety: Without Security, There is no Safety
by Mike Gianfagna on 08-04-2020 at 10:00 am

Attack vectors and EDA countermeasures

One of the Designer Track at this year’s DAC focused on the popular topic of automotive electronics.  The title was particularly on-point, The Modern Automobile: A Safety and Security “Hot Zone”. The session was chaired by Debdeep Mukhopadhyay, a Professor at the Indian Institute of Technology in Kharagpur.

This special, invited… Read More


Webinar – Designing and Verifying HBM ESD Protection Networks, August 11, 10AM PST

Webinar – Designing and Verifying HBM ESD Protection Networks, August 11, 10AM PST
by Tom Simon on 08-03-2020 at 10:00 am

Promo Ad 400x400 2

Every chip needs ESD protection, especially RF, analog and nm designs. Because each type of design has specific needs relating to IOs, pad rings, operating voltage, process, etc. it is important that the ESD protection network is carefully tailored to the design. Also because of interactions between the design and its ESD protection… Read More


Cooley’s 11 Quickie Questions About Virtual DAC’20 Last Week!

Cooley’s 11 Quickie Questions About Virtual DAC’20 Last Week!
by Daniel Nenni on 08-02-2020 at 8:00 am

John Cooley DeepChip.

Just a little funny history, after I started my Silicon Valley Blog in 2009 several EDA CEOs bullied me into creating my own site to compete with John Cooley’s DeepChip.com. Competition is good, right? One good friend and CEO even suggested I call it DeepNenni.com. Thankfully we came up with something a little less awkward,

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Synopsys Presents SAT-Sweeping Enhancements for Logic Synthesis

Synopsys Presents SAT-Sweeping Enhancements for Logic Synthesis
by Mike Gianfagna on 07-31-2020 at 10:00 am

Screen Shot 2020 07 25 at 2.05.14 PM

There was a “research reviewed” panel on Thursday at DAC entitled Shortening the Wires Between High-Level Synthesis and Logic Synthesis. Chaired by Alric Althoff of Tortuga Logic, the panel explored methods to deal with wire delays in high-level synthesis and logic synthesis. The four speakers and their focus were:

  • Licheng
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DAC Panel – Artificial Intelligence Comes to CAD: Where’s the Data?

DAC Panel – Artificial Intelligence Comes to CAD: Where’s the Data?
by Tom Simon on 07-30-2020 at 10:00 am

Which problems are ripe for AIML

Artificial Intelligence (AI) and Machine Learning (ML) are becoming more and more commonplace in our world. We have Siri, Alexa and Google Assistant that understand our voice commands. Vision systems that recognize objects are used for facial recognition, autonomous driving, medical, geographical and many other applications.… Read More


DAC Panel: Cadence Weighs in on AI for EDA, What Applications, Where’s the Data?

DAC Panel: Cadence Weighs in on AI for EDA, What Applications, Where’s the Data?
by Mike Gianfagna on 07-29-2020 at 6:00 am

Drivers of Convergence in Computational Software

DAC was full of great panels, research papers and chip design stories this year, the same as other years. Being a virtual show, there were some differences of course. I’ve heard attendance was way up, allowing a lot more folks to experience the technical program.  This is likely to be true for a virtual event. I’m sure we’ll see more… Read More


#57DAC – Panel Discussion of High Level Synthesis

#57DAC – Panel Discussion of High Level Synthesis
by Daniel Payne on 07-28-2020 at 10:00 am

sean dart, Cadence

Presenters took a trip down memory lane at DAC this year by having a panel discussion on HLS (High Level Synthesis) spanning from 1974 to 2020, and that time period aligns with when I first graduated from the University of Minnesota in 1978, starting chip design at Intel, then later transitioning into EDA companies by 1986. MarilynRead More


Low Power and RISC-V Talks at DAC2020, Hosted by Mentor

Low Power and RISC-V Talks at DAC2020, Hosted by Mentor
by Bernard Murphy on 07-28-2020 at 6:00 am

low battery

I’m going to get to low power and RISC-V, but first I’m trying out virtual DAC this year. Seems to be working smoothly, aside from some glitches in registration. But maybe that’s just me – I switched email addresses in the middle of the process. Some sessions are live, many pre-recorded, not quite the same interactive experience… Read More