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Nobody ever lost their job for spending too much on hardware verification, did they?

Nobody ever lost their job for spending too much on hardware verification, did they?
by Daniel Nenni on 06-25-2020 at 6:00 am

Silicon Bug Cost Scenario

A paper was published last month on the Acuerdo Consultancy Services website authored by Joe Convey of Acuerdo and Bryan Dickman of Valytic Consulting. Joe and Bryan spent combined decades in the Semi and EDA World which means they have a great understanding of hardware bugs first hand, absolutely.

Here is a quick summary… Read More


Why Go Custom in AI Accelerators, Revisited

Why Go Custom in AI Accelerators, Revisited
by Bernard Murphy on 06-24-2020 at 6:00 am

frame interpolation

I believe I asked this question a year or two ago and answered it for the absolute bleeding edge of datacenter performance – Google TPU and the like. Those hyperscalars (Google, Amazon, Microsoft, Baidu, Alibaba, etc) who want to do on-the-fly recognition in pictures so they can tag friends in photos, do almost real-time machine… Read More


How to Grow with Poise and Grace, a Tale of Scalability from ClioSoft

How to Grow with Poise and Grace, a Tale of Scalability from ClioSoft
by Mike Gianfagna on 06-23-2020 at 10:00 am

Screen Shot 2020 05 10 at 1.06.27 PM

ClioSoft published a white paper recently entitled Best Practices are the Foundations of a Startup. The piece discusses the needs and challenges associated with building a scalable infrastructure to support growth.

Before I get into more details on ClioSoft’s white paper, I would offer my own experience on this topic – the need… Read More


Design Technology Co-Optimization (DTCO) for sub-5nm Process Nodes

Design Technology Co-Optimization (DTCO) for sub-5nm Process Nodes
by Tom Dillinger on 06-23-2020 at 6:00 am

scaled metal resistance

Summary
Design Technology Co-Optimization (DTCO) analysis was pursued for library cell PPA estimates for gate-all-around (GAA) devices and new metallurgy options.  The cell design and process recommendations are a bit surprising.

Introduction
During the “golden years” of silicon technology evolution that applied Dennard… Read More


DVCon 2020 Virtual Follow-Up Conference!

DVCon 2020 Virtual Follow-Up Conference!
by Daniel Nenni on 06-19-2020 at 6:00 am

DVCon 2020 Logo SemiWiki

As most of you know DVCon 2020 was our first conference to be cut short by the Pandemic. SemiWiki bloggers Bernard Murphy, Mike Gianfagna, and I were there with full schedules but at the last minute it was called off. It really was an eerie feeling, the emptiness of it all.

The rest of our EDA live events followed suit and went virtual … Read More


The Moving Target Known as UPF

The Moving Target Known as UPF
by Tom Simon on 06-18-2020 at 10:00 am

UPF hierarchy

As if engineers did not have enough difficulty just getting everything right so that their designs are implemented functionally correct, the demands of lowering power consumption require changes that can affect functionality and verification. Techniques such as power gating, clock gating, mixed supply voltage, voltage … Read More


Cadence Adds “Always On” to vManager Verification Management with Distributed and Cloud Access

Cadence Adds “Always On” to vManager Verification Management with Distributed and Cloud Access
by Mike Gianfagna on 06-17-2020 at 10:00 am

Screen Shot 2020 06 15 at 11.32.15 AM

Cadence vManager™ Verification Management provides what the company describes as metric-driven signoff. Anyone who has been through the tapeout process for a complex SoC knows the perils of verification sign-off. How much of the chip has been verified?  What’s left to do? Will all be ready when the tapeout deadline arrives? … Read More


Fractal CEO Update 2020

Fractal CEO Update 2020
by Daniel Nenni on 06-16-2020 at 10:00 am

Fractal Technologies SemiWiki

Rene Donkers, the company’s Co-founder and CEO, started his EDA career at Sagantec where he became responsible for world wide customer support and operations management. Ten years ago, Rene and a handful of people noticed a need in the design community for a standardized (portable) IP Validation approach to replace internal… Read More


Webinar: Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff

Webinar: Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff
by Mike Gianfagna on 06-16-2020 at 6:00 am

Screen Shot 2020 06 15 at 6.59.34 PM

I had the opportunity to preview an upcoming webinar from Synopsys on SoC Glitch Power – what it is and how to reduce it. There is some eye-opening information in this webinar. Glitch power is a bigger problem than you may think and Synopsys has some excellent strategies to help reduce the problem. The webinar is available via replay… Read More


What’s At the Center of Your SoC Design Process?

What’s At the Center of Your SoC Design Process?
by Daniel Payne on 06-15-2020 at 10:00 am

IP SoC min

I love starting a new project from scratch, because there’s that optimistic feeling of having no constraints and being able to creatively express myself and get the job done right this time. For SoC designs today there are teams of engineers and maybe a program manager plus a marketing person that define the features, budget… Read More