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EDA

Electronic Design Automation

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Webinar – Why Keeping Track of IP in the Enterprise Really Matters

Webinar – Why Keeping Track of IP in the Enterprise Really Matters
by Mike Gianfagna on 08-30-2021 at 10:00 am
Categories: Cliosoft, EDA, Events

Webinar – Why Keeping Track of IP in the Enterprise Really Matters

Everyone knows IP is an important asset for the enterprise. You spend a lot of money on IP licenses. You try to keep track of who bought what as buying the same thing twice is painful. You wonder if you have the latest version of an IP, especially if it’s part of mission-critical functionality. If you’re a good corporate citizen, you … Read More

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NetApp’s ONTAP Enables Engineering Productivity Boost

NetApp’s ONTAP Enables Engineering Productivity Boost
by Kalar Rajendiran on 08-30-2021 at 6:00 am
Categories: EDA, NetApp

What if you could Table

One of the few things that remain constant in the engineering world is the desire for higher productivity. Innovation happens when engineers are designing something and creative ideas crop up when they are reviewing and analyzing the results. In between these fun steps, engineers have to deal with the necessary evil of creating… Read More

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Accelerating Exhaustive and Complete Verification of RISC-V Processors

Accelerating Exhaustive and Complete Verification of RISC-V Processors
by Ashish Darbari on 08-29-2021 at 6:00 am
Categories: Cadence, EDA

FIG 1 spec bug

As processor architecture and design development becomes completely liberated with open-source RISC-V instruction set architecture (ISA), the race to get RISC-V silicon in our hands has increased massively. We have no doubt that in next 5 years, we will see RISC-V based laptops and desktops in the market. But would these processors… Read More

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Side Channel Analysis at RTL. Innovation in Verification

Side Channel Analysis at RTL. Innovation in Verification
by Bernard Murphy on 08-26-2021 at 6:00 am
Categories: Cadence, EDA, Security

Innovation New

Roots of trust can’t prevent attacks through side-channels which monitor total power consumption or execution timing. Correcting weakness to such attacks requires pre-silicon vulnerability analysis. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO)… Read More

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Using Machine Learning to Improve EDA Tool Flow Results

Using Machine Learning to Improve EDA Tool Flow Results
by Daniel Payne on 08-25-2021 at 10:00 am
Categories: EDA, Synopsys

gajski kuhn

Back in 2020 I first learned from Synopsys about how they had engineered a better way to do optimize layouts on digital designs by using machine learning techniques, instead of relying upon manual approaches. The product was named DSO.ai, standing for Design Space Optimization, and it produced a more optimal floor-plan in less… Read More

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Expanding Intel’s Foundry Partnerships: A Critical Piece of IDM 2.0

Expanding Intel’s Foundry Partnerships: A Critical Piece of IDM 2.0
by Daniel Nenni on 08-25-2021 at 6:00 am
Categories: Foundries, Intel, Synopsys
8 Comments

Stuart Pann SemiWiki

One of the career Intel employees (33+ years) that Pat Gelsinger brought back is Stuart Pann. Stuart is now the Senior Vice President of the Intel Corporate Planning Group. He does not have direct foundry experience but he certainly knows Intel and Pat so it will be interesting to see where this goes.

Stuart recently penned an article… Read More

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Symmetry Requirements Becoming More Important and Challenging

Symmetry Requirements Becoming More Important and Challenging
by Tom Simon on 08-24-2021 at 10:00 am
Categories: EDA, Siemens EDA

Symmetry across the design flow

Humans certainly have always had an aesthetic preference for symmetry. We also see symmetry showing up frequently in nature. The importance of symmetry in electronic designs has been apparent for decades. There are a host of analog structures that require balanced layout. For instance, these include differential pairs and … Read More

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Cadence Tempus Update Promises to Transform Timing Signoff User Experience

Cadence Tempus Update Promises to Transform Timing Signoff User Experience
by Tom Simon on 08-23-2021 at 6:00 am
Categories: Cadence, EDA

Tempus With SmartHub for Timing Signoff

Cadence invests heavily in the development of their Tempus Timing Signoff Solution due to its importance in the SoC design flow. I recently had a discussion on the topic of the most recent Tempus update with Brandon Bautz, senior product management group director in the Digital & Signoff Group, and Hitendra Divecha, product… Read More

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Have STA and SPICE Run Out of Steam for Clock Analysis?

Have STA and SPICE Run Out of Steam for Clock Analysis?
by Tom Simon on 08-20-2021 at 6:00 am
Categories: Ansys, Inc., EDA
1 Comment

Ansys clock jitter analysis

At advanced nodes such as 7 and 5nm, timing closure and sign off are becoming much more difficult than before at 16nm. One area of chips that has increased in complexity dramatically and who’s correct operation is essential for silicon success is the clock tree. If the clock tree has excessive jitter, it will throw off every timing… Read More

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How Hyperscalers Are Changing the Ethernet Landscape

How Hyperscalers Are Changing the Ethernet Landscape
by Synopsys Editorial on 08-17-2021 at 6:00 am
Categories: EDA, Synopsys
1 Comment

How Hyperscalers Are Changing the Ethernet Landscape

It’s all about bandwidth these days – fueling hyperscale data centers that support high-performance and cloud computing applications. It’s what enables you to stream a movie on your smart TV while your roommate plays an online game with friends located in different parts of the country. It’s what makes big data analytics run swiftly… Read More