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EDA Appears to Have COVID Immunity – ESD Alliance Reports Strong Q2 2020

EDA Appears to Have COVID Immunity – ESD Alliance Reports Strong Q2 2020
by Daniel Nenni on 10-05-2020 at 10:00 am

EDA Appears to Have COVID Immunity – ESD Alliance Reports Strong Q2 2020

The ESD Alliance tracks revenue growth for a large number of EDA companies. Their recent report paints a positive picture in a landscape dotted with challenges and not-so-good news. The report cites 12.6% overall revenue growth for Q2 2020 vs. Q2 2019. Furthermore, the overall most recent four quarter revenue average has increased… Read More


CEO Interview: Dean Drako of IC Manage

CEO Interview: Dean Drako of IC Manage
by Daniel Nenni on 10-02-2020 at 6:00 am

Dean Drako CEO Interview SemiWiki 1

Dean founded IC Manage in 2003, a company that he has helped expand to become the IC/SoC design and IP management technology leader. Dean was also founder, President and CEO of Barracuda Networks from 2003 to 2012, where he built and expanded Barracuda from a spam and virus firewall provider to a broad line enterprise technology … Read More


Free Webinar on SPICE Simulation

Free Webinar on SPICE Simulation
by Tom Simon on 10-01-2020 at 10:00 am

SPICE Simulation

The world of SPICE simulators is one filled with compromises. Typically, it is possible to choose the highest accuracy and pay a performance and capacity penalty, or to choose high speed and capacity but give up accuracy in the process. Many semiconductor companies have been turning to Primarius Technologies to help escape these… Read More


SkillCAD Layout Automation Suite has Over 120 Commands Backed by 60 Customers

SkillCAD Layout Automation Suite has Over 120 Commands Backed by 60 Customers
by Tom Simon on 09-29-2020 at 10:00 am

SkillCAD Layout Automation Suite

Cadence Virtuoso is by far the most popular layout tool for IC design. This is especially true at advanced process nodes. In my opinion one of the key reasons for this is its built-in extension language, SKILL. SKILL is a powerful tool to add time saving and customized functionality to the Virtuoso layout editor. For analog and custom… Read More


Siemens PAVE360 Stepping Up to Digital Twins

Siemens PAVE360 Stepping Up to Digital Twins
by Bernard Murphy on 09-29-2020 at 6:00 am

Siemens PAVE360

The idea of a digital twin is simple enough. You use a digital model of a car, aircraft, whatever to test design ideas and prove your design will be robust across a wide range of scenarios before you commit millions of dollars and lives to proving out the real thing. As Siemens have accomplished in their PAVE360 platform. There are a … Read More


Altair HPC Virtual Summit 2020 – The Latest in Enterprise Computing

Altair HPC Virtual Summit 2020 – The Latest in Enterprise Computing
by Mike Gianfagna on 09-28-2020 at 10:00 am

Altair HPC Virtual Summit 2020 – The Latest in Enterprise Computing

On September 9 and 10 Altair held their high-performance computing virtual summit. Altair is a company with a large footprint. In their own words, “Altair is a global technology company that provides software and cloud solutions in the areas of data analytics, product development, and high-performance computing (HPC).” Their… Read More


Webinar: Static Verification for RISC-V Cores and SoCs

Webinar: Static Verification for RISC-V Cores and SoCs
by Daniel Nenni on 09-28-2020 at 6:00 am

Aldec RISC V Webinar SemiWiki 1

RISC-V has been trending ever since it landed on SemiWiki in 2016.  Even more so now that Arm is in flux with the Nvidia acquisition. Verification is a fast growing EDA challenge with the number of verification engineers steadily outpacing design, so this webinar is a best case scenario for SemiWiki traffic, absolutely.

Two thingsRead More


Don’t You Forget About “e”

Don’t You Forget About “e”
by Daniel Nenni on 09-25-2020 at 10:00 am

e Flow Vert

I imagine that the title of this post will remind many of 80s synth-pop, or perhaps the movie The Breakfast Club. But my topic is the venerable hardware verification language (HVL) known simply as e. It has quite an interesting history and it played a key role in the development of the modern testbench methodology that most chip verification… Read More


Synopsys talks about their DesignWare USB4 PHY at TSMC’s OIP

Synopsys talks about their DesignWare USB4 PHY at TSMC’s OIP
by Tom Simon on 09-25-2020 at 6:00 am

USB4 operating modes

When USB initially came out it revolutionized how peripherals connect to host systems. We all remember when Apple did away with many separate connections for mouse, keyboard, audio and more with their first computers supporting USB. USB has continued to develop more flexibility and more throughput. In 2015 Apple again introduced… Read More


112G/56G SerDes – Select the Right PAM4 SerDes for Your Application

112G/56G SerDes – Select the Right PAM4 SerDes for Your Application
by Mike Gianfagna on 09-24-2020 at 10:00 am

112G56G SerDes Select the right PAM4 SerDes for your application

This is another installment covering TSMC’s very popular Open Innovation Platform event (OIP), held on August 25. This event presents a diverse and high-impact series of presentations describing how TSMC’s vast ecosystem collaborates with each other and with TSMC. Not all SerDes are the same. The presentation covered here,… Read More