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CXL Verification. A Siemens EDA Perspective

CXL Verification. A Siemens EDA Perspective
by Bernard Murphy on 07-07-2022 at 6:00 am

CXL Verification

Amid the alphabet soup of inter-die/chip coherent access protocols, CXL is gaining a lot of traction. Originally proposed by Intel for cross-board and cross-backplane connectivity to accelerators of various types (GPU, AI, warm storage, etc.), a who’s who of systems and chip companies now sits on the board, joined by an equally… Read More


What Quantum Means for Electronic Design Automation

What Quantum Means for Electronic Design Automation
by Kelly Damalou and Kostas Nikellis on 07-06-2022 at 10:00 am

Ansys quantum blog Image1

In 1982, Richard Feynman, a theoretical physicist and Nobel Prize winner, proposed the initial quantum computer; Feynman’s quantum computer would have the capacity to facilitate traditional algorithms and quantum circuits with the goal of simulating quantum behavior as it would have occurred in nature. The systems Feynman… Read More


Multi-FPGA Prototyping Software – Never Enough of a Good Thing

Multi-FPGA Prototyping Software – Never Enough of a Good Thing
by Daniel Nenni on 07-06-2022 at 8:00 am

PlayerPro EN

Building a multi-FPGA prototype for SoC verification is complex with many interdependent parts – and is “always on a clock”.  The best multi-FPGA prototype implementation is worthless if its not up and running early in the SoC design cycle, where it offers the highest verification ROI terms of minimizing the cost of bug fixes … Read More


Jade Design Automation’s Register Management Tool

Jade Design Automation’s Register Management Tool
by Kalar Rajendiran on 07-05-2022 at 10:00 am

RegMan supervisor CSRs

When more than one person is working on any project, coordination is imperative. When the team size grows, being in sync becomes essential. When it comes to SoC design management, registers and bit fields are used to communicate status of results and execute conditional controls. The Register Management function plays an essential… Read More


Using AI in EDA for Multidisciplinary Design Analysis and Optimization

Using AI in EDA for Multidisciplinary Design Analysis and Optimization
by Daniel Payne on 07-04-2022 at 10:00 am

Optimality min

Most IC and system engineers follow a familiar process when designing a new product: create a model, use parameters for the model, simulate the model, observe the results, compare results versus requirements, change the parameters or model and repeat until satisfied or it’s time to tape out. On the EDA side, most tools perform… Read More


The Lines Are Blurring Between System and Silicon. You’re Not Ready.

The Lines Are Blurring Between System and Silicon. You’re Not Ready.
by Daniel Nenni on 07-01-2022 at 8:00 am

3D Memory HBM Ansys

3D-ICs bring together multiple silicon dies into a single package that’s significantly larger and complex than traditional systems on a chip (SoCs). There’s no doubt these innovative designs are revolutionizing the semiconductor industry.

3D-ICs offer a variety of performance advantages over traditional SoCs. Because … Read More


Cadence Execs Look to the Future

Cadence Execs Look to the Future
by Dave Bursky on 07-01-2022 at 6:00 am

CDNLive 2020

Everything is becoming digital, and everything digital requires semiconductors. Cadence’s President and CEO, Dr. Anirudh Devgan, highlighted this at the recent CadenceLIVE user conference and discussed many of the company’s accomplishments and future directions. Dr. Devgan also sees the emergence of data—especially … Read More


Using IP-XACT, RTL and UPF for Efficient SoC Design

Using IP-XACT, RTL and UPF for Efficient SoC Design
by Daniel Payne on 06-30-2022 at 6:00 am

ESDA Revenue

The ESD Alliance collects and reports every quarter the revenue trends for both EDA and Semiconductor IP (SiP), and the biggest component for the past few years has been the SiP, as IP re-use dominates new designs. For Q4 of 2021 the total SiP revenue was $1,314.3 Million, enjoying a 24.8% growth in just one year. Here’s a chart… Read More


Using an IDE to Accelerate Hardware Language Learning

Using an IDE to Accelerate Hardware Language Learning
by Daniel Nenni on 06-29-2022 at 10:00 am

Indian Institute of Technology IIT Bhubaneswar

Recently, in one of my regular check-ins with AMIQ EDA, I was pleased that they linked me up with an active customer. The resulting post summarized my discussion with three engineers from Kepler Communications Inc. They talked about using one of the AMIQ EDA products in the design of FPGAs for space-borne Internet connectivity.… Read More


Stalling to Uncover Timing Bugs. Innovation in Verification

Stalling to Uncover Timing Bugs. Innovation in Verification
by Bernard Murphy on 06-29-2022 at 6:00 am

Innovation New

Artificially stalling datapaths and virtual channels is a creative method to uncover corner case timing bugs. A paper from Nvidia describes a refinement to this technique. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue… Read More