2024 DVCon was very busy this year. Bernard Murphy and I were in attendance for SemiWiki, he has already written about it. Multi die and chiplets was again a popular topic. Lauro Rizzatti, a consultant specializing in hardware-assisted verification, moderated an engaging panel, sponsored by Synopsys, focusing on the intricacies… Read More
Electronic Design Automation
2024 Outlook with John Lee, VP and GM Electronics, Semiconductor and Optics Business Unit at Ansys
We have been working with Ansys since SemiWiki was founded in 2011. It has been a richly rewarding relationship in all regards. I always say the semiconductor industry is filled with the most intelligent people in the world and Ansys is an excellent proof point. I have known John Lee for 30+ years and he is one of my trusted few, absolutely.… Read More
QuantumPro unifies superconducting qubit design workflow
To create quantum computing chips today, a typical designer must cobble various tools together, switching back and forth between them for different tasks. By contrast, EDA solutions such as Keysight Advanced Design System (ADS) unify a design workflow in a single interface with automated data exchange between features. In … Read More
Challenge and Response Automotive Keynote at DVCon
Keynotes commonly provide a one-sided perspective of a domain, either customer-centric or supplier-centric. Kudos therefore to Cadence’s Paul Cunningham for breaking the mold in offering the first half of his keynote to Anthony Hill, a TI fellow, to talk about outstanding challenges he sees in verification for automotive … Read More
Unleash the Power: NVIDIA GPUs, Ansys Simulation
In the realm of engineering simulations, the demand for faster, more accurate solutions to complex multiphysics challenges is ever-growing.
Simulation is a vital tool for engineers to design, test, and optimize complex systems and products. It helps engineers reduce costs, improve quality, and accelerate innovation. However,… Read More
Synopsys Enhances PPA with Backside Routing
Complexity and density conspire to make power delivery very difficult for advanced SoCs. Signal integrity, power integrity, reliability and heat can seem to present unsolvable problems when it comes to efficient power management. There is just not enough room to get it all done with the routing layers available on the top side… Read More
Afraid of mesh-based clock topologies? You should be
Digital logic chips synchronize all logic operations by using a clock signal connected to flip-flops or latches, and the clock is distributed across the entire chip. The ultimate goal is to have a clock signal that arrives at the exact same moment in time at all clocked elements. If the clock arrives too early or too late from the PLL… Read More
Checking and Fixing Antenna Effects in IC Layouts
IC layouts go through extensive design rule checking to ensure correctness, before being accepted for fabrication at a foundry or IDM. There’s something called the antenna effect that happens during chip manufacturing where plasma-induced damage (PID) can lower the reliability of MOSFET devices. Layout designers run Design… Read More
Automotive Electronics Trends are Shaping System Design Constraints
Something is brewing in automotive electronics. Within a one-month window most of the product announcements and pitches to which I am being invited are on automotive topics. Automotive markets have long been one of the primary targets for suppliers to system designers, but this level of alignment in announcements seems more … Read More
2024 Outlook with Jim Cantele of Altair
Jim Cantele, global SVP of sales and technology at Altair, is an electronics industry veteran with deep knowledge of EDA software and services. Before joining Altair during the acquisition of Runtime Design Automation in 2017, Jim held executive-level management positions at a number of leading EDA and semiconductor companies,… Read More
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