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Signal Integrity Basics

Signal Integrity Basics
by Daniel Payne on 11-12-2024 at 10:00 am

Digital and analog waveforms

PCB and package designers need to be concerned with Signal Integrity (SI) issues to deliver electronic systems that work reliably in the field. EDA vendors like Siemens have helped engineers with SI analysis using a simulator called HyperLynx, dating all the way back to 1992. Siemens even wrote a 56-page e-book recently, SignalRead More


Changing RISC-V Verification Requirements, Standardization, Infrastructure

Changing RISC-V Verification Requirements, Standardization, Infrastructure
by Daniel Nenni on 11-07-2024 at 10:00 am

Abstract,Futuristic,Infographic,With,Visual,Data,Complexity,,,Represent,Big

A lively panel discussion about RISC-V and open-source functional verification highlighted this year’s Design Automation Conference. Part One looked at selecting a RISC-V IP block from a third-party vendor and investigating its functional verification process.

In Part Two, moderator Ron Wilson and Contributing Editor … Read More


New Product for In-System Test

New Product for In-System Test
by Daniel Payne on 11-05-2024 at 8:00 am

Failure rates over time

The annual ITC event is happening this week in San Diego as semiconductor test professionals gather from around the world to discuss their emerging challenges and new approaches, so last week I had the opportunity to get an advance look at something new from Siemens named Tessent In-System Test software. Jeff Mayer, Product Manager,… Read More


An Illuminating Real Number Modeling Example in Functional Verification

An Illuminating Real Number Modeling Example in Functional Verification
by Bernard Murphy on 11-05-2024 at 6:00 am

Data stream sine waves 1s and 0s orange Getty 496123972 EXT min

I just read an interesting white paper on functional verification of analog blocks using SV-RNM (SystemVerilog real number modeling). The content is worth the effort to read closely as it elaborates a functional verification flow for RNM matching expectations for digital logic verification, from randomization to functional… Read More


How to Update Your FPGA Devices with Questa

How to Update Your FPGA Devices with Questa
by Mike Gianfagna on 10-29-2024 at 6:00 am

How to Update Your FPGA Devices with Questa

It’s a fact of life that technology marches on. Older process nodes get replaced by newer ones. As a result, ASSPs and FPGAs are obsoleted, leaving behind large system design investments that need to re-done. Since many of these obsolete designs are performing well in the target application, this re-do task can be particularly … Read More


The RISC-V and Open-Source Functional Verification Challenge

The RISC-V and Open-Source Functional Verification Challenge
by Daniel Nenni on 10-24-2024 at 10:00 am

Semiwiki Blog Post #1 Image #1

Most of the RISC-V action at the end of June was at the RISC-V Summit Europe, but not all. In fact, a group of well-informed and opinionated experts took over the Pavilion stage at the Design Automation Conference to discuss functional verification challenges for RISC-V and open-source IP.

Technology Journalist Ron Wilson and … Read More


Prioritize Short Isolation for Faster SoC Verification

Prioritize Short Isolation for Faster SoC Verification
by Ritu Walia on 10-17-2024 at 10:00 am

Fig1 shorts analysis conf data

Improve productivity by shifting left LVS
In modern semiconductor design, technology nodes continue to shrink and the complexity and size of circuits increase, making layout versus schematic (LVS) verification more challenging. One of the most critical errors designers encounter during LVS runs are shorted nets. Identifying… Read More


Navigating Resistance Extraction for the Unconventional Shapes of Modern IC Designs

Navigating Resistance Extraction for the Unconventional Shapes of Modern IC Designs
by Nada Tarek on 10-15-2024 at 6:00 am

Fig1 MEMS design

The semiconductor industry is experiencing rapid evolution, driven by the proliferation of IoT applications, image sensors, photonics, MEMS applications, 3DIC and other emerging technologies. This growth has dramatically increased the complexity of integrated circuit (IC) design. One aspect of this complexity is the … Read More


SystemVerilog Functional Coverage for Real Datatypes

SystemVerilog Functional Coverage for Real Datatypes
by Mariam Maurice on 10-03-2024 at 6:00 am

fig 1

Functional coverage acts as a guide to direct verification resources by identifying the tested and untested portions of a design. Functional coverage is a user-defined metric that assesses the extent to which the design specification, as listed by the test plan’s features, has been used. It can be used to estimate the presence… Read More


Automating Reset Domain Crossing (RDC) Verification with Advanced Data Analytics

Automating Reset Domain Crossing (RDC) Verification with Advanced Data Analytics
by Kalar Rajendiran on 09-26-2024 at 10:00 am

RDC Verification using Data Analysis Techniques

The complexity of System-on-Chip (SoC) designs continues to rise at an accelerated rate, with design complexity doubling approximately every two years. This increasing complexity makes verification a more difficult and time-consuming task for design engineers. Among the key verification challenges is managing reset domain… Read More