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3D IC – Managing the System-level Netlist

3D IC – Managing the System-level Netlist
by Daniel Payne on 09-27-2022 at 10:00 am

2.5D IC min

I just did a Google search for “3D IC”, and was stunned to see it return a whopping 476,000 results. This topic is trending, because more companies are using advanced IC packaging to meet their requirements, and yet the engineers doing the 3D IC design have new challenges to overcome. One of those challenges is creating… Read More


Three Ways to Meet Manufacturing Rules in Advanced Package Designs

Three Ways to Meet Manufacturing Rules in Advanced Package Designs
by Kendall Hiles on 09-15-2022 at 10:00 am

1

Often designers are amazed at the diversity of requirements fabricators and manufacturers have for metal filled areas in advanced package designs. Package fabricators and manufacturers do not like solid metal planes or large metal areas. Their strict metal fill requirements address two main issues. The dielectric and metal… Read More


Machine Learning in the Fab at #59DAC

Machine Learning in the Fab at #59DAC
by Daniel Payne on 09-14-2022 at 8:00 am

Virtual Metrology min

It used to be true that a foundry or fab would create a set of DRC files, provide them to designers, and then the process yield would be acceptable, however if the foundry knows more details about the physical implementation of IC designs then they can improve the yield. Using a digital twin of the design, process and metrology steps… Read More


Connecting SystemC to SystemVerilog

Connecting SystemC to SystemVerilog
by Bernard Murphy on 09-13-2022 at 6:00 am

UVM Connect

Siemens EDA is clearly on a mission to help verifiers get more out of their tools and methodologies. Recently they published a white paper on UVM polymorphism. Now they have followed with a paper on using UVM Connect, re-introducing how to connect between SystemC and SystemVerilog. I’m often mystified by seemingly overlapping… Read More


Today’s SoC Design Verification and Validation Require Three Types of Hardware-Assisted Engines

Today’s SoC Design Verification and Validation Require Three Types of Hardware-Assisted Engines
by Daniel Nenni on 09-06-2022 at 6:00 am

IC Chip Low angle light emitting 600x600

Lauro Rizzatti offers Semiwiki readers a two-part series on why three kinds of hardware-assisted verification engines are now a must have for semiconductor designs continues today. His interview below with Juergen Jaeger, Prototyping Product Strategy Director in the Scalable Verification Solution division at Siemens EDA,… Read More


Resilient Supply Chains a Must for Electronic Systems

Resilient Supply Chains a Must for Electronic Systems
by Dave Bursky on 09-01-2022 at 10:00 am

three phase approach to supply chain resilence

The last few years have seen multiple disruptions in the supply chain in many industries. One of the key technologies that many fingers have pointed to is the semiconductor technology.  As products in all industries become more electronics based, semiconductors play a key role since no end system could function today without … Read More


Five Key Workflows For 3D IC Packaging Success

Five Key Workflows For 3D IC Packaging Success
by Kalar Rajendiran on 08-31-2022 at 6:00 am

3D IC design workflows

An earlier blog started with the topic of delivering 3D IC innovations faster. The blog covered the following foundational enablers for successful heterogeneous 3D IC implementation.

  • System Co-Optimization (STCO) approach
  • Transition from design-based to systems-based optimization
  • Expanding the supply chain and tool
Read More

IC Layout Symmetry Challenges

IC Layout Symmetry Challenges
by Daniel Payne on 08-29-2022 at 10:00 am

1D symmetry

Many types of designs, including analog designs, MEMs, and image sensors, require electrically matched configurations. This symmetry has a huge impact on the robustness of the design across process variations, and its performance. Having an electrically matched layout basically means having a symmetric layout. To check … Read More


Verifying 10+ Billion-Gate Designs Requires Distinct, Scalable Hardware Emulation Architecture

Verifying 10+ Billion-Gate Designs Requires Distinct, Scalable Hardware Emulation Architecture
by Daniel Nenni on 08-29-2022 at 6:00 am

960 x 540 Veloce

In a two-part series, Lauro Rizzatti examines why three kinds of hardware-assisted verification engines are a must have for today’s semiconductor designs. To do so, he interviewed Siemens EDA’s Vijay Chobisa and Juergen Jaeger to learn more about the Veloce hardware-assisted verification systems.

What follows is part one,… Read More


UVM Polymorphism is Your Friend

UVM Polymorphism is Your Friend
by Bernard Murphy on 08-17-2022 at 6:00 am

Polymorphism min

Rich Edelman of Siemens EDA recently released a paper on this topic. I’ve known Rich since our days together back in National Semi. And I’ve always been impressed by his ability to make a complex topic more understandable to us lesser mortals. He tackles a tough one in this paper – a complex concept (polymorphism) in a complex domain… Read More