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Can Correlation Between Simulation and Measurement be Achieved for Advanced Designs?

Can Correlation Between Simulation and Measurement be Achieved for Advanced Designs?
by Mike Gianfagna on 03-18-2024 at 6:00 am

Can Correlation Between Simulation and Measurement be Achieved for Advanced Designs?

“What you simulate is what you get.” This is the holy grail of many forms of system design. Achieving a high level of accuracy between predicted and actual performance can cut design time way down, resulting in better cost margins, time to market and overall success rates. Achieving a high degree of confidence in predicted performance… Read More


CEO Interview: Patrick T. Bowen of Neurophos

CEO Interview: Patrick T. Bowen of Neurophos
by Daniel Nenni on 03-15-2024 at 6:00 am

Patrick T. Bowen

Patrick is an entrepreneur with a background in physics and metamaterials. Patrick sets the vision for the future of the Neurophos architecture and directs his team in research and development, particularly in metamaterials design. He has a Master’s degree in Micro-Nano systems from ETH Zurich and PhD in Electrical Engineering… Read More


No! TSMC does not Make 90% of Advanced Silicon

No! TSMC does not Make 90% of Advanced Silicon
by Scotten Jones on 03-11-2024 at 2:00 pm

Slide1

Throughout the debate on fab incentives and the Chips Act I keep seeing comments like; TSMC makes >90% of all advanced silicon, or sometimes Taiwan make >90% of all advanced silicon. This kind of ill-defined and grossly inaccurate statement drives me crazy. I just saw someone make that same claim in the SemiWiki forums and… Read More


How Sarcina Technology Makes Advanced Semiconductor Package Design Easier

How Sarcina Technology Makes Advanced Semiconductor Package Design Easier
by Mike Gianfagna on 03-11-2024 at 6:00 am

How Sarcina Technology Makes Advanced Semiconductor Package Design Easier

For a long time, package engineering was part of the cleanup crew for chip design. The glory was all around the design of advance monolithic chips on the latest technology node. Once the design was done, the package/test team would take the design over the finish line, adding the required I/O specs, lead frame, load board and test … Read More


SPIE Let there be Light! High NA Kickoff! Samsung Slows? “Rapid” Decline?

SPIE Let there be Light! High NA Kickoff! Samsung Slows? “Rapid” Decline?
by Robert Maire on 03-03-2024 at 6:00 am

High NA EUV 2024

– High NA EUV’s coming out party – “Dawn” of the Angstrom Era
– Well attended, positive vibes, not much new but good progress
– Concerns about Samsung slowing spend while Intel accelerates
– KLA reticle inspection quandary – Risky business in China

SPIE was a High-NA
Read More

CEO Interview: Larry Zu of Sarcina Technology

CEO Interview: Larry Zu of Sarcina Technology
by Daniel Nenni on 03-01-2024 at 6:00 am

Larry Zu Photo 091516

Larry has grown Sarcina from designing semiconductor packages for a few small companies, to doing package designs for top semiconductor companies around the world. From 2014 to 2018, Larry led the expansion of Sarcina beyond package design into final test and wafer sort hardware and software development.

Larry is a semiconductor… Read More


WEBINAR: Chipmakers can leverage generative AI to speed up RTL design and verification

WEBINAR: Chipmakers can leverage generative AI to speed up RTL design and verification
by Daniel Nenni on 02-29-2024 at 2:00 pm

planorama blog ai

The subjects of Generative AI and Large Language Models (LLMs) permeate businesses and the public conversation.  It’s not without good reason!  While this emergent field of AI develops, it is now seen at a minimum as a valuable assistant, or, often, a dramatic accelerant to productivity, even to technical workflows.

As we’re … Read More


BDD-Based Formal for Floating Point. Innovation in Verification

BDD-Based Formal for Floating Point. Innovation in Verification
by Bernard Murphy on 02-27-2024 at 6:00 am

Innovation New

A different approach to formally verifying very challenging datapath functions. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome. We’re planning to add a wrinkle… Read More


A Candid Chat with Sean Redmond About ChipStart in the UK

A Candid Chat with Sean Redmond About ChipStart in the UK
by Daniel Nenni on 02-23-2024 at 6:00 am

Chip Start UK

When I first saw the Silicon Catalyst business plan 10 years ago I had very high hopes. Silicon Valley design starts were falling and Venture Capital Firms were distracted by software companies even though without silicon there would be no software.

Silicon Catalyst is an organization focused on accelerating silicon-based startups.… Read More


AMAT – Flattish QTR Flattish Guide – Improving 2024 – Memory and Logic up, ICAPs Down

AMAT – Flattish QTR Flattish Guide – Improving 2024 – Memory and Logic up, ICAPs Down
by Robert Maire on 02-19-2024 at 10:00 am

HBM SIP

– AMAT slightly better than expected, flat & guides flat but > expected
– Expects better 2024- Systems flat, service up, display down
– China risk remains high at 45%- $200M Sculpta expected in 2024
– HBM 5% of industry but not a lot of tool sales- but high growth

Still bumping along with flattish Read More