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WP_Term Object
(
    [term_id] => 386
    [name] => Semiconductor Services
    [slug] => semiconductor-services
    [term_group] => 0
    [term_taxonomy_id] => 386
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 639
    [filter] => raw
    [cat_ID] => 386
    [category_count] => 639
    [category_description] => 
    [cat_name] => Semiconductor Services
    [category_nicename] => semiconductor-services
    [category_parent] => 0
    [is_post] => 
)

ISS 2021 – Scotten W. Jones – Logic Leadership in the PPAC era

ISS 2021 – Scotten W. Jones – Logic Leadership in the PPAC era
by Scotten Jones on 01-15-2021 at 6:00 am

Slide3

I was asked to give a talk at the 2021 ISS conference and the following is a write up of the talk.

The title of the talk is “Logic Leadership in the PPAC era”.

The talk is broken up into three main sections:

  1. Background information explaining PPAC and Standard Cells.
  2. A node-by-node comparisons of companies running leading edge logic
Read More

2020 was a Mess for Intel

2020 was a Mess for Intel
by Robert Maire on 01-13-2021 at 10:00 am

Intel 2020 Mess

Understanding Intel’s future means understanding Intel’s past

Yes, there are two paths you can go by, but in the long run. There’s still time to change the road you’re on.

Intel is at a crossroad. The road they have been on since inception, and the road that has differentiated them from the rest of the pack… Read More


ESD Alliance Report for Q3 2020 Presents an Upbeat Snapshot That is Up and to the Right

ESD Alliance Report for Q3 2020 Presents an Upbeat Snapshot That is Up and to the Right
by Mike Gianfagna on 01-12-2021 at 10:00 am

ESD Alliance Report for Q3 2020 Presents an Upbeat Snapshot That is Up and to the Right

The Electronic System Design (ESD) Alliance (a SEMI Technology Community) recently released their regular report on EDA revenue for Q3, 2020 . While the report is a normal occurrence, the numbers in this particular report are anything but normal. I have been reviewing these reports for many years, and I honestly can’t remember… Read More


Webinar: Rescale is Providing an On-Ramp to the Hybrid Cloud for Chip Design

Webinar: Rescale is Providing an On-Ramp to the Hybrid Cloud for Chip Design
by Mike Gianfagna on 01-11-2021 at 6:00 am

Webinar Rescale is Providing an On Ramp to the Hybrid Cloud for Chip Design

We all know that design complexity is increasing at a fast pace. There’s always more analysis to run on larger and larger volumes of data. During tapeout, these demands can grow by an order of magnitude. Successful design projects need to add huge amounts of CPU, memory and storage for short bursts of time during tapeout to meet their… Read More


IEDM 2020 – Imec Plenary talk

IEDM 2020 – Imec Plenary talk
by Scotten Jones on 01-08-2021 at 6:00 am

Imec Figure 1

On Monday morning at IEDM, Sri Samavedam of Imec opened the technical program with a plenary talk entitled “Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips”. I am not generally a fan of plenary talks, I think the presenters often try to cover too much in their talks and end up not providing enough detail to be… Read More


Managing custom silicon projects with trans national, multi company, and cross functional teams

Managing custom silicon projects with trans national, multi company, and cross functional teams
by Raul Perez on 12-30-2020 at 10:00 am

iStock 1169660398

Probably the least appreciated and most critical thing I spend my time on when driving custom silicon projects is setting up the entire framework to get everyone talking and in rhythm with each other. Only supplier selection is more critical to the project’s success than this.

All system custom silicon projects where theRead More


ESL Expertise when You Need It. Spinning Up Faster

ESL Expertise when You Need It. Spinning Up Faster
by Bernard Murphy on 12-30-2020 at 6:00 am

CircuitSutra min

System-level expertise, once the domain a few architecture specialists, is now shouldering its way everywhere into chip design and verification. In virtual modeling together with OS and application software certainly. That now couples into mixed-level system-verification, using different levels of abstraction for different… Read More


NetApp’s FlexGroup Volumes – A Game Changer for EDA Workflows

NetApp’s FlexGroup Volumes – A Game Changer for EDA Workflows
by Mike Gianfagna on 12-23-2020 at 10:00 am

NetApps FlexGroup Volumes – A Game Changer for EDA Workflows

In my prior post on NetApp, I discussed how the company’s FlexCache technology can keep distributed design teams in sync. Coordination and collaboration are critical elements of any complex design project. The ability to deliver results quickly while managing the massive amounts of data is also a critical element of success.… Read More


SMIC Blacklist puts ASML in Jam

SMIC Blacklist puts ASML in Jam
by Robert Maire on 12-20-2020 at 6:00 am

SMIC Blacklisted US

US BIS confirms our prediction of “blacklisting” SMIC
SMIC embargoed from 10NM or better technology
Likely related to ASML pressure & WH scorched earth

Not just the stock

We had received a lot of feedback on our Nov 30th note regarding blacklisting of SMIC suggesting that we were wrong and the only thing blacklisted… Read More


Silicon Catalyst’s Semi Industry Forum – All-Star Cast Didn’t Disappoint

Silicon Catalyst’s Semi Industry Forum – All-Star Cast Didn’t Disappoint
by Mike Gianfagna on 12-18-2020 at 10:00 am

Silicon Catalysts Semi Industry Forum – All Star Cast Didnt Disappoint

A few weeks ago I wrote about an upcoming event Silicon Catalyst was hosting, the Semiconductor Industry Forum – A View to the Future. I mentioned a high-profile group of presenters: Don Clark, Contributing Journalist, New York Times as moderator;  Mark Edelstone, Chairman of Global Semiconductor Investment Banking, Morgan… Read More