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Mars Perseverance Rover Features First Zoom Lens in Deep Space

Mars Perseverance Rover Features First Zoom Lens in Deep Space
by Synopsys Editorial on 05-09-2021 at 10:00 am

Mars Perseverance Rover Features First Zoom Lens in Deep Space

On July 30, 2020, NASA launched the Mars 2020 Perseverance rover, which is scheduled to land today. Perseverance has been deployed to Mars with a new mission: to search for evidence of past life and collect samples that will eventually be brought back to Earth by future missions.

Mars 2020 Perseverance rendering courtesy of NASA/JPL-Caltech
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Verification Management the Synopsys Way

Verification Management the Synopsys Way
by Bernard Murphy on 05-06-2021 at 6:00 am

Verification management min

Remember the days when verification meant running a simulator with directed tests? (Back then we just called them tests.) Then came static and formal verification, simulation running in farms, emulation and FPGA prototyping. We now have UVM, constrained random testing and many different test objectives (functional, power,… Read More


Synopsys Debuts Major New Analog Simulation Capabilities

Synopsys Debuts Major New Analog Simulation Capabilities
by Tom Simon on 05-03-2021 at 10:00 am

Synopsys analog simulation

Just prior to this year’s Synopsys User Group (SNUG) meeting, I had a call with Hany Elhak, Group Director of Product Management and Marketing at Synopsys, to talk about their latest announcements for analog simulation. Synopsys usually has big things to talk about each year around this time – this year is no exception. Hany… Read More


Accelerating Cache Coherence Verification

Accelerating Cache Coherence Verification
by Bernard Murphy on 04-29-2021 at 6:00 am

Cache coherence checking min

It would be nice if there were a pre-packaged set of assertions which could formally check all aspects of cache coherence in an SoC. In fact, formal checks do a very nice job for the control aspects of a coherent network. But that covers only one part of the cache coherence verification task. Dataflow checks are just as important, where… Read More


Addressing SoC Test Implementation Time and Costs

Addressing SoC Test Implementation Time and Costs
by Daniel Payne on 04-20-2021 at 10:00 am

testmax flow

In business we all have heard the maxim, “Time is Money.” I learned this lesson early on in my semiconductor career when doing DRAM design, discovering that the packaging costs and time on the tester were actually higher than the fabrication costs. System companies like IBM were early adopters of Design For Test (DFT)… Read More


Your Car Is a Smartphone on Wheels—and It Needs Smartphone Security

Your Car Is a Smartphone on Wheels—and It Needs Smartphone Security
by Taylor Armerding on 04-18-2021 at 10:00 am

Your Car Is a Smartphone on Wheels—and It Needs Smartphone Security

Your modern car is a computer on wheels—potentially hundreds of computers on a set of wheels. Heck, even the wheels are infested with computers—what do you think prompts that little light on your dashboard to come on if your tire pressure is low? And computers don’t just run your infotainment system, backup camera, dashboard warning

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Global Variation and Its Impact on Time-to-Market for Designs

Global Variation and Its Impact on Time-to-Market for Designs
by umangdoshi on 04-14-2021 at 2:00 pm

Impact of Global Variation on Delay

We have come a long way from the days of limited and manageable characterization databases with fewer views and smaller library sizes. The technologies we are headed towards pushing characterization to its limits with special modeling for variation, aging and reliability all on a single process, voltage and temperature (PVT).… Read More


VC Formal SIG Virtually Conferences in Europe

VC Formal SIG Virtually Conferences in Europe
by Bernard Murphy on 04-06-2021 at 6:00 am

VC Formal graphic min

Pratik Mahajan, Synopsys VC Formal R&D Group Director, kicked off an absorbing event featuring talks from multiple customers in Europe. He spent some time on formal signoff, an important topic that I’m still not sure is fully understood. Answering the questions “OK, we did a bunch of formal checking but how does that affect… Read More


Key Requirements for Effective SoC Verification Management

Key Requirements for Effective SoC Verification Management
by Kirankumar Karanam on 02-25-2021 at 6:00 am

The Four Phases of SoC Verification

Effective and efficient functional verification is one of the biggest hurdles for today’s large and complex system-on-chip (SoC) designs. The goal is to verify as close as possible to 100% of the design’s specified functionality before committing to the long and expensive tape-out process for application-specific integrated… Read More


Techniques and Tools for Accelerating Low Power Design Simulations

Techniques and Tools for Accelerating Low Power Design Simulations
by Kalar Rajendiran on 02-17-2021 at 10:00 am

Figure 1 for Synopsys Blog

I recently watched a webinar titled “How to accelerate power-aware simulation debug with Synopsys’ VC LP” that was presented by Ashwani Kumar Dwivedi senior applications engineer at Synopsys. Watching the webinar made me reminisce how design verification has evolved over the years. A long time ago, static verification started… Read More