Name: Seminar: Domain-Specific Processor Design using ASIP Designer
Start: 2019-12-09T12:30:00-08:00
End: 2019-12-09T17:30:00-08:00
Location: Synopsys

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November 22, 2019November 22, 2019

Top Three Reasons to Attend the Synopsys Fusion Compiler Event!

Top Three Reasons to Attend the Synopsys Fusion Compiler Event!
by Daniel Nenni on 11-22-2019 at 10:00 am
Categories: EDA, Events, Synopsys

Image RemovedAs a professional semiconductor event attendee I can pretty much tell if an event will be successful by looking at the agenda. What I look for is simple, customer presentations. Not company presentations or partner presentations but actual customer case studies presented by name brand companies. For this event … Read More

November 15, 2019November 15, 2019

Synopsys Fusion Compiler Delivers ARM Hercules-Samsung 5LPE Design

Synopsys Fusion Compiler Delivers ARM Hercules-Samsung 5LPE Design
by Daniel Nenni on 11-15-2019 at 10:00 am
Categories: EDA, Events, Synopsys

Image Removed

There were many interesting presentations at ARM TechCon this year besides the keynote addresses by Arm, which were truly stunning for content and production value. One very interesting presentation was the talk given in the afternoon of Wednesday, October 9, 2019, titled, Synopsys Fusion Compiler for Next Generation… Read More

October 24, 2019October 22, 2019

Accelerating Functional Safety Verification

Accelerating Functional Safety Verification
by Bernard Murphy on 10-24-2019 at 6:00 am
Categories: Automotive, EDA, Synopsys

Verifying a design for functional safety requirements for an IP or SoC per ISO 26262 is a complex process that can’t be encapsulated in one tool. Process complexities depend on whether the Tier1 or OEM is targeting safety-levels ASIL-A , B, C or D, where ASIL-D applies to anything truly safety-critical such as airbag controls or … Read More

October 15, 2019October 15, 2019

Formal in the Field: Users are Getting More Sophisticated

Formal in the Field: Users are Getting More Sophisticated
by Bernard Murphy on 10-15-2019 at 5:00 am
Categories: EDA, Synopsys

Building on an old chestnut, if sufficiently advanced technology looks like magic, there are a number of technology users who are increasingly looking like magicians. Of course when it comes to formal, neither is magical, just very clever. The technology continues to advance and so do the users in their application of those methods.… Read More

October 8, 2019October 1, 2019

Design Perspectives on Intermittent Faults

Design Perspectives on Intermittent Faults
by Bernard Murphy on 10-08-2019 at 5:00 am
Categories: EDA, FPGA, Synopsys

Bugs are an inescapable reality in any but the most trivial designs and usually trace back to very deterministic causes – a misunderstanding of the intended spec or an incompletely thought-through implementation of some feature, either way leading to reliably reproducible failure under the right circumstances. You run diagnostics,… Read More

October 3, 2019October 3, 2019

AI Hardware Summit, Report #3: Enabling On-Device Intelligence

AI Hardware Summit, Report #3: Enabling On-Device Intelligence
by Randy Smith on 10-03-2019 at 6:00 am
Categories: EDA, Events, Synopsys

This is the third and final blog I have written about the recent AI Hardware Summit held at the Computer History Museum in Mountain View, CA. Day 1 of the conference was more about solutions in the data center, whereas Day 2 was primarily around solutions at the Edge. This presentation from Day 2 was given by Dr. Thomas Anderson, Head,… Read More

October 1, 2019October 23, 2019

Webinar: Finding Your Way Through Formal Verification

Webinar: Finding Your Way Through Formal Verification
by Bernard Murphy on 10-01-2019 at 6:00 am
Categories: EDA, Events, Synopsys

Formal verification has always appeared daunting to me and I suspect to many other people also. Logic simulation feels like a “roll your sleeves up and get the job done” kind of verification, easily understood, accessible to everyone, little specialized training required. Formal methods for many years remained the Image Removed… Read More

September 25, 2019September 25, 2019

High-Speed PHY IP for Hyperscale Data Centers

High-Speed PHY IP for Hyperscale Data Centers
by Tom Dillinger on 09-25-2019 at 10:00 am
Categories: EDA, Synopsys
4 Comments

A new designation has recently entered the vernacular of the computing industry – a hyperscale data center. The adjective hyperscale implies the ability of a computing resource to scale corresponding to increased workload, to maintain an appropriate quality of service.

The traditional enterprise data center is often characterized… Read More

July 25, 2019July 18, 2019

5G and V2X

5G and V2X
by Bernard Murphy on 07-25-2019 at 5:00 am
Categories: 5G, Automotive, EDA, Synopsys
2 Comments

Amid the glamor of autonomous vehicles and hot new ADAS features, communication between vehicles and other vehicles, pedestrians, cyclists or infrastructure, generally labeled V2X, doesn’t get as much press, perhaps because adoption is still pretty early or because it’s technology under the hood (quite literally) and therefore… Read More

May 25, 2019November 21, 2019

Automotive Design and Virtual Prototyping

Automotive Design and Virtual Prototyping
by Daniel Payne on 05-25-2019 at 5:40 pm
Categories: Automotive, EDA, Prototyping, Synopsys

The entire history of EDA software tools has enabled engineers to design ICs and SoCs using virtual prototyping, so most of us in the industry are familiar with the idea of modeling and simulating something as complex as an IC before actually starting the manufacturing process. In a complex system like an automobile there are a lot… Read More

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Prototyping with Intel's New 80M Gate FPGA and S2C! Analyzing PowerMOS Devices to Reduce Power Loss and Improve Reliability REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation REPLAY: Avoiding CDM (Charged Device Model) ESD Failures REPLAY: eFPGA – "What a great idea! But I have no idea how I’d use it!" REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification REPLAY: Fabless: The Transformation of the Semiconductor Industry REPLAY: The Brave New World of Customized Memory REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning REPLAY: VLSI Design Methodology Development REPLAY: Lightspeed Data Sync - Design Workspace Problems Solved! REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats? REPLAY: How ASIC/SoC Prototyping Solutions Can Help You! REPLAY: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso® REPLAY: Taiwan ESD Workshop Recording REPLAY: Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction REPLAY: Text: A Year of Breakfast Bytes by Paul McLellan (Free PDF Version) REPLAY: Finding Your Way Through Verification REPLAY: Concerned about IP security threats for your SoCs? REPLAY: Achronix: Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip REPLAY: PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior REPLAY: Thermal-induced Reliability Challenges and Solutions for Advanced IC Design REPLAY: Choose the Right ASIC Manufacturing Model for Your Business [filter] => 1 [visual] => 1 [rw_opt] => Array ( [widget_select] => 1 [others_front_page] => 1 [cpt_page] => 1 [others_blog_page] => 1 ) [display_widget_mobile] => 1 )

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Recent Article Comments

Why is Intel still short on chips?
Dec 2018 Intel 'backported' the B360 PCH from 14nm to 22nm and callid it "B365", possibly to free up 14nm…

— hkwint on December 6, 2019
Evolving Landscape of Self-Driving Safety Standards
Nice article, Bernard!! Making an autonomous car perfectly safe is a tough, tough job. Probably impossible. But …. given our…

— John East on December 5, 2019
2020 Semiconductor Foundry Landscape Update!
For years Intel used a process advantage to maintain their lead on AMD. Now, using TSMC, AMD has turned the…

— John East on December 5, 2019
Is the ASIC Business Dead?
I work for an ASIC company, or perhaps more specifically IC design services company with some focus on mixed signal…

— Peter Deutschman on December 5, 2019
Why is Intel still short on chips?
Dumb as a door stop sounds more likely to me... Intel CPUs are not only made on a CPU-tailored process…

— IanD on December 4, 2019
Why is Intel still short on chips?
Yes and lets not forget this gem: Oct 22, 2018 by Charlie Demerjian SemiAccurate has learned that Intel just pulled…

— Daniel Nenni on December 3, 2019
Why is Intel still short on chips?
Clearly, but why so many articles saying otherwise? Intentional or are the editors dumb as a door stop? https://www.techradar.com/news/intel-turns-to-samsung-for-help-keeping-up-with-amd-rumor-claims https://wccftech.com/intel-has-tapped-samsung-foundries-to-manufacture-cpus/…

— Daniel Nenni on December 3, 2019
Why is Intel still short on chips?
There's this https://www.forbes.com/sites/moorinsights/2019/12/03/aws-goes-all-in-on-arm-based-graviton2-processors-with-ec2-6th-gen-instances/ We'll see if graviton2 will be commercially available. Intel may not have this problem for much longer…

— Portland on December 3, 2019
Why is Intel still short on chips?
Big Intel is too slow on ramping up, why was F42 so slow?Is it Really Up? And older Fabs still…

— kgoncher on December 3, 2019
Why is Intel still short on chips?
It was from Charlie Demerjian from semiaccurate. The guy makes a lot of claims from speculations. Honest I thought what…

— Portland on December 3, 2019

Top Three Reasons to Attend the Synopsys Fusion Compiler Event!

Synopsys Fusion Compiler Delivers ARM Hercules-Samsung 5LPE Design

Accelerating Functional Safety Verification

Formal in the Field: Users are Getting More Sophisticated

Design Perspectives on Intermittent Faults

AI Hardware Summit, Report #3: Enabling On-Device Intelligence

Webinar: Finding Your Way Through Formal Verification

High-Speed PHY IP for Hyperscale Data Centers

5G and V2X

Automotive Design and Virtual Prototyping

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Seminar: Domain-Specific Processor Design...

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Recent Synopsys Press

Synopsys Custom Compiler Adopted by Samsung Foundry to Accelerate IP Design for 5LPE Process Technology with EUV Technology

Synopsys Completes Acquisition of DINI Group

Synopsys DesignWare ARC Data Fusion IP Subsystem Incorporated by Himax in Their Artificial Intelligence WiseEye ASIC

Samsung Foundry Deploys Industry-Leading Synopsys TestMAX XLBIST Dynamic In-System Test Solution for Automotive Safety

Synopsys and TSMC Collaborate to Develop Portfolio of DesignWare IP for TSMC 5nm FinFET Plus (N5P) Process

eSilicon to be Acquired by Inphi and Synopsys

Synopsys VC LP for Low Power Signoff Verification Delivers Up to 5X Runtime Gain at Samsung

Synopsys and AMD Execute Multi-Year ZeBu Emulation Agreement

Synopsys Accelerates Cloud Computing SoC Designs with New Die-to-Die PHY IP in Advanced 7nm FinFET Process

Synopsys Ships More Than 3,000 HAPS-80 Prototyping Systems

Recent Article Comments

Why is Intel still short on chips?

Evolving Landscape of Self-Driving Safety Standards

2020 Semiconductor Foundry Landscape Update!

Is the ASIC Business Dead?

Why is Intel still short on chips?

Why is Intel still short on chips?

Why is Intel still short on chips?

Why is Intel still short on chips?

Why is Intel still short on chips?

Why is Intel still short on chips?