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800x100 Efficient and Robust Memory Verification
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The Immensity of Software Development and the Challenges of Debugging (Part 3 of 4)

The Immensity of Software Development and the Challenges of Debugging (Part 3 of 4)
by Lauro Rizzatti on 10-03-2024 at 10:00 am

Immensity of SW development Part 3 Figure 1

Part 3 of this 4-part series analyzes methods and tools involved in debugging software at different layers of the software stack.

Software debugging involves identifying and resolving issues ranging from functional misbehaviors to crashes. The essential requirement for validating software programs is the ability to monitor… Read More


Synopsys and TSMC Pave the Path for Trillion-Transistor AI and Multi-Die Chip Design

Synopsys and TSMC Pave the Path for Trillion-Transistor AI and Multi-Die Chip Design
by Kalar Rajendiran on 10-02-2024 at 10:00 am

OIP 2024 Synopsys TSMC

Synopsys made significant announcements during the recent TSMC OIP Ecosystem Forum, showcasing a range of cutting-edge solutions designed to address the growing complexities in semiconductor design. With a strong emphasis on enabling next-generation chip architectures, Synopsys introduced both new technologies and … Read More


The Immensity of Software Development and the Challenges of Debugging Series (Part 2 of 4)

The Immensity of Software Development and the Challenges of Debugging Series (Part 2 of 4)
by Lauro Rizzatti on 09-25-2024 at 10:00 am

Immensity of SW development Part 2 Fig 1

Part 2 of this 4-part series reviews the role of virtual prototypes as stand-alone tools and their use in hybrid emulation for early software validation, a practice known as the “shift-left” methodology. It assesses the differences among these approaches, focusing on their pros and cons.

The Immensity of Software DevelopmentRead More


Synopsys Powers World’s Fastest UCIe-Based Multi-Die Designs with New IP Operating at 40 Gbps

Synopsys Powers World’s Fastest UCIe-Based Multi-Die Designs with New IP Operating at 40 Gbps
by Kalar Rajendiran on 09-23-2024 at 10:00 am

Synopsys 40G UCIe IP Solution

As the demand for higher performance computing solutions grows, so does the need for faster, more efficient data communication between components in complex multi-die system-on-chip (SoC) designs. In response to these needs, Synopsys has introduced the world’s fastest UCIe-based IP solution, capable of operating at a groundbreaking… Read More


Synopsys IP Processor Summit 2024

Synopsys IP Processor Summit 2024
by Daniel Nenni on 08-21-2024 at 6:00 am

Synopsys Processor Summit

Now that live events are filling up there are even more live events especially here in Silicon Valley. Synopsys, the #1 full IP provider, will host a processor summit here in Santa Clara next month. Given the popularity of anything RISC-V, I would expect this event to be very well attended so be sure and register in advance.

The networking… Read More


Mitigating AI Data Bottlenecks with PCIe 7.0

Mitigating AI Data Bottlenecks with PCIe 7.0
by Kalar Rajendiran on 08-05-2024 at 6:00 am

Mitigating AI Data Bottlenecks with PCIe 7.0 LinkedIn Event

During a recent LinkedIn webcast, Dr. Ian Cutress, Chief Analyst at More than Moore and Host at TechTechPotato, and Priyank Shukla, Principal Product Manager at Synopsys, shared their thoughts regarding the industry drivers, design considerations, and critical advancements in compute interconnects enabling data center… Read More


The Immensity of Software Development the Challenges of Debugging (Part 1 of 4)

The Immensity of Software Development the Challenges of Debugging (Part 1 of 4)
by Lauro Rizzatti on 07-15-2024 at 10:00 am

Immensity of SW development Fig 1

Part 1 of this 4-part series introduces the complexities of developing and bringing up the entire software stack on a System on Chip (SoC) or Multi-die system. It explores various approaches to deployment, highlighting their specific objectives and the unique challenges they address.

Introduction

As the saying goes, it’s… Read More


LIVE WEBINAR Maximizing SoC Energy Efficiency: The Role of Realistic Workloads and Massively Parallel Power Analysis

LIVE WEBINAR Maximizing SoC Energy Efficiency: The Role of Realistic Workloads and Massively Parallel Power Analysis
by Daniel Nenni on 07-03-2024 at 2:00 pm

The Role of Realistic Workloads and Massively Parallel Power Analysis

As the complexity of modern System-on-Chip (SoC) designs continues to rise, achieving energy efficiency measured as performance per watt has become a crucial design goal. With the increasing demand for powerful, multifunctional chips, balancing performance with power consumption has become essential. Realistic workloads… Read More


Synopsys’ Strategic Advancement with PCIe 7.0: Early Access and Complete Solution for AI and Data Center Infrastructure

Synopsys’ Strategic Advancement with PCIe 7.0: Early Access and Complete Solution for AI and Data Center Infrastructure
by Kalar Rajendiran on 06-25-2024 at 6:00 am

(From NewsRelease)Synopsys PCIe 7.0 IP Solution Infographic

In the rapidly evolving world of high-performance computing (HPC) and artificial intelligence (AI), technological advancements must keep pace with increasing demands for speed, efficiency, and security. Synopsys recently announced the industry’s first complete PCIe 7.0 IP solution. This groundbreaking initiative addresses… Read More


Synopsys-AMD Webinar: Advancing 3DIC Design Through Next-Generation Solutions

Synopsys-AMD Webinar: Advancing 3DIC Design Through Next-Generation Solutions
by Kalar Rajendiran on 06-13-2024 at 10:00 am

The Synopsys Multi Die Solution

Introduction of 2.5D and 3D multi-die based products are helping extend the boundaries of Moore’s Law, overcoming limitations in speed and capacity for high-end computational tasks. In spite of its critical function within the 3DIC paradigm, the interposer die’s role and related challenges are often neither fully comprehended… Read More