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The Most Interesting CEO in Semiconductors!

The Most Interesting CEO in Semiconductors!
by Daniel Nenni on 10-21-2020 at 6:00 am

GTC 2020 Lip Bu Tan

Hands down, without a doubt, the most interesting CEO in semiconductors is Lip-Bu Tan, founder of Walden Capitol and current CEO of Cadence Design Systems. If you want to talk about a man with a plan it’s Lip-Bu Tan.

Before we get into the fireside chat between Tom Caufield and Lip-Bu at the GTC 2020 Virtual event let’s do a quick biography:… Read More


Covering Configurable Systems. Innovation in Verification

Covering Configurable Systems. Innovation in Verification
by Bernard Murphy on 10-20-2020 at 6:00 am

innovation min

Covering configurable systems is a challenge. What’s a good strategy to pick a small subset of settings and still get high confidence in coverage? Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I continue our series on research ideas, here an idea from software testing which should also apply to hardware. Feel free… Read More


Tempus: Delivering Faster Timing Signoff with Optimal PPA

Tempus: Delivering Faster Timing Signoff with Optimal PPA
by Mike Gianfagna on 10-12-2020 at 10:00 am

Tempus Delivering Faster Timing Signoff with Optimal PPA

In July, I explored the benefits of the new Cadence Tempus™ Power Integrity Solution. In that piece, I explored some of the unique capabilities of this new tool with Brandon Bautz, senior product management group director and Hitendra Divecha, product management director in the Digital & Signoff Group at Cadence. I recently… Read More


Bug Trace Minimization. Innovation in Verification

Bug Trace Minimization. Innovation in Verification
by Bernard Murphy on 09-22-2020 at 6:00 am

innovation min

A checker tripped in verification. Is there a bug trace minimization technique to simplify manual debug? Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I continue our series to highlight all the great research that’s out there in verification. Feel free to comment.

The Innovation

This month’s pick is Simulation-BasedRead More


Anirudh CadenceLIVE Plays Up Computational Software

Anirudh CadenceLIVE Plays Up Computational Software
by Bernard Murphy on 09-17-2020 at 6:00 am

Anirudh min

Cadence has clearly found its groove with Intelligent System Design, something that Lip-Bu reinforced in the CadenceLIVE kickoff keynote on Tuesday, August 11th. Anirudh Devgan, president of Cadence, continued to discuss the theme in his keynote on Wednesday, August 12th with his equally consistent subtitle—”Strength… Read More


Lip-Bu Hyperscaler Cast Kicks off CadenceLIVE

Lip-Bu Hyperscaler Cast Kicks off CadenceLIVE
by Bernard Murphy on 09-02-2020 at 6:00 am

Lip Bu min

Lip-Bu (Cadence CEO) sure knows how to draw a crowd. For the opening keynote in CadenceLIVE (Americas) this year, he reprised his data-centric revolution pitch, followed by a talk from a VP at AWS on bending the curve in chip development. And that was followed by a talk by a Facebook director of strategy and technology on aspects of… Read More


Quick Error Detection. Innovation in Verification

Quick Error Detection. Innovation in Verification
by Bernard Murphy on 08-27-2020 at 6:00 am

innovation min

Can we detect bugs in post- and pre-silicon testing where we can drastically reduce latency between root-cause and effect? Quick error detection can. Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I continue our series on novel research ideas. Feel free to comment.

The Innovation

This month’s pick is Logic Bug DetectionRead More


The Big Three Weigh in on Emulation Best Practices

The Big Three Weigh in on Emulation Best Practices
by Mike Gianfagna on 08-18-2020 at 10:00 am

Emulation Best Practices

As software content increases in system-on-chip and system-in-package designs, emulation has become a critical enabling technology for the software team. This technology offers software developers the opportunity to verify their code in against a high-fidelity model of the target system that actually executes fast enough… Read More


Cadence Increases Verification Efficiency up to 5X with Xcelium ML

Cadence Increases Verification Efficiency up to 5X with Xcelium ML
by Mike Gianfagna on 08-13-2020 at 6:00 am

Screen Shot 2020 08 07 at 11.24.49 PM

SoC verification has always been an interesting topic for me. Having worked at companies like Zycad that offered hardware accelerators for logic and fault simulation, the concept of reducing the time needed to verify a complex SoC has occupied a lot of my thoughts. The bar we always tried to clear was actually simple to articulate… Read More


Structural CDC Analysis Signoff? Think Again.

Structural CDC Analysis Signoff? Think Again.
by Bernard Murphy on 08-05-2020 at 6:00 am

strainer min

Talking not so long ago to a friend from my Atrenta days, I learned that the great majority of design teams still run purely structural CDC analysis. You should sure asynchronous clock domains are suitably represented in the SDC, find all places where data crosses between those domains that require a synchronizer, gray-coded FIFO… Read More