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Formal at System Level. Innovation in Verification

Formal at System Level. Innovation in Verification
by Bernard Murphy on 07-27-2022 at 6:00 am

Innovation New

Formal verification at the SoC level has long seemed an unapproachable requirement. Maybe we should change our approach. Could formal be practical on a suitable abstraction of the SoC? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and… Read More


DSPs in Radar Imaging. The Other Compute Platform

DSPs in Radar Imaging. The Other Compute Platform
by Bernard Murphy on 07-20-2022 at 6:00 am

Radar Trends

In the flood of CPU and GPU announcements in pursuit of new technology advances, it is easy to lose track of another kind of platform – DSPs. Digital signal processors, once a niche platform for specialized applications, are now front and center in some of the hottest technologies. Because their strength in signal processing has… Read More


Clocking for High-Speed SerDes

Clocking for High-Speed SerDes
by Tom Dillinger on 07-18-2022 at 6:00 am

SerDes architecture

The incessant demand for faster data rates across a wide range of end applications has led to the development of the most recent generation of SerDes hardware, achieving 112Gbps.  For example, network switches in datacenter architectures are starting to provide 51T throughput utilizing these new 112Gbps implementations (51.2Tbps… Read More


Using AI in EDA for Multidisciplinary Design Analysis and Optimization

Using AI in EDA for Multidisciplinary Design Analysis and Optimization
by Daniel Payne on 07-04-2022 at 10:00 am

Optimality min

Most IC and system engineers follow a familiar process when designing a new product: create a model, use parameters for the model, simulate the model, observe the results, compare results versus requirements, change the parameters or model and repeat until satisfied or it’s time to tape out. On the EDA side, most tools perform… Read More


Cadence Execs Look to the Future

Cadence Execs Look to the Future
by Dave Bursky on 07-01-2022 at 6:00 am

CDNLive 2020

Everything is becoming digital, and everything digital requires semiconductors. Cadence’s President and CEO, Dr. Anirudh Devgan, highlighted this at the recent CadenceLIVE user conference and discussed many of the company’s accomplishments and future directions. Dr. Devgan also sees the emergence of data—especially … Read More


Stalling to Uncover Timing Bugs. Innovation in Verification

Stalling to Uncover Timing Bugs. Innovation in Verification
by Bernard Murphy on 06-29-2022 at 6:00 am

Innovation New

Artificially stalling datapaths and virtual channels is a creative method to uncover corner case timing bugs. A paper from Nvidia describes a refinement to this technique. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue… Read More


Refined Fault Localization through Learning. Innovation in Verification

Refined Fault Localization through Learning. Innovation in Verification
by Bernard Murphy on 05-25-2022 at 6:00 am

Innovation New

This is another look at refining the accuracy of fault localization. Once a bug has been detected, such techniques aim to pin down the most likely code locations for a root cause. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue… Read More


224G Serial Links are Next

224G Serial Links are Next
by Daniel Nenni on 05-17-2022 at 6:00 am

link designs

The tremendous increase in global data traffic over the past decade shows no sign of abating.  Indeed, the applications for all facets of data communications are expanding, from 5G (and soon, 6G) wireless communications to metropolitan area networks serving autonomous vehicles to broader deployment of machine learning algorithms. … Read More


Tensilica Edge Advances at Linley

Tensilica Edge Advances at Linley
by Bernard Murphy on 05-04-2022 at 6:00 am

NNE graphic min

The Linley spring conference this year had a significant focus on AI at the edge, with all that implies. Low power/energy is a key consideration, though increasing performance demands for some applications are making this more challenging. David Bell (Product Marketing at Tensilica, Cadence) presented the Tensilica NNE110… Read More


ML-Based Coverage Refinement. Innovation in Verification

ML-Based Coverage Refinement. Innovation in Verification
by Bernard Murphy on 04-27-2022 at 6:00 am

Innovation New

We’re always looking for ways to leverage machine-learning (ML) in coverage refinement. Here is an intriguing approach proposed by Google Research. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research… Read More