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ML plus formal for analog. Innovation in Verification

ML plus formal for analog. Innovation in Verification
by Bernard Murphy on 11-30-2020 at 6:00 am

innovation min

Can machine learning be combined with formal to find rare failures in analog designs? ML plus formal for analog – neat! Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I continue our series on research ideas. Here an idea from analog simulation sampling. Feel free to comment.

The Innovation

This month’s pick… Read More


Cadence is Making Floorplanning Easier by Changing the Rules

Cadence is Making Floorplanning Easier by Changing the Rules
by Mike Gianfagna on 11-25-2020 at 8:00 am

Mixed placement floorplan

SoC designs are getting more complex, resulting in a higher level of difficulty to get anything done. This trend is well-known. What I want to focus on here is how to deal with the issue of complexity. There are many approaches to taming this problem — faster algorithms for one, and improved algorithm efficiency or the ability to run… Read More


Verification IP for Systems? It’s Not What You Think.

Verification IP for Systems? It’s Not What You Think.
by Bernard Murphy on 11-05-2020 at 6:00 am

System VIP2 min

When I think of verification IP (VIP), I think of something closely tied to a protocol standard – AMBA, MIPI or DDR for example. Something that will generate traffic and run protocol compliance checks, to verify correct operation of an IP or as a model to use in SoC verification. What would a VIP for systems be? Systems support multiple… Read More


How ML Enables Cadence Digital Tools to Deliver Better PPA

How ML Enables Cadence Digital Tools to Deliver Better PPA
by Mike Gianfagna on 10-28-2020 at 10:00 am

How ML Enables Cadence Digital Tools to Deliver Better PPA

There has been a lot written about artificial intelligence/machine learning (AI/ML) and its application in the Cadence digital design flow. Most recently, I covered significant verification efficiency improvements in Xcellium ML.  A recent digital-themed white paper from Cadence takes a broader look at the impact of ML on… Read More


Clarity 3D Transient Solver Speeds Up EMI/EMC Certification

Clarity 3D Transient Solver Speeds Up EMI/EMC Certification
by Tom Simon on 10-25-2020 at 8:00 am

Clarity 3D Transient Solver

Cadence made waves a while back with its innovative Clarity 3D Solver, a FEM solver for near field EM analysis. Now they are shaking things up with their new far field Clarity 3D Transient Solver. System level EMI and EMC analysis has often exceeded the limits of simulation tools, leading to expensive and time-consuming prototype… Read More


The Most Interesting CEO in Semiconductors!

The Most Interesting CEO in Semiconductors!
by Daniel Nenni on 10-21-2020 at 6:00 am

GTC 2020 Lip Bu Tan

Hands down, without a doubt, the most interesting CEO in semiconductors is Lip-Bu Tan, founder of Walden Capitol and current CEO of Cadence Design Systems. If you want to talk about a man with a plan it’s Lip-Bu Tan.

Before we get into the fireside chat between Tom Caufield and Lip-Bu at the GTC 2020 Virtual event let’s do a quick biography:… Read More


Covering Configurable Systems. Innovation in Verification

Covering Configurable Systems. Innovation in Verification
by Bernard Murphy on 10-20-2020 at 6:00 am

innovation min

Covering configurable systems is a challenge. What’s a good strategy to pick a small subset of settings and still get high confidence in coverage? Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I continue our series on research ideas, here an idea from software testing which should also apply to hardware. Feel free… Read More


Tempus: Delivering Faster Timing Signoff with Optimal PPA

Tempus: Delivering Faster Timing Signoff with Optimal PPA
by Mike Gianfagna on 10-12-2020 at 10:00 am

Tempus Delivering Faster Timing Signoff with Optimal PPA

In July, I explored the benefits of the new Cadence Tempus™ Power Integrity Solution. In that piece, I explored some of the unique capabilities of this new tool with Brandon Bautz, senior product management group director and Hitendra Divecha, product management director in the Digital & Signoff Group at Cadence. I recently… Read More


Bug Trace Minimization. Innovation in Verification

Bug Trace Minimization. Innovation in Verification
by Bernard Murphy on 09-22-2020 at 6:00 am

innovation min

A checker tripped in verification. Is there a bug trace minimization technique to simplify manual debug? Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I continue our series to highlight all the great research that’s out there in verification. Feel free to comment.

The Innovation

This month’s pick is Simulation-BasedRead More


Anirudh CadenceLIVE Plays Up Computational Software

Anirudh CadenceLIVE Plays Up Computational Software
by Bernard Murphy on 09-17-2020 at 6:00 am

Anirudh min

Cadence has clearly found its groove with Intelligent System Design, something that Lip-Bu reinforced in the CadenceLIVE kickoff keynote on Tuesday, August 11th. Anirudh Devgan, president of Cadence, continued to discuss the theme in his keynote on Wednesday, August 12th with his equally consistent subtitle—”Strength… Read More