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An ISA-like Accelerator Abstraction. Innovation in Verification

An ISA-like Accelerator Abstraction. Innovation in Verification
by Bernard Murphy on 09-29-2021 at 6:00 am

Innovation New

A processor ISA provides an abstraction against which to verify an implementation. We look here at a paper extending this concept to accelerators, for verification of how these interact with processors and software. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys… Read More


Accelerating Exhaustive and Complete Verification of RISC-V Processors

Accelerating Exhaustive and Complete Verification of RISC-V Processors
by Ashish Darbari on 08-29-2021 at 6:00 am

FIG 1 spec bug

As processor architecture and design development becomes completely liberated with open-source RISC-V instruction set architecture (ISA), the race to get RISC-V silicon in our hands has increased massively. We have no doubt that in next 5 years, we will see RISC-V based laptops and desktops in the market. But would these processors… Read More


Side Channel Analysis at RTL. Innovation in Verification

Side Channel Analysis at RTL. Innovation in Verification
by Bernard Murphy on 08-26-2021 at 6:00 am

Innovation New

Roots of trust can’t prevent attacks through side-channels which monitor total power consumption or execution timing. Correcting weakness to such attacks requires pre-silicon vulnerability analysis. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO)… Read More


Cadence Tempus Update Promises to Transform Timing Signoff User Experience

Cadence Tempus Update Promises to Transform Timing Signoff User Experience
by Tom Simon on 08-23-2021 at 6:00 am

Tempus With SmartHub for Timing Signoff

Cadence invests heavily in the development of their Tempus Timing Signoff Solution due to its importance in the SoC design flow. I recently had a discussion on the topic of the most recent Tempus update with Brandon Bautz, senior product management group director in the Digital & Signoff Group, and Hitendra Divecha, product… Read More


Cerebrus, the ML-based Intelligent Chip Explorer from Cadence

Cerebrus, the ML-based Intelligent Chip Explorer from Cadence
by Kalar Rajendiran on 07-29-2021 at 10:00 am

Screen Shot 2021 07 21 at 4.39.06 PM

Electronic design automation (EDA) has come a long way from its beginnings. It has enabled chip engineers from specifying designs directly in layout format during the early days to today’s capture in RTL format. Every advance in EDA has made the task of designing a chip easier and increased the design team productivity, enabling… Read More


Instrumenting Post-Silicon Validation. Innovation in Verification

Instrumenting Post-Silicon Validation. Innovation in Verification
by Bernard Murphy on 07-28-2021 at 6:00 am

Instrumenting Post-Silicon Validation

Instrumenting post-silicon validation is not a new idea but here’s a twist. Using (pre-silicon) emulation to choose debug observation structures to instrument in-silicon. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO) and I continue our series on research… Read More


EDA Flows for 3D Die Integration

EDA Flows for 3D Die Integration
by Tom Dillinger on 07-20-2021 at 6:00 am

future integration

Background

The emergence of 2.5D heterogeneous die integration using a silicon (or organic) interposer has enabled unique system architectures.  The term “More than Moore” has been used to describe the circuit density and cost advantages of leveraging multiple die in the package, the die potentially in different process technologies. … Read More


Neural Nets and CR Testing. Innovation in Verification

Neural Nets and CR Testing. Innovation in Verification
by Bernard Murphy on 06-29-2021 at 10:00 am

Instrumenting Post-Silicon Validation

Leveraging neural nets and CR testing isn’t as simple as we first thought. But is that the last word in combining these two techniques? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO) and I continue our series on research ideas. As always, feedback welcome.… Read More


Circuit Simulation Challenges to Design the Xilinx Versal ACAP

Circuit Simulation Challenges to Design the Xilinx Versal ACAP
by Daniel Payne on 06-24-2021 at 10:00 am

xilinx versal acap min

One of the most unique acronyms that I learned about this past year is ACAP from Xilinx, which stands for Adaptive Compute Acceleration Platform. At the recent Cadence LIVE event, I had the pleasure of watching Pei Yao, a Xilinx senior staff CAD engineer, as she talked about the challenges of getting all the analog and mixed-signals… Read More


EDA Design and Amazon Web Services (AWS)

EDA Design and Amazon Web Services (AWS)
by Daniel Payne on 06-21-2021 at 10:00 am

EC2 min

I first remember blogging about EDA in the cloud starting back in 2011, so what’s changed in the last 10 years you may ask? In 2011, it was basically a handful of EDA point tools running batch mode in the cloud, and you were on your own to integrate those into a coherent flow, so expect help from the CAD and IT departments for sure.… Read More