WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 449
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 449
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
    [is_post] => 
)
            
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WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 449
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 449
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
    [is_post] => 
)

Structural CDC Analysis Signoff? Think Again.

Structural CDC Analysis Signoff? Think Again.
by Bernard Murphy on 08-05-2020 at 6:00 am

strainer min

Talking not so long ago to a friend from my Atrenta days, I learned that the great majority of design teams still run purely structural CDC analysis. You should sure asynchronous clock domains are suitably represented in the SDC, find all places where data crosses between those domains that require a synchronizer, gray-coded FIFO… Read More


Cadence on Automotive Safety: Without Security, There is no Safety

Cadence on Automotive Safety: Without Security, There is no Safety
by Mike Gianfagna on 08-04-2020 at 10:00 am

Attack vectors and EDA countermeasures

One of the Designer Track at this year’s DAC focused on the popular topic of automotive electronics.  The title was particularly on-point, The Modern Automobile: A Safety and Security “Hot Zone”. The session was chaired by Debdeep Mukhopadhyay, a Professor at the Indian Institute of Technology in Kharagpur.

This special, invited… Read More


DAC Panel: Cadence Weighs in on AI for EDA, What Applications, Where’s the Data?

DAC Panel: Cadence Weighs in on AI for EDA, What Applications, Where’s the Data?
by Mike Gianfagna on 07-29-2020 at 6:00 am

Drivers of Convergence in Computational Software

DAC was full of great panels, research papers and chip design stories this year, the same as other years. Being a virtual show, there were some differences of course. I’ve heard attendance was way up, allowing a lot more folks to experience the technical program.  This is likely to be true for a virtual event. I’m sure we’ll see more… Read More


#57DAC – Panel Discussion of High Level Synthesis

#57DAC – Panel Discussion of High Level Synthesis
by Daniel Payne on 07-28-2020 at 10:00 am

sean dart, Cadence

Presenters took a trip down memory lane at DAC this year by having a panel discussion on HLS (High Level Synthesis) spanning from 1974 to 2020, and that time period aligns with when I first graduated from the University of Minnesota in 1978, starting chip design at Intel, then later transitioning into EDA companies by 1986. MarilynRead More


Cadence Defines a New Signoff Paradigm with Tempus PI

Cadence Defines a New Signoff Paradigm with Tempus PI
by Mike Gianfagna on 07-20-2020 at 10:00 am

Screen Shot 2020 06 24 at 11.24.34 PM

Semiconductor technology advances have a way of rewriting the rule book. As process geometries shrink, subtle effects graduate to mainstream problems. Performance curves can become inverted. And no matter what else occurs, low power demands are constantly reducing voltage and design margins along with it. Sometimes these… Read More


Using AI to Locate a Fault. Innovation in Verification

Using AI to Locate a Fault. Innovation in Verification
by Bernard Murphy on 07-16-2020 at 10:00 am

innovation in verification

After we detect a bug, can we use AI to locate the fault, or at least get close? Paul Cunningham (GM of Verification at Cadence), Jim Hogan and I continue our series on novel research ideas, through a paper in software verification we find equally relevant to hardware. Feel free to comment.

 

The Innovation
This month’s pick is… Read More


The Future of Chip Design with the Cadence iSpatial Flow

The Future of Chip Design with the Cadence iSpatial Flow
by Mike Gianfagna on 07-06-2020 at 10:00 am

Screen Shot 2020 06 20 at 2.30.57 PM

A few months ago, I wrote about the announcement of a new digital full flow from Cadence. In that piece, I focused on the machine learning (ML) aspects of the new tool. I had covered a discussion with Cadence’s Paul Cunningham a week before that explored ML in Cadence products, so it was timely to dive into a real-world example of the … Read More


Cadence Adds “Always On” to vManager Verification Management with Distributed and Cloud Access

Cadence Adds “Always On” to vManager Verification Management with Distributed and Cloud Access
by Mike Gianfagna on 06-17-2020 at 10:00 am

Screen Shot 2020 06 15 at 11.32.15 AM

Cadence vManager™ Verification Management provides what the company describes as metric-driven signoff. Anyone who has been through the tapeout process for a complex SoC knows the perils of verification sign-off. How much of the chip has been verified?  What’s left to do? Will all be ready when the tapeout deadline arrives? … Read More


Predicting Bugs: ML and Static Team Up. Innovation in Verification

Predicting Bugs: ML and Static Team Up. Innovation in Verification
by Bernard Murphy on 06-11-2020 at 6:00 am

innovation

Can we predict where bugs are most likely to be found, to better direct testing? Paul Cunningham (GM of Verification at Cadence), Jim Hogan and I continue our series on novel research ideas, again through a paper in software verification we find equally relevant to hardware. Feel free to comment if you agree or disagree.

The InnovationRead More


Is Mutation Testing Worth the Effort? Innovation in Verification

Is Mutation Testing Worth the Effort? Innovation in Verification
by Bernard Murphy on 05-19-2020 at 6:00 am

innovation

Mutation testing is an intriguing idea, but is it useful? Paul Cunningham (GM of Verification at Cadence), Jim Hogan and I continue our series on novel research ideas, here looking at a paper examining the pros and cons of this topic. Feel free to comment if you agree or disagree.

The Innovation

This month’s pick is Which Software Read More