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Explicit and implicit sneak paths to leak or compromise information continue to represent a threat to security. This paper looks a refinement of existing gate level information flow tracking (IFT) techniques extended to RTL, encouraging early-stage security optimization. Paul Cunningham (Senior VP/GM, Verification at … Read More
Formal methods offer completeness in proving functionality but are difficult to scale to system level without abstraction and cannot easily incorporate system aspects outside the logic world such as in cyber-physical systems (CPS). Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst,… Read More
As integration levels increase, clock frequencies rise, and feature sizes shrink it is not surprising that all or most aspects of semiconductor design become more complex and demand more from design technologies. One example where the traditional approach is breaking down is in optimizing power distribution networks (PDNs)… Read More
I wrote previously that the debate over which CPU rules the world (Arm versus RISC-V) somewhat misses the forest for the trees in modern systems. This is nowhere more obvious that in intelligent audio and vision: smart doorbells, speakers, voice activated remotes, intelligent earbuds, automotive collision avoidance, self-parking,… Read More
Static Timing Analysis (STA) has been an EDA tool category for many years now, yet with each new generation of smaller foundry process nodes come new physical effects that impact timing, requiring new analysis features to be added. For advanced process nodes, there are five different types of analysis that must be included when… Read More
Mixed-signal modeling is becoming more important as interaction between digital and analog circuitry become more closely intertwined. This level of modeling depends critically on sufficiently accurate yet fast behavioral models for analog components. Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano… Read More
Assertion based verification is a very productive way to catch bugs, however assertions are hard enough to write that assertion-based coverage is not as extensive as it could be. Is there a way to simplify developing assertions to aid in increasing that coverage? Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl … Read More
When considering SoC architectures it is easy to become trapped in simple narratives. These assume the center of compute revolves around a central core or core cluster, typically Arm, more recently perhaps a RISC-V option. Throw in an accelerator or two and the rest is detail. But for today’s competitive products that view is a … Read More
Support for AI at the edge has prompted a good deal of innovation in accelerators, initially in CNNs, evolving to DNNs and RNNs (convolutional neural nets, deep neural nets, and recurrent neural nets). Most recently, the transformer technology behind the craze in large language models is proving to have important relevance at… Read More
I have historically avoided mixed signal topics, assuming they decouple from digital and can be left to the experts. That simple view no longer holds water. Analog and digital are becoming more closely linked through control loops and datapaths, requiring a careful balancing act in verification between performance, accuracy… Read More
Podcast EP16: Hyperscale Computing & Changes in the Datacenter
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Podcast EP105: Cadence STA Strategy and Capabilities, Today and Tomorrow with Brandon Bautz
Podcast EP112: How Cadence is Revolutionizing Full-Chip Signoff with Certus
Most Viewed Blog 2018
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