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#DAC56 – Optimizing Verification Throughput for Advanced Designs in a Connected World

#DAC56 – Optimizing Verification Throughput for Advanced Designs in a Connected World
by Daniel Payne on 07-24-2019 at 10:00 am

Cadence, DAC 56, Wednesday

It was the final day of DAC56 and my head was already spinning from information overload after meeting so many people and hearing so many presentations, but I knew that IC functional verification was a huge topic and looming bottleneck for many SoC design teams, so I made a last-minute email request to attend a luncheon panel discussion… Read More


SiP is the new SoC @ 56thDAC

SiP is the new SoC @ 56thDAC
by Tom Dillinger on 06-19-2019 at 6:48 pm

The emergence of 3D packaging technology has been accompanied by the term “more than Moore”, to reflect the increase in areal circuit density at a rate that exceeds the traditional IC scaling pace associated with Moore’s Law.  At the recent Design Automation Conference in Las Vegas, numerous exhibits on the vendor floor presented… Read More


Parallel SPICE Circuit Simulator Debuts

Parallel SPICE Circuit Simulator Debuts
by Daniel Payne on 06-03-2019 at 10:01 am

Spectre X, speed improvements

In EDA the most successful companies will often re-write their software tools in order to add new features, improve accuracy, increase capacity and of course, shorten run times. For SPICE circuit simulators we typically look at several factors to see if a new tool is worth a look or not:

  • Netlist compatibility
  • Model support
  • Foundry
Read More

JasperGold Gets Smarter, Faster and Easier for Signoff

JasperGold Gets Smarter, Faster and Easier for Signoff
by Bernard Murphy on 05-28-2019 at 5:00 am

Machine learning (ML) is already making its way into EDA tools and flows, but the majority of announcements have been around implementation, especially in guiding toward improved timing and area. This is a pretty obvious place to start; ML is in one sense an optimization technique, trained on prior examples, which should be able… Read More


Anirudh Keynote at CDNLive 2019

Anirudh Keynote at CDNLive 2019
by Bernard Murphy on 05-08-2019 at 7:00 am

Anirudh Devgan (President of Cadence), gave the third keynote at CDNLive Silicon Valley this year. He has clearly become adept in this role. He has a big, but supportable vision for Cadence across markets and technologies and he’s become a master of the annual tech reveals that I usually associate with keynotes.


Anirudh opened … Read More


EDA Update 2019

EDA Update 2019
by Daniel Nenni on 04-26-2019 at 12:00 pm

Over the last six years EDA has experienced yet another disruption not unlike the Synopsys acquisition of Avant! in 2001 which positioned Synopsys for the EDA lead they still enjoy today. Or the hiring of famed venture capitalist Lip-Bu Tan in 2009 to be the CEO of struggling EDA pioneer Cadence Design Systems. Under Lip-Bu’s… Read More


Hogan Fireside Chat with Paul Cunningham at ESDA

Hogan Fireside Chat with Paul Cunningham at ESDA
by Bernard Murphy on 04-17-2019 at 7:00 am

If you’re in verification and you don’t know who Paul Cunningham is, this is a guy you need to have on your radar. Paul has risen through the Cadence ranks fast, first in synthesis and now running the verification group, responsible for about a third of Cadence revenue and a hefty percentage of verification tooling in the semiconductor… Read More


Lip-Bu Keynote at CDNLive 2019

Lip-Bu Keynote at CDNLive 2019
by Bernard Murphy on 04-10-2019 at 7:00 am

Cadence CEO Lip-Bu Tan is always an interesting guy to listen to for his broader technology industry overview and his insight into emerging tech through his Walden International investments. Though we’re usually heads-down in challenging technical problems, it’s good to look up from time to time to check whether what … Read More


My Thoughts on Cadence in the Cloud

My Thoughts on Cadence in the Cloud
by Daniel Nenni on 04-03-2019 at 12:00 pm

The cloud is a highly popular term that a lot of people don’t fully understand. If you are one of those people please read on as I will share my experience, observations, and opinions. Even if you are a cloud aficionado you may want to catch up on what’s new with EDA cloud services so again read on.

When we first started SemiWiki 9 years … Read More


Solving the EM Solver Problem

Solving the EM Solver Problem
by Tom Simon on 04-03-2019 at 7:00 am

The need for full wave EM solvers has been creeping into digital design for some time. Higher operating frequencies – like those found in 112G links, lower noise margins – caused by multi level signaling such as in PAM-4, and increasing design complexity – as seen in RDL structures, interposers, advanced connector… Read More