CAST Compression IP Webinar 800x100 (2)
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4178
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4178
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

TCAD for 3D Silicon Simulation

TCAD for 3D Silicon Simulation
by Daniel Payne on 06-03-2025 at 10:00 am

Silvaco TCAD min

Semiconductor fabs aim to have high yields and provide processes that attract design firms and win new design starts, but how does a fab deliver their process nodes in a timely manner without having to run lots of expensive silicon through the line? This is where simulation and TCAD tools come into play, and to learn more about this… Read More


Breker Verification Systems at the 2025 Design Automation Conference #62DAC

Breker Verification Systems at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-02-2025 at 10:00 am

62nd DAC SemiWiki

Breker Verification Systems Plans Demonstrations of its Complete Synthesis and SystemVIP Library and Solutions Portfolio

Attendees who step into the Breker Verification Systems booth during DAC (Booth #2520—second floor) will see demonstrations of its Trek Test Suite Synthesis and SystemVIP libraries and solutions portfolio.… Read More


The SemiWiki 62nd DAC Preview

The SemiWiki 62nd DAC Preview
by Daniel Nenni on 06-02-2025 at 6:00 am

62nd DAC SemiWiki

After being held in San Francisco since the pandemic the beloved Design Automation Conference will be on the move again. In 2026 DAC will be held in Huntington Beach. For you non-California natives, Huntington Beach is a California city Southeast of Los Angeles. It’s known for surf beaches and its long Huntington Beach Pier.… Read More


Video EP7: The impact of Undo’s Time Travel Debugging with Greg Law

Video EP7: The impact of Undo’s Time Travel Debugging with Greg Law
by Daniel Nenni on 05-30-2025 at 10:00 am

In this episode of the Semiconductor Insiders video series, Dan is joined by Dr Greg Law, CEO of Undo, He is a C++ debugging expert, well-known conference speaker, and the founder of Undo. Greg explains the history of Undo, initially as a provider of software development and debugging tools for software vendors. He explains that… Read More


Synopsys Addresses the Test Barrier for Heterogeneous Integration

Synopsys Addresses the Test Barrier for Heterogeneous Integration
by Mike Gianfagna on 05-29-2025 at 10:00 am

Synopsys Addresses the Test Barrier for Heterogeneous Integration

The trend is clear, AI and HPC is moving to chiplet-based, or heterogenous design to achieve the highest levels of performance, while traditional monolithic system-on-chip (SoC) designs struggle to scale. What is also clear is the road to this new design style is not a smooth one. There are many challenges to overcome. Some are … Read More


Anirudh Keynote at CadenceLIVE 2025 Reveals Millennium M2000

Anirudh Keynote at CadenceLIVE 2025 Reveals Millennium M2000
by Bernard Murphy on 05-29-2025 at 6:00 am

Anirudh Keynote at CadenceLIVE 2025 Reveals Millennium M2000

Another content-rich kickoff covering a lot of bases under three main themes: the new Millennium AI supercomputer release, a moonshot towards full autonomy in chip design exploiting agentic AI, and a growing emphasis on digital twins. Cadence President and CEO Anirudh Devgan touched on what is new today, and also market directions… Read More


Design-Technology Co-Optimization (DTCO) Accelerates Market Readiness of Angstrom-Scale Process Technologies

Design-Technology Co-Optimization (DTCO) Accelerates Market Readiness of Angstrom-Scale Process Technologies
by Kalar Rajendiran on 05-28-2025 at 10:00 am

Sassine Holding an 18A Test chip

Design-Technology Co-Optimization (DTCO) has been a foundational concept in semiconductor engineering for years. So, when Synopsys referenced DTCO in their April 2025 press release about enabling Angstrom-scale chip designs on Intel’s 18A and 18A-P process technologies, it may have sounded familiar—almost expected. … Read More


Optimizing an IR for Hardware Design. Innovation in Verification

Optimizing an IR for Hardware Design. Innovation in Verification
by Bernard Murphy on 05-28-2025 at 6:00 am

Innovation New

Intermediate representations (IRs) between high level languages (C++, AI, etc.) and machine language are both commonplace (witness LLVM) and a continuing active area of research. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford,… Read More


WEBINAR: PCIe 7.0? Understanding Why Now Is the Time to Transition

WEBINAR: PCIe 7.0? Understanding Why Now Is the Time to Transition
by Don Dingee on 05-27-2025 at 10:00 am

PCIe application interface options are the primary motivation for the PCIe 7.0 transition

PCIe is familiar to legions of PC users as a high-performance enabler for expansion slots, especially GPU-based graphics cards and M.2 SSDs. It connects higher-bandwidth networking adapters and niche applications like system expansion chassis in server environments. Each PCIe specification generation has provided a leap… Read More


Video EP6: The Benefits of AI Agents for Waveform Debugging with Zackary Glazewski of Alpha Design

Video EP6: The Benefits of AI Agents for Waveform Debugging with Zackary Glazewski of Alpha Design
by Daniel Nenni on 05-23-2025 at 6:00 am

In this episode of the Semiconductor Insiders video series, Dan is joined by Zackary Glazewski, an ML Engineer at Alpha Design AI. Dan explores the challenges of waveform debugging with Zack, who explains how the process is done today and the shortcoming of existing approaches. He explains why current approaches are time consuming… Read More