hip webinar automating integration workflow 800x100 (1)
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BDD-Based Formal for Floating Point. Innovation in Verification

BDD-Based Formal for Floating Point. Innovation in Verification
by Bernard Murphy on 02-27-2024 at 6:00 am

Innovation New

A different approach to formally verifying very challenging datapath functions. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome. We’re planning to add a wrinkle… Read More


New Emulation, Enterprise Prototyping and FPGA-based Prototyping Launched

New Emulation, Enterprise Prototyping and FPGA-based Prototyping Launched
by Daniel Payne on 02-26-2024 at 10:00 am

Veloce Strato CS min

General purpose CPUs have run most EDA tools quite well for many years now, but if you really want to accelerate something like simulation then you start to look at using specializedhardware accelerators. . Emulators came onto the scene around 1986 and the processing power has greatly increased over the years, mostly in response… Read More


Photonic Computing – Now or Science Fiction?

Photonic Computing – Now or Science Fiction?
by Mike Gianfagna on 02-26-2024 at 6:00 am

Photonic Computing – Now or Science Fiction?

Cadence recently held an event to dig into the emerging world of photonic computing. Called The Rise of Photonic Computing, it was a two-day event held in San Jose on February 7th and 8th. The first day of the event was also accessible virtually. I attended a panel discussion on the topic – more to come on that. The day delivered a rich… Read More


Achieving Extreme Low Power with Synopsys Foundation IP Memory Compilers and Logic Libraries

Achieving Extreme Low Power with Synopsys Foundation IP Memory Compilers and Logic Libraries
by Mike Gianfagna on 02-22-2024 at 10:00 am

Achieving Extreme Low Power with Synopsys Foundation IP Memory Compilers and Logic Libraries

The relentless demand for lower power SoCs is evident across many markets.  Examples include cutting-edge mobile, IoT, and wearable devices along with the high compute demands for AI and 5G/6G communications. Drivers for low power include battery life, thermal management and, for high compute applications, the overall cost… Read More


Navigating the 1.6Tbps Era: Electro-Optical Interconnects and 224G Links

Navigating the 1.6Tbps Era: Electro-Optical Interconnects and 224G Links
by Kalar Rajendiran on 02-22-2024 at 6:00 am

Simulation and Silicon ADC outpit scatter plot

In the relentless pursuit of ever-increasing data speeds, the 1.6 Terabits per second (Tbps) era looms on the horizon, promising unprecedented levels of connectivity and bandwidth within data centers. As data-intensive applications proliferate and the demand for real-time processing escalates, the need for robust and efficient… Read More


Cadence Debuts Celsius Studio for In-Design Thermal Optimization

Cadence Debuts Celsius Studio for In-Design Thermal Optimization
by Bernard Murphy on 02-21-2024 at 6:00 am

Celsius Studio min

Continuing the multiphysics theme, I talked recently with Melika Roshandell (Product Management Director at Cadence) on the continuing convergence between MCAD and ECAD. You should know first that Melika has a PhD in mechanical engineering and an extensive background in thermal engineering at Broadcom and Qualcomm, all very… Read More


Handling Preprocessed Files in a Hardware IDE

Handling Preprocessed Files in a Hardware IDE
by Daniel Nenni on 02-20-2024 at 10:00 am

Preprocessor 1

For several years now, I’ve been meeting with AMIQ EDA co-founder Cristian Amitroaie every few months to discuss the state of the industry, key trends in design and verification, and the ways that they help facilitate and accelerate chip development. I noticed an interesting new feature mentioned in their latest press releaseRead More


CEO Interview: Vincent Bligny of Aniah

CEO Interview: Vincent Bligny of Aniah
by Daniel Nenni on 02-09-2024 at 6:00 am

Imge 2

Vincent Bligny is a renowned expert in mixed-signal verification, particularly with transistor-level formal techniques. He spent 15 years in this industry, mainly within STMicroelectronics’ design and verification teams, allowing him to understand the challenges and opportunities of the EDA field.

 Tell us about your company?Read More


Outlook 2024 with Anna Fontanelli Founder & CEO MZ Technologies

Outlook 2024 with Anna Fontanelli Founder & CEO MZ Technologies
by Daniel Nenni on 02-08-2024 at 10:00 am

ANNA (1)

I spoke with Anna again at the Chiplet Summit this week, we had previously spoken at DAC 2023. MZ is short for Monozukuri which is a Japanese term that translates to “making things” or “manufacturing.” In a broader sense, it refers to the art, science, and craftsmanship of creating products which fit chiplets… Read More


2024 Outlook with Cristian Amitroaie, Founder and CEO of AMIQ EDA

2024 Outlook with Cristian Amitroaie, Founder and CEO of AMIQ EDA
by Daniel Nenni on 02-07-2024 at 10:00 am

AMIQ EDA DVT Eclipse

SemiWki has been working with AMIQ EDA for more than four years now and it has been quite the education. AMIQ EDA is a company that specializes in providing development and verification solutions for digital design and verification teams in the semiconductor industry. They offer a range of products and services aimed at improving… Read More