3DIC Design from Concept to Silicon 800X100
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Bonds, Wire-bonds: No Time to Mesh Mesh It All with Phi Plus

Bonds, Wire-bonds: No Time to Mesh Mesh It All with Phi Plus
by Matt Commens on 11-23-2021 at 10:00 am

Ansys Phi Plus

Automatic adaptive meshing in HFSS is a critical component of its advanced simulation process. Guided by Maxwell’s Equations, it efficiently refines the mesh to accurately capture both the geometric and electromagnetic detail of a design. The end result is a process that guarantees accurate and reliable simulation results… Read More


Learning-Based Power Modeling. Innovation in Verification

Learning-Based Power Modeling. Innovation in Verification
by Bernard Murphy on 11-23-2021 at 6:00 am

Innovation New

Learning-Based Power Modeling. Innovation in Verification

Is it possible to automatically generate abstract power models for complex IP which can both run fast and preserve high estimation accuracy? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO) and… Read More


Machine Learning Applied to IP Validation, Running on AWS Graviton2

Machine Learning Applied to IP Validation, Running on AWS Graviton2
by Daniel Payne on 11-22-2021 at 10:00 am

Solido Variation Designer on Neoverse N1 CPU min

I recall meeting with Solido at DAC back in 2009, learning about their Variation Designer tool that allowed circuit designers to quickly find out how their designs performed under the effects of process variation, in effect finding the true corners of the process. Under the hood the Solido tool was using Machine Learning (ML) techniques… Read More


Numerical Sizing and Tuning Shortens Analog Design Cycles

Numerical Sizing and Tuning Shortens Analog Design Cycles
by Tom Simon on 11-22-2021 at 6:00 am

Sizing and tuning

By any measure analog circuit design is a difficult and complex process. This point is driven home in a recent webinar by MunEDA. Michael Pronath, VP Products and Solutions at MunEDA, lays out why, even with the assistance of simulators, analog circuit sizing and tuning can consume weeks of time in what can potentially be a non-convergent… Read More


Synopsys Expands into Silicon Lifecycle Management

Synopsys Expands into Silicon Lifecycle Management
by Daniel Payne on 11-18-2021 at 10:00 am

SLM, Synopsys

I spoke with Steve Pateras of Synopsys last week to better understand what was happening with their Silicon Lifecycle Management vision, and I was reminded of a Forbes article from last year: Never Heard of Silicon Lifecycle Management? Join the Club. At least two major EDA vendors are now using the relatively new acronym SLM, and… Read More


Register Management is the Foundation of Every Chip

Register Management is the Foundation of Every Chip
by Mike Gianfagna on 11-17-2021 at 6:00 am

Register Management is the Foundation of Every Chip

Virtually every chip today runs software. And that software needs to interact with and control the hardware on the chip. There are typically many interfaces to manage as well as dedicated hardware accelerators to coordinate. In fact, many of those hardware accelerators are present only to support the execution of the software… Read More


Siemens EDA Automotive Insights, for Analysts

Siemens EDA Automotive Insights, for Analysts
by Bernard Murphy on 11-16-2021 at 6:00 am

Siemens auto electronics min

There is a classical approach to EDA marketing, and semiconductor marketing at times, which aims exclusively at technical customers and the businesspeople immediately around those experts. The style is understandable and necessary. Those folks are the direct influencers and buyers of the products we are promoting, so we must… Read More


Tessent Streaming Scan Network Brings Hierarchical Scan Test into the Modern Age

Tessent Streaming Scan Network Brings Hierarchical Scan Test into the Modern Age
by Tom Simon on 11-15-2021 at 10:00 am

Streaming Scan Network

Remember when you had to use dial up internet or parallel printer cables connected directly to the printer to print something? Well even if you don’t remember these things, you know that now there is a better way. Regrettably, the prevalent methods used for hierarchical Design for Test (DFT) still look at lot like this – SoC level … Read More


Battery Sipping HiFi DSP Offers Always-On Sensor Fusion

Battery Sipping HiFi DSP Offers Always-On Sensor Fusion
by Tom Simon on 11-11-2021 at 10:00 am

HiFi DSP

Earbuds are one of the fastest growing market segments, which is creating the need for audio DSPs with higher performance and a smaller energy footprint. More than just being wireless speakers – earbuds, and wearables for that matter, have become a sophisticated extension of the user interface of phones and laptops, etc.… Read More


Minimizing MCU Supply Chain Grief

Minimizing MCU Supply Chain Grief
by Bernard Murphy on 11-11-2021 at 6:00 am

Siemens AUTOSAR min

I doubt there is anyone who hasn’t felt the impact of supply chain problems, from late ecommerce deliveries (weeks) to kitchen appliances (up to 6 months or more). Perhaps no industry has been more affected than auto makers, whose cars are now critically dependent on advanced electronics. According to a white paper recently released… Read More