There’s a world of difference between our smart phones that are battery powered and pack billions of transistors, and power MOSFET devices that can be used in industrial applications, telecom, cloud computing and automotive where they could be run at a few hundred volts and up to 80A of current. I’ve read about one power MOSFET company called Monolithic Power Systems, Inc. (MPS) because they were in the news recently with an open-source ventilator to help out during the COVID-19 pandemic. Now that’s a noble goal to have.
MPS also uses some EDA tools to help automate their IC design process of power MOSFET devices, and back in June 2019 they talked about using Polas from Empyrean. I followed up on WebEx with Kyle Tsai at Empyrean to see what Polas had to offer, and then better understand the design challenges.
Designers of power MOSFET devices have a handful of challenges, like:
- Reaching a low Rds value to meet spec
- Sufficient metal interconnections
- Package and pad locations that work
- Vias and contacts that allow large, peak currents
- Meeting dead-time specs
Shown below is a schematic with two MOSFET devices, the one on top is called high-side, and the one on the bottom is called low-side. The gates of each MOSFET are pulsed at complimentary times:
The four types of analysis that the Polas tool offers for power MOSFET devices include:
- EM/IR drop
- Timing Delay
IC layout creates parasitic RC values, and these most be accounted for during each analysis because they impact how the device performs in trying to meet all of the specifications. Polas uses some clever technology to account for IC layout and parasitics:
- A field solver to account for irregular polygons
- Split MOS for the most accurate interconnect resistance
- Fast-mode Rds(on) and IR drop analysis without dynamic circuit simulation
- SPICE-based simulation mode for Rds(on) and IR drop analysis
In just a few minutes you can get a very detailed report of Rdson effective resistance with Polas:
EM/IR drop analysis uses a color gradient (red – large drop, blue – small drop) to show the weak and strong spots of your layout, so the design engineer can communicate to the layout designer on which areas need to have wider metal or improved vias and contacts:
Timing delay analysis uses a circuit simulator called ALPS, and colors show how the delay changes across the IC layout view:
Cross-talk is the capacitive coupling of adjacent IC layers, so the analysis shows the engineering team all of the coupling nets and their capacitive coupling so that better layout decisions can be made to minimize the effect. Here you can see the cross-probing between the coupling list reported on the left, with the layout on the right:
Setting up and using Polas is straight forward, you’ll just need the PDK files from your foundry and the IC layout, so it fits nicely into your design flow. Some other unique features with Polas are support of:
- Tandem MOS devices
- Different widths and types in the layout
- Pre-drivers for power MOS
Customer Case 1
A Polas user doing charger power MOS designs with a BCD technology and they needed to do pad location analysis and optimization. With this tool they were able to calculate the Rdson values and current density. Next, they optimized the pad number and location, meeting cost and performance goals. Here’s a table showing their Pad number, Rdson value, top metal resistance and the maximum current densities:
Customer Case 2
In this scenario engineers were designed a vehicle power MOS on a BCD process, and they ran the timing analysis to help optimize their layout to meet timing specifications. The good news is that it took only one pass of silicon to get their results. Notice that this layout uses 12,000 fingers.
Industrial, telecom, cloud computing and automotive designs are all using power MOSFET chips, and with their unique environments come challenging design requirements. It’s now possible to use EDA tools like Polas from Empyrean to quickly and accurately analyze Rdson, EM/IR drop, timing delays and cross-talk effects.