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Analyzing PowerMOS Devices to Reduce Power Loss and Improve Reliability

REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation

REPLAY: Avoiding CDM (Charged Device Model) ESD Failures

REPLAY: eFPGA – "What a great idea! But I have no idea how I’d use it!"

REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification

REPLAY: Fabless: The Transformation of the Semiconductor Industry

REPLAY: The Brave New World of Customized Memory

REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning

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Analyzing PowerMOS Devices to Reduce Power Loss and Improve Reliability

REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation

REPLAY: Avoiding CDM (Charged Device Model) ESD Failures

REPLAY: eFPGA – "What a great idea! But I have no idea how I’d use it!"

REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification

REPLAY: Fabless: The Transformation of the Semiconductor Industry

REPLAY: The Brave New World of Customized Memory

REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning

REPLAY: VLSI Design Methodology Development

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REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats?

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REPLAY: Taiwan ESD Workshop Recording

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REPLAY: PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior

REPLAY: Thermal-induced Reliability Challenges and Solutions for Advanced IC Design

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November 28, 2019November 28, 2019

Webinar Recap: IP Security Threats in your SoC

Webinar Recap: IP Security Threats in your SoC
by Daniel Payne on 11-28-2019 at 10:00 am
Categories: EDA, Events, Methodics

Three years ago my youngest son purchased a $17 smart watch on eBay, but then my oldest son read an article warning about how that watch would sync with your phone, then send all of your contact info to an address in China. My youngest son then wisely turned the watch off, and never used it again. Hackers have been able to spoof and hide … Read More

November 27, 2019November 27, 2019

Webinar Recap: Challenges of Autonomous Vehicle Validation

Webinar Recap: Challenges of Autonomous Vehicle Validation
by Daniel Payne on 11-27-2019 at 10:00 am
Categories: Automotive, EDA, Mentor, a Siemens Business

Autonomous vehicle progress is in the daily news, so it’s quite exciting to watch it develop with the help of SoC design, sensors, actuators and software from engineering teams spanning the entire globe. Tesla vehicles have reached Level 2 autonomy, Audi e-tron is at Level 3, and Waymo nearly at Level 5 with robot taxis being… Read More

November 13, 2019November 12, 2019

Functional Safety Comes to EDA and IP

Functional Safety Comes to EDA and IP
by Daniel Payne on 11-13-2019 at 10:00 am
Categories: Accellera, Semiconductor Services

Every week I read headlines about the progress of autonomous vehicles, and the inevitable questions began to arise, like, “Just how safe is this AV?”, or “Is this new ADAS feature trustworthy?” The automotive industry has already setup the ISO 26262 functional safety standard, and we’ve blogged… Read More

November 8, 2019November 6, 2019

Mentor Adds Circuit Simulators to the Cloud using Azure

Mentor Adds Circuit Simulators to the Cloud using Azure
by Daniel Payne on 11-08-2019 at 6:00 am
Categories: Mentor, a Siemens Business

Most EDA tools started out running on mainframe computers, then minicomputers, followed by workstations and finally desktop PCs running Linux. If your SoC design team is working on a big chip with over a billion transistors, then your company likely will use a compute farm to distribute some of the more demanding IC jobs over lots… Read More

October 28, 2019October 27, 2019

DAC 2020 – Call for Contributions

DAC 2020 – Call for Contributions
by Daniel Payne on 10-28-2019 at 6:00 am
Categories: EDA, Events
1 Comment

My first DAC was in 1987 so I’ve seen our industry expand greatly over the years, and I expect that #57DAC on July 19-23, 2020 in SFO to be another exciting event to attend for semiconductor professionals from around the globe. What makes DAC so compelling for me to visit are the people, exhibitors, panel discussions, technical… Read More

October 16, 2019October 13, 2019

Automating Timing Arc Prediction for AMS IP using ML

Automating Timing Arc Prediction for AMS IP using ML
by Daniel Payne on 10-16-2019 at 6:00 am
Categories: EDA, Empyrean

NVIDIA designs some of the most complex chips for GPU and AI applications these days, with SoCs exceeding 21 billion transistors. They certainly know how to push the limits of all EDA tools, and they have a strong motivation to automate more manual tasks in order to quicken their time to market. I missed their Designer/IP Track Poster… Read More

October 4, 2019October 9, 2019

Workflow Automation Applied to IP Lifecycle Management

Workflow Automation Applied to IP Lifecycle Management
by Daniel Payne on 10-04-2019 at 10:00 am
Categories: EDA, Methodics

I often blog about a specific EDA tool, or an IP block, but the way that SoC design teams approach their designs and then use tools and IP can either be a manual, ad-hoc process, or part of something that is well-documented, following a design methodology. Back in the 1980’s while at Intel our team first created a design methodology… Read More

October 2, 2019October 3, 2019

Debugging SoCs at the RTL, Gate and SPICE Netlist Levels

Debugging SoCs at the RTL, Gate and SPICE Netlist Levels
by Daniel Payne on 10-02-2019 at 10:00 am
Categories: Concept Engineering, EDA, Events

Debugging an IC is never much fun because of all the file formats used, the levels of hierarchy and just the sheer design size, so when an EDA tool comes around that allows me to get my debugging done quicker, then I take notice and give it a look. I was already familiar with debugging SPICE netlists using a tool called SPICEVision Pro,… Read More

September 19, 2019October 3, 2019

Speeding Up Physical Failure Analysis (PFA)

Speeding Up Physical Failure Analysis (PFA)
by Daniel Payne on 09-19-2019 at 10:00 am
Categories: EDA, Mentor, a Siemens Business

The cost of an IC depends on many factors like: NRE, masks, fabrication, testing, packaging. Product engineers are tasked with testing each part and understanding what exactly is limiting the yields. Every company has a methodology for Physical Failure Analysis (PFA), and the challenge is to make this process as quick as possible,… Read More

August 30, 2019September 17, 2019

3D TCAD Simulation for Power Devices

3D TCAD Simulation for Power Devices
by Daniel Payne on 08-30-2019 at 10:00 am
Categories: EDA, Silvaco

My first IC design back in 1978 was a DRAM and it ran on 12V, 5V and -5V, but then my second DRAM was using only a 5V supply. Today we see SOCs running under a 1V supply voltage, but there is a totally different market for power devices that are at the other end of the voltage spectrum and they handle switching ranges from 12V – 250V. … Read More

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Threads

Recent Forum Threads

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started by Daniel Nenni on December 11, 2019
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Author: Daniel Payne

Webinar Recap: IP Security Threats in your SoC

Webinar Recap: Challenges of Autonomous Vehicle Validation

Functional Safety Comes to EDA and IP

Mentor Adds Circuit Simulators to the Cloud using Azure

DAC 2020 – Call for Contributions

Automating Timing Arc Prediction for AMS IP using ML

Workflow Automation Applied to IP Lifecycle Management

Debugging SoCs at the RTL, Gate and SPICE Netlist Levels

Speeding Up Physical Failure Analysis (PFA)

3D TCAD Simulation for Power Devices

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Recent Forum Threads

Intel hires former GlobalFoundries, IBM chip executive Dr. Gary Patton!

? on Packaging, Layers Replacing Node Shrink

Hong Kong Key to Tech

Qualcomm Moving Back to TSM

Pentagon Working with TSMC?

A Survey on Reliability of DNN Algorithms and Accelerators

EUV Shot Noise Impact on 7nm

Global Semiconductor Sales Increase 2.9 Percent Month-to-Month in October; Annual Sales Projected to Decrease 12.8 Percent in 2019

IC Insights Bulletin: NAND Flash to Lead All Others As IC Market Growth Returns in 2020

China lags far behind in semiconductor battle

Recent Article Comments

Intel vs AMD vs Google vs Amazon vs NUVIA

Bob Swan says Intel 7nm equals TSMC 5nm!

As 2019 comes to an end everyone is starting to look at what 2020 holds

Bob Swan says Intel 7nm equals TSMC 5nm!

As 2019 comes to an end everyone is starting to look at what 2020 holds

Intel vs AMD vs Google vs Amazon vs NUVIA

Bob Swan says Intel 7nm equals TSMC 5nm!

As 2019 comes to an end everyone is starting to look at what 2020 holds

Bob Swan says Intel 7nm equals TSMC 5nm!

Bob Swan says Intel 7nm equals TSMC 5nm!