Viewing the Largest IC Layout Files Quickly

Viewing the Largest IC Layout Files Quickly
by Daniel Payne on 03-10-2020 at 6:00 am

Skipper, Empyrean

The old adage, “Time is money”, certainly rings true today for IC designers, so the entire EDA industry has focused on this challenging goal of making tools that help speed up design and physical verification tasks like DRC (Design Rule Checks) and LVS (Layout Versus Schematic). Sure, the big three EDA vendors have… Read More


DVCon Is a Must Attend Event for Design and Verification Engineers

DVCon Is a Must Attend Event for Design and Verification Engineers
by Daniel Payne on 02-03-2020 at 10:00 am

dvcon 2020

Learning is a never-ending process for design and verification engineers, so outside of reading SemiWiki you likely want to attend at least a few events per year to keep updated, learn something new, attend a workshop, or even present something that has made your IC project work much better than before. Sure, DAC is always a great… Read More


Cycling and CES 2020

Cycling and CES 2020
by Daniel Payne on 01-16-2020 at 10:00 am

eflow min

It’s a new year, so time to share with you all things cycling being shown at CES. Yes, most of CES is devoted to new TV displays, futuristic automobiles, all things 5G, laptops and mobile phones, but there’s a growing segment of consumer products for fitness, and cycling happens to be my fitness passion. Riding a bike … Read More


Saving Time in Physical Verification by Reusing Metadata

Saving Time in Physical Verification by Reusing Metadata
by Daniel Payne on 01-08-2020 at 10:00 am

voltage propagation cross reference data min

Physical verification is an important and necessary step in the process to tapeout an IC design, and the foundries define sign-off qualification steps for:

  • Physical validation
  • Circuit validation
  • Reliability verification

This sounds quite reasonable until you actually go through the steps only to discover that some of the … Read More


Avoiding Fines for Semiconductor IP Leakage

Avoiding Fines for Semiconductor IP Leakage
by Daniel Payne on 12-24-2019 at 10:00 am

Percipient IPLM

In my semiconductor and EDA travels I’ve enjoyed visiting engineers across the USA, Canada, Europe, Japan, Taiwan and South Korea. I’ll never forget on one trip to South Korea where I was visiting a semiconductor company and upon reaching the lobby a security officer asked me to take out my laptop computer, because he wanted me to… Read More


Another Smart EDA Merger Adds RF Tools

Another Smart EDA Merger Adds RF Tools
by Daniel Payne on 12-12-2019 at 10:00 am

Cadence acquires AWR

Mergers and acquisitions are just a fact of modern business life, so the semiconductor, IP and EDA industries all can benefit, but only when the two companies have complementary products with some actual synergy. Cadence acquired OrCAD back in 1999, adding a Windows-based PCB tool to their product lineup, and here in 2019 some … Read More


Webinar Recap: IP Security Threats in your SoC

Webinar Recap: IP Security Threats in your SoC
by Daniel Payne on 11-28-2019 at 10:00 am

Methodics Security SoC

Three years ago my youngest son purchased a $17 smart watch on eBay, but then my oldest son read an article warning about how that watch would sync with your phone, then send all of your contact info to an address in China. My youngest son then wisely turned the watch off, and never used it again. Hackers have been able to spoof and hide Read More


Webinar Recap: Challenges of Autonomous Vehicle Validation

Webinar Recap: Challenges of Autonomous Vehicle Validation
by Daniel Payne on 11-27-2019 at 10:00 am

Waymo Jaguar

Autonomous vehicle progress is in the daily news, so it’s quite exciting to watch it develop with the help of SoC design, sensors, actuators and software from engineering teams spanning the entire globe. Tesla vehicles have reached Level 2 autonomy, Audi e-tron is at Level 3, and Waymo nearly at Level 5 with robot taxis being… Read More


Functional Safety Comes to EDA and IP

Functional Safety Comes to EDA and IP
by Daniel Payne on 11-13-2019 at 10:00 am

Every week I read headlines about the progress of autonomous vehicles, and the inevitable questions began to arise, like, “Just how safe is this AV?”, or “Is this new ADAS feature trustworthy?” The automotive industry has already setup the ISO 26262 functional safety standard, and we’ve bloggedRead More


Mentor Adds Circuit Simulators to the Cloud using Azure

Mentor Adds Circuit Simulators to the Cloud using Azure
by Daniel Payne on 11-08-2019 at 6:00 am

Mentor and Azure

Most EDA tools started out running on mainframe computers, then minicomputers, followed by workstations and finally desktop PCs running Linux. If your SoC design team is working on a big chip with over a billion transistors, then your company likely will use a compute farm to distribute some of the more demanding IC jobs over lots… Read More