Joseph Sawicki of Siemens EDA at User2User

Joseph Sawicki of Siemens EDA at User2User
by Daniel Payne on 05-19-2022 at 10:00 am

Joseph Sawicki

I attended the annual user group meeting called User2User in Santa Clara this year, hosted by Siemens EDA, with 51 presentations by customers in 11 tracks, and keynotes during each lunch hour from semiconductor executives. Joseph Sawicki, Executive VP, IC Segment, at Siemens EDA presented on a Tuesday, along with Prashant Varshney,… Read More


Cybersecurity Threat Detection and Mitigation

Cybersecurity Threat Detection and Mitigation
by Daniel Payne on 05-16-2022 at 10:00 am

Embedded Analytics min

Every week in the technology trade press I am reading about cybersecurity attacks against web sites, apps, IoT devices, vehicles and even ICs. At the recent IP SoC Silicon Valley 2022 event in April I watched a cybersecurity  presentation from Robert Rand, Solution Architect for Tessent Embedded Analytics at Siemens EDA. Common… Read More


High-speed, low-power, Hybrid ADC at IP-SoC

High-speed, low-power, Hybrid ADC at IP-SoC
by Daniel Payne on 05-10-2022 at 10:00 am

hybrid adc min

Andrew Levy and I both worked at Intel and Opmaxx, and I knew that he was now working at Alphacore, an IP company specializing in mixed-signal, RF, imaging and rad-hard applications. I was curious what Alphacore was up to, so at the IP-SoC Silicon Valley 2022 event I watched the ADC presentation from Ken Potts, COO of Alphacore. Mr.… Read More


Designing Ultra-Low-Power, Always On IP

Designing Ultra-Low-Power, Always On IP
by Daniel Payne on 05-09-2022 at 10:00 am

processor and sensor trends min

It’s popular to use DSP chips for vision processing in diverse applications like ADAS, security cameras and AR. Tensilica has been designing DSP chips and IP since 1997, and their technology was successful enough that Cadence acquired Tensilica back in 2013. At the IP-SoC Silicon Valley 2022 event in April I had the pleasure… Read More


Efficient Memory BIST Implementation

Efficient Memory BIST Implementation
by Daniel Payne on 05-05-2022 at 10:00 am

Figure 1 min

Test experts use the acronym BIST for Built In Self Test, it’s the test logic added to an IP block that speeds up the task of testing by creating stimulus and then looking at the output results. Memory IP is a popular category for SoC designers, as modern chips include multiple memory blocks for fast, local data and register storage… Read More


IP Subsystems and Chiplets for Edge and AI Accelerators

IP Subsystems and Chiplets for Edge and AI Accelerators
by Daniel Payne on 05-02-2022 at 10:00 am

Scalable Chiplet Platform min

From a business viewpoint we often read in the technical press about the virtues of applying AI, and in the early days most of the AI model building was done in the cloud, because of the high computation requirements, yet there’s a developing trend now to use AI accelerators at the Edge. The other mega-trend in the past decade… Read More


Freemium Business Model Applied to Analog IC Layout Automation

Freemium Business Model Applied to Analog IC Layout Automation
by Daniel Payne on 04-28-2022 at 10:00 am

animate preview min

Freemium is the two words “free” and “premium” combined together, and many of us have enjoyed using freemium apps on our phones, tablets and desktop devices over the years. The concept is quite simple, you find an app that is useful, and download the free version, mostly to see if it operates as advertised,… Read More


Data Processing Unit (DPU) uses Verification IP (VIP) for PCI Express

Data Processing Unit (DPU) uses Verification IP (VIP) for PCI Express
by Daniel Payne on 03-29-2022 at 10:00 am

Fungible min

Domain specific processors are a mega-trend in the semiconductor industry, so we see new three letter acronyms like DPU, for Data Processing Unit. System level performance can actually be improved by moving some of the tasks away from the CPU. Companies like Xilinx (Alveo), Amazon (Nitro) and NVIDIA (BlueField) have been talking… Read More


Webinar: Beyond the Basics of IP-based Digital Design Management

Webinar: Beyond the Basics of IP-based Digital Design Management
by Daniel Payne on 03-08-2022 at 10:00 am

Digital Design Flow

According to the ESD Alliance, the single biggest revenue category in our industry is for semiconductor IP, so the concept of IP reuse is firmly established as a way to get complex products to market more quickly and reducing risk. On the flip side, with hundreds or even thousands of IP blocks in a complex SoC, how does a team, division… Read More


Analog IC Layout Automation Benefits

Analog IC Layout Automation Benefits
by Daniel Payne on 03-07-2022 at 10:00 am

Differential Pair Schematic

I viewed a recent webinar from Paul Clewes of Pulsic, and the topic was Balancing Analog Layout Parasitics in MOSFET Differential Pairs. This topic interests me, because back in 1982 I wrote my first IC layout automation tool at Intel that automatically created 15% of a GPU chip layout called the 82786, then joined Silicon Compilers… Read More