Fast EM/IR Analysis, a new EDA Category

Fast EM/IR Analysis, a new EDA Category
by Daniel Payne on 08-09-2022 at 6:00 am

IR Drop min

I’ve watched the SPICE market segment into multiple approaches, like: Classic SPICE, Parallel SPICE, FastSPICE and Analog FastSPICE. In a similar fashion the same thing just happened to EM/IR analysis, because after years of waiting we finally have a different approach to EM/IR analysis that works at the top-level of … Read More


EDA in the Cloud with Siemens EDA at #59DAC

EDA in the Cloud with Siemens EDA at #59DAC
by Daniel Payne on 08-01-2022 at 10:00 am

craig johnson

Tuesday at DAC I had the pleasure of attending the Design on Cloud Theatre where experts from Siemens EDA gave an update on what they’ve been offering to IC and systems designers. I remember attending a cloud presentation from Craig Johnson in 2021, so I was keen to note what had changed in the past 12 months.

Industry Trends,

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Axiomise at #59DAC, Formal Update

Axiomise at #59DAC, Formal Update
by Daniel Payne on 07-27-2022 at 10:00 am

Dr. Ashish Darbari min 1

Monday at DAC I was able to meet with Dr. Ashish Darbari, the CEO and founder of Axiomise. Ashish had a busy DAC, appearing as a panelist at,  “Those Darn Bugs! When Will They be Exterminated for Good?”; and then presenting,  “Taming the Beast: RISC-V Formal Verification Made Easy.”

I had read a bit about Axiomise… Read More


Calibre, Google and AMD Talk about Surge Compute at #59DAC

Calibre, Google and AMD Talk about Surge Compute at #59DAC
by Daniel Payne on 07-25-2022 at 10:00 am

Google Cloud vendor of the year min

In 2022 using the cloud for EDA tasks is a popular topic, and at DAC this year I could see a bigger presence from the cloud hardware vendors in the exhibit area, along with a growing stampede of EDA companies. Tuesday at DAC there was a luncheon with experts from Siemens EDA, Google and AMD talking about surge compute. I already knew Michael… Read More


New Mixed-Signal Simulation Features from Siemens EDA at DAC

New Mixed-Signal Simulation Features from Siemens EDA at DAC
by Daniel Payne on 07-13-2022 at 10:00 am

Symphony Pro for mixed-signal verification

It’s the second day of DAC, and the announcements are coming in at a fast pace, so stay tuned to SemiWiki for all of the latest details. As a long-time SPICE user and industry follower, I’ve witnessed the progression as EDA vendors have connected their SPICE simulators to digital simulators, opening up a bigger world… Read More


What’s New With Calibre at DAC This Year?

What’s New With Calibre at DAC This Year?
by Daniel Payne on 07-12-2022 at 9:00 am

whats changed min

When I worked at EDA vendors and attended DAC, one of the most popular questions asked in the booth and suites was simply, “What’s new this year?” It’s a fair question, and yet many semiconductor professionals are so focused on their present project, using their familiar methodology, that they simply… Read More


Using AI in EDA for Multidisciplinary Design Analysis and Optimization

Using AI in EDA for Multidisciplinary Design Analysis and Optimization
by Daniel Payne on 07-04-2022 at 10:00 am

Optimality min

Most IC and system engineers follow a familiar process when designing a new product: create a model, use parameters for the model, simulate the model, observe the results, compare results versus requirements, change the parameters or model and repeat until satisfied or it’s time to tape out. On the EDA side, most tools perform… Read More


Using IP-XACT, RTL and UPF for Efficient SoC Design

Using IP-XACT, RTL and UPF for Efficient SoC Design
by Daniel Payne on 06-30-2022 at 6:00 am

ESDA Revenue

The ESD Alliance collects and reports every quarter the revenue trends for both EDA and Semiconductor IP (SiP), and the biggest component for the past few years has been the SiP, as IP re-use dominates new designs. For Q4 of 2021 the total SiP revenue was $1,314.3 Million, enjoying a 24.8% growth in just one year. Here’s a chart… Read More


Using STA with Aging Analysis for Robust IC Designs

Using STA with Aging Analysis for Robust IC Designs
by Daniel Payne on 06-23-2022 at 10:00 am

Gate Level Aging min

Our laptops and desktop computers have billions of transistors in their application processor chips, yet I often don’t consider the reliability effects of aging that the transistors experience in the chips. At the recent Synopsys User Group (aka SNUG), there was a technical presentation on this topic from Srinivas Bodapati,… Read More


Using EM/IR Analysis for Efinix FPGAs

Using EM/IR Analysis for Efinix FPGAs
by Daniel Payne on 05-30-2022 at 10:00 am

XLR min

I’ve been following the EM/IR (Electro-Migration, IR is current and resistance) analysis market for many years now, and recently attended a presentation from Steven Chin, Sr. Director IC Engineering of Efinix, at the User2User event organized by Siemens EDA. The Tuesday presentation was in the morning at the Marriott… Read More