I first met Jimmy Chen from Easy-Logic at #60DAC and wrote about their Engineering Change Order (ECO) tool in August 2023. Recently we had a Zoom call so that I could see a live demo of their EDA tool in action. Allen Guo, the AE Manager for Easy-Logic gave me an overview presentation of the company and some history to provide a bit of context.… Read More
Author: Daniel Payne
ECO Demo Update from Easy-Logic
Electrical Rule Checking and Exhaustive Classification of Errors
The goal of SoC design teams is to tape-out their project and receive working silicon on the first try, without discovering any bugs in silicon. To achieve this lofty goal requires all types of specialized checking and verification during the design phase to prevent bugs. There are checks at the system level, RTL level, gate level,… Read More
A Modeling, Simulation, Exploration and Collaborative Platform to Develop Electronics and SoCs
During the GOMACTech conference held in South Carolina last week I had a Zoom call with Deepak Shankar, Founder and VP Technology at Mirabilis Design Inc. to ask questions and view a live demo of VisualSim – a modeling, simulation, exploration and collaborative platform to develop electronics and SoCs. What makes VisualSim so … Read More
Afraid of mesh-based clock topologies? You should be
Digital logic chips synchronize all logic operations by using a clock signal connected to flip-flops or latches, and the clock is distributed across the entire chip. The ultimate goal is to have a clock signal that arrives at the exact same moment in time at all clocked elements. If the clock arrives too early or too late from the PLL… Read More
Checking and Fixing Antenna Effects in IC Layouts
IC layouts go through extensive design rule checking to ensure correctness, before being accepted for fabrication at a foundry or IDM. There’s something called the antenna effect that happens during chip manufacturing where plasma-induced damage (PID) can lower the reliability of MOSFET devices. Layout designers run Design… Read More
Soft checks are needed during Electrical Rule Checking of IC layouts
IC designs have physical verification applications like Layout Versus Schematic (LVS) at the transistor-level to ensure that layout and schematics are equivalent, in addition there’s an Electrical Rules Check (ERC) for connections to well regions called a soft check. The connections to all the devices needs to have the most… Read More
New Emulation, Enterprise Prototyping and FPGA-based Prototyping Launched
General purpose CPUs have run most EDA tools quite well for many years now, but if you really want to accelerate something like simulation then you start to look at using specializedhardware accelerators. . Emulators came onto the scene around 1986 and the processing power has greatly increased over the years, mostly in response… Read More
AI and SPICE Circuit Simulation Applications
Can you name the EDA vendor that first used AI starting 15 years ago for circuit designers using SPICE simulators? I can remember that vendor, it was Solido, now part of Siemens EDA, and I just read their 8 page paper on how they look at the various levels of AI being used in EDA to help IC designers work smarter and faster than using manual… Read More
Mastering Mixed-Signal Verification with Siemens Symphony Platform
Digital design and verification is well understood by EDA vendors and IC designers, however mixed-signal design and verification is more challenging, because the continuous nature of analog signals requires more compute resources and specialized design skills. Siemens EDA has a unique offering in what they call Symphony… Read More
CES 2024 and all things Cycling
From the comfort of my home office I attended CES 2024 virtually this week, and collected all the news for cyclists, and it’s mostly all about e-bikes. The total count of e-bike sales now even outnumber EV car sales worldwide, so that growth trend continues. Some 85% of all bikes sold in China are now e-bikes.
e-bikes
This single… Read More
Real men have fabs!