Afraid of mesh-based clock topologies? You should be

Afraid of mesh-based clock topologies? You should be
by Daniel Payne on 03-18-2024 at 10:00 am

mesh-based clock topology

Digital logic chips synchronize all logic operations by using a clock signal connected to flip-flops or latches, and the clock is distributed across the entire chip. The ultimate goal is to have a clock signal that arrives at the exact same moment in time at all clocked elements. If the clock arrives too early or too late from the PLL… Read More


Checking and Fixing Antenna Effects in IC Layouts

Checking and Fixing Antenna Effects in IC Layouts
by Daniel Payne on 03-14-2024 at 10:00 am

Planar CMOS cross-section – antenna DRC

IC layouts go through extensive design rule checking to ensure correctness, before being accepted for fabrication at a foundry or IDM. There’s something called the antenna effect that happens during chip manufacturing where plasma-induced damage (PID) can lower the reliability of MOSFET devices. Layout designers run Design… Read More


Soft checks are needed during Electrical Rule Checking of IC layouts

Soft checks are needed during Electrical Rule Checking of IC layouts
by Daniel Payne on 02-28-2024 at 10:00 am

Metal1 Via Metal2 s

IC designs have physical verification applications like Layout Versus Schematic (LVS) at the transistor-level to ensure that layout and schematics are equivalent, in addition there’s an Electrical Rules Check (ERC) for connections to well regions called a soft check. The  connections to all the devices needs to have the most… Read More


New Emulation, Enterprise Prototyping and FPGA-based Prototyping Launched

New Emulation, Enterprise Prototyping and FPGA-based Prototyping Launched
by Daniel Payne on 02-26-2024 at 10:00 am

Veloce Strato CS min

General purpose CPUs have run most EDA tools quite well for many years now, but if you really want to accelerate something like simulation then you start to look at using specializedhardware accelerators. . Emulators came onto the scene around 1986 and the processing power has greatly increased over the years, mostly in response… Read More


AI and SPICE Circuit Simulation Applications

AI and SPICE Circuit Simulation Applications
by Daniel Payne on 01-24-2024 at 10:00 am

Figure 1 min

Can you name the EDA vendor that first used AI starting 15 years ago for circuit designers using SPICE simulators? I can remember that vendor, it was Solido, now part of Siemens EDA, and I just read their 8 page paper on how they look at the various levels of AI being used in EDA to help IC designers work smarter and faster than using manual… Read More


Mastering Mixed-Signal Verification with Siemens Symphony Platform

Mastering Mixed-Signal Verification with Siemens Symphony Platform
by Daniel Payne on 01-17-2024 at 10:00 am

verification platform min

Digital design and verification is well understood by EDA vendors and IC designers, however mixed-signal design and verification is more challenging, because the continuous nature of analog signals requires more compute resources and specialized design skills. Siemens EDA has a unique offering in what they call SymphonyRead More


CES 2024 and all things Cycling

CES 2024 and all things Cycling
by Daniel Payne on 01-11-2024 at 10:00 am

UrbanCross min

From the comfort of my home office I attended CES 2024 virtually this week, and collected all the news for cyclists, and it’s mostly all about e-bikes. The total count of e-bike sales now even outnumber EV car sales worldwide, so that growth trend continues. Some 85% of all bikes sold in China are now e-bikes.

e-bikes

This single… Read More


Keysight EDA Connect World Tour

Keysight EDA Connect World Tour
by Daniel Payne on 01-08-2024 at 6:00 am

RF System Explorer min

Video webinars are a main staple to learn what’s new about EDA tools and methodologies, but there’s nothing quite like meeting in person, where you can ask questions and gauge the expertise of the presenters. I was delighted to learn that Keysight is planning a literal world tour to update EDA customers and prospects on what they … Read More


Making UVM faster through a new configuration system

Making UVM faster through a new configuration system
by Daniel Payne on 12-26-2023 at 10:00 am

Elapsed Time min

The Universal Verification Methodology (UVM) is a popular way to help verify SystemVerilog designs, and it includes a configuration system that unfortunately has some speed and usage issues. Rich Edelman from Siemens EDA wrote a detailed 20-page paper on the topic of how to avoid these issues, and I’ve gone through it to… Read More


Using PCB Automation for an AI and Machine Vision Product

Using PCB Automation for an AI and Machine Vision Product
by Daniel Payne on 12-12-2023 at 10:00 am

machine vision testing

I knew that HDMI was a popular standard used to connect consumer products like a monitor to a laptop, but most professional video and broadcast systems use the SDI (Serial Digital Interface) connector standard. Pleora Technologies, founded in 2000, currently serves the machine vision and manufacturing markets, including those… Read More