On the last day of #DAC2026 I stopped by the Keysight booth to chat with Nilesh Kamdar, GM of EDA Business to get an update. He has spent 27 years in the industry, and this made 25 DAC trips for him. For Keysight the application areas of focus are serving designers of high frequency and high-speed digital, RF, and mm/uwave designs. An … Read More
Author: Daniel Payne
Keysight EDA update at DAC 2026
AI Memory Gap at DAC 2026
On Tuesday at #DAC2026 I attended the exhibitor presentation, Synopsys: How Silicon Startups are Addressing the AI Memory Gap. Vikram Bhatia from Synopsys introduced the two presentations from Wenbo Yin, SVP of IC Design at TetraMem and R. Scott Hills, VP of Business Development at ANAFLASH. Datacenters consume large amounts… Read More
Synopsys Cloud at DAC 2026
Cloud-based EDA has been around for awhile now, so at #DAC2026 I met with Vikram Bhatia, Executive Director of Synopsys Cloud to see what’s new with their offering. His background includes stints at Sun, IBM, Microsoft, HP, Oracle and NetApp. The Synopsys Cloud FlexEDA lets designs teams run their EDA solutions inside of a web browser,… Read More
Questa One Updated at DAC 2026
Abhi Kolpekwar, VP & General Manager, Digital Verification Technologies at Siemens EDA met with me at #DAC2026 to provide the big picture on smart verification tools, something they call Questa One. Their verification tools are infused with AI to improve productivity on projects like SoCs, 3D IC and chiplets. Abhi shared… Read More
Rise Design Automation at DAC 2026
AI was everywhere at DAC 2026, so I stopped by the booth of Rise Design Automation to chat with Ellie Burns to hear what’s new this year. Ellie shared that Rise DA has added a new AI-powered flow to go from specification to a High Level Synthesis (HLS) model, to a RTL model. The reason for using a HLS model is to gain much more simulation… Read More
Tuple Technologies at DAC 2026
At #DAC2026 I met with Vamshi Kothur at Tuple Technologies to see how their cloud infrastructure products help IC design teams get their chip designs to market more quickly without the overhead of big IT and CAD teams. Tuple was founded in 2017 and has grown to about 45 people, headquartered in New Jersey. The challenge of using complex… Read More
Siemens and NVIDIA tout Agentic AI
Siemens has EDA tools and flows, NVIDIA has AI infrastructure, so what happens when these two companies collaborate? I’m at DAC 2026 and all the buzz this year is Agentic AI, so an came out on Sunday evening about how semiconductor and PCB design flows are being improved by this teamwork. Amit Gupta from Siemens and Timothy Costa from… Read More
Webinar: Faster Design Spec to Implementation using IP-XACT
As SoC design flows grow increasingly complex, IP-XACT has become a cornerstone standard throughout the entire development lifecycle: from architecture specification to design assembly and verification. Its growing adoption is reflected in the standard’s continuous evolution, from the 2009 release through 2014… Read More
What’s New at the 2026 DAC Exhibits
The most common question that I get each year at DAC is, “So, what’s new?” When I reviewed the exhibitor list I was pleasantly surprised to see how many EDA, IP and AI companies were attending that I didn’t know about. Here’s just a quick preview of what to expect in Long Beach from July 27-29. I’ll… Read More
Library Characterization gets a Boost from AI
The semiconductor industry creates increasingly complex SoC and chiplets using lots of IP and all of that IP needs to be characterized at the cell level. As we design with 3nm and 2nm nodes, the sheer volume of data required for accurate static timing analysis (STA) is greatly increasing. Modern design flows rely on characterized… Read More
ASML and TSMC’s 12-Inch Photomask Initiative: Technical Significance