APR Tool Gets a Speed Boost and Uses Less RAM

APR Tool Gets a Speed Boost and Uses Less RAM
by Daniel Payne on 10-18-2021 at 10:00 am

Aprisa

Automatic Place and Route (APR) tools have been around since the 1980s for IC design teams to use, and before that routing was done manually by very patient layout designers. Initially the big IDMs had their own internal CAD groups coding APR tools in house, but eventually the commercial EDA market picked up this automation area,… Read More


Webinar – Comparing ARM and RISC-V Cores

Webinar – Comparing ARM and RISC-V Cores
by Daniel Payne on 10-14-2021 at 10:00 am

Mirabilis Webinar, October 21

Operating systems and Instruction Set Architectures (ISA) can have long lifespans, and I’ve been an engineering user of many ISAs since the 1970s. For mobile devices I’ve followed the rise to popularity of the ARM architecture, and then more recently the RISC-V ISA which has successfully made the leap from university… Read More


High Reliability Power Management Chip Simulation and Verification for Automotive Electronics

High Reliability Power Management Chip Simulation and Verification for Automotive Electronics
by Daniel Payne on 10-11-2021 at 10:00 am

iWave waveform min

Automotive electronics bring strong demand for power management chips, but its strict reliability requirements also pose new challenges for chip designers. The chip needs to be able to work in various harsh environments such as high temperature, low temperature, aging, abnormal power supply, etc. Although the traditional… Read More


Electromigration and IR Drop Analysis has a New Entrant

Electromigration and IR Drop Analysis has a New Entrant
by Daniel Payne on 09-28-2021 at 9:00 am

mPower capacity

My first IR drop analysis was back in the early 1980s at Intel, where I had to manually model the parasitics of the VDD and VSS interconnect for all of the IO cells that our team was designing in a graphics chip, then I ran that netlist in a SPICE simulator using transient analysis, measuring the bounce in VSS and droop in VDD levels as all… Read More


System-Level Modeling using your Web Browser

System-Level Modeling using your Web Browser
by Daniel Payne on 09-27-2021 at 10:00 am

VisualSim example

I’ve simulated IC designs at the transistor-level with SPICE, gate-level, RTL with Verilog, and even used cycle-based functional simulators. Sure, they each worked well, but only for the domain and purpose they were designed for. Industry analyst, Gary Smith predicted that the IC world would soon move to system-level… Read More


Webinar: AMS, RF and Digital Full Custom IC Designs need Circuit Sizing

Webinar: AMS, RF and Digital Full Custom IC Designs need Circuit Sizing
by Daniel Payne on 09-21-2021 at 10:00 am

circuit sizing min

My career started out by designing DRAM circuits at Intel, and we manually sized every transistor in the entire design to get the optimum performance, power and area. Yes, it was time consuming, required lots of SPICE iterations and was a bit error prone. Thank goodness that times have changed, and circuit designers can work smarter… Read More


What to expect at the 58th DAC this December

What to expect at the 58th DAC this December
by Daniel Payne on 09-16-2021 at 10:00 am

DAC

I’ve attended the DAC conference and trade show since the late 1980s, and every visit has been a continuing learning experience about the EDA, IP and semiconductor industry. I first started attended as an EDA vendor in 1987, and since 2004 as a freelance marketing professional. There’s a significant amount of preparation… Read More


Reliability Analysis for Mission-Critical IC design

Reliability Analysis for Mission-Critical IC design
by Daniel Payne on 09-13-2021 at 10:00 am

reliability analysis min

Mission-critical IC design for segments like automotive, aerospace, defense, medical and 5G have more stringent reliability analysis requirements than consumer electronics, and entails running special simulations for the following concerns:

  • Electromigration analysis
  • IR drop analysis
  • MOS aging
  • High-sigma Monte Carlo
Read More

AMS IC Designers need Full Tool Flows

AMS IC Designers need Full Tool Flows
by Daniel Payne on 08-31-2021 at 10:00 am

AMS tool flow min

Digital IC design gets a lot of attention, because all of our modern devices primarily use digital logic, but in reality whenever you have a sensor like a camera,  accelerometer, gyroscope or any radio like Bluetooth, WiFi or NFC, then you’re really in the realm of analog, and that’s where mixed-signal  IC design comes… Read More


Using Machine Learning to Improve EDA Tool Flow Results

Using Machine Learning to Improve EDA Tool Flow Results
by Daniel Payne on 08-25-2021 at 10:00 am

gajski kuhn

Back in 2020 I first learned from Synopsys about how they had engineered a better way to do optimize layouts on digital designs by using machine learning techniques, instead of relying upon manual approaches. The product was named DSO.ai, standing for Design Space Optimization, and it produced a more optimal floor-plan in less… Read More