Conference: Embedded DevOps

Conference: Embedded DevOps
by Daniel Payne on 01-07-2021 at 6:00 am

embedded devops min

The catchy phrase DevOps is defined by Agile advocates as, “The practice of operations and development engineers participating together in the entire service lifecycle, from design through the development process to production support.

I’ve been developing software since the stone ages, which means… Read More


Analysis of Curvilinear FPDs

Analysis of Curvilinear FPDs
by Daniel Payne on 12-31-2020 at 6:00 am

FPD voltage distribution analysis min

This area of automating the design of Flat Panel Displays (FPD) is so broad that it has taken me three blogs to cover all of the details, so in brief review the first two blogs were:

My final blog covers five areas:

  • DRC/LVS for curvilinear layout
  • Circuit
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Curvilinear FPD Layout and Schematics

Curvilinear FPD Layout and Schematics
by Daniel Payne on 12-03-2020 at 10:00 am

layout ladder min

You are likely reading this blog using a Flat Panel Display (FPD), because they are so ubiquitous in our desktop, tablet and smart phone devices. Today I’m following up from a previous article. A quick recap of the unique design flow for FPD is shown below:

What follows is the second part of a Q&A discussion with Chen Zhao… Read More


Third Generation of IP Lifecycle Management Launched

Third Generation of IP Lifecycle Management Launched
by Daniel Payne on 11-17-2020 at 10:00 am

Methodics and Perforce

Back in July I first read the news that Perforce had acquired Methodics, and wasn’t too surprised, because many of the EDA vendors that we blog about do get acquired or merge with similar sized companies in order to be part of a bigger offering. When Methodics announced a webinar introducing IPLM 3.0 (IP Lifecycle Management),… Read More


Automating the Design of Flat Panel Displays

Automating the Design of Flat Panel Displays
by Daniel Payne on 10-29-2020 at 10:00 am

Empyrean - FPD design flow

I’ve used OLED (Organic Light-Emitting Diode) displays for many years in my monitors, laptops, tablets, e-readers and smart phones; and knew that the AMOLED (Active-Matrix OLED) displays used thin-film transistor technology where each pixel can be controlled, but I hadn’t considered the actual design process… Read More


Automotive Upate at Arm DevSummit from VW

Automotive Upate at Arm DevSummit from VW
by Daniel Payne on 10-20-2020 at 10:00 am

audi etron

Although our family has down-sized to just one vehicle, my dream car is still a Tesla, both because it’s an EV and they have a vision for autonomous vehicles. At the recent Arm DevSummit I watched a fireside chat with Alexander Hitzinger, CEO of Artemis, the skunkworks at Audi, part of the Volkswagen Group.  I knew that Audi … Read More


WEBINAR: UVM RISC-V and DV

WEBINAR: UVM RISC-V and DV
by Daniel Payne on 09-21-2020 at 10:00 am

UVM Testbench RISC-V

Oh, our semiconductor industry just loves acronyms, and the title of my blog packs three of the most popular acronyms together at once. I attended a webinar hosted by Aldec last week on this topic, “UVM Simulation-based environment for Ibex RISC-V CPU core with Google RISC-V DV“. Verification engineers have been … Read More


Making Full Memory IP Robust During Design

Making Full Memory IP Robust During Design
by Daniel Payne on 08-28-2020 at 10:00 am

64Mb SRAM example, memory IP

Looking at a typical SoC design today it’s likely to contain a massive amount of memory IP, like: RAM, ROM, register files. Keeping memory close to the CPU makes sense for the lowest latency and highest performance metrics, but what about process variations affecting the memory operation? At the recent DAC conference held… Read More


Xilinx Moves from Internal Flow to Commercial Flow for IP Integration

Xilinx Moves from Internal Flow to Commercial Flow for IP Integration
by Daniel Payne on 08-25-2020 at 10:00 am

Xilinx IP min

I’ll never forget first learning about Xilinx when they got started back in 1984, because the concept of a Field Programmable Gate Array (FPGA) was so simple and elegant, it was rows and columns of logic gates that a designer could program to perform any logic function, then connect that logic to IO pads to drive other chips … Read More


#57DAC – Panel Discussion of High Level Synthesis

#57DAC – Panel Discussion of High Level Synthesis
by Daniel Payne on 07-28-2020 at 10:00 am

sean dart, Cadence

Presenters took a trip down memory lane at DAC this year by having a panel discussion on HLS (High Level Synthesis) spanning from 1974 to 2020, and that time period aligns with when I first graduated from the University of Minnesota in 1978, starting chip design at Intel, then later transitioning into EDA companies by 1986. MarilynRead More