Webinar: AMS, RF and Digital Full Custom IC Designs need Circuit Sizing

Webinar: AMS, RF and Digital Full Custom IC Designs need Circuit Sizing
by Daniel Payne on 09-21-2021 at 10:00 am

circuit sizing min

My career started out by designing DRAM circuits at Intel, and we manually sized every transistor in the entire design to get the optimum performance, power and area. Yes, it was time consuming, required lots of SPICE iterations and was a bit error prone. Thank goodness that times have changed, and circuit designers can work smarter… Read More


What to expect at the 58th DAC this December

What to expect at the 58th DAC this December
by Daniel Payne on 09-16-2021 at 10:00 am

DAC

I’ve attended the DAC conference and trade show since the late 1980s, and every visit has been a continuing learning experience about the EDA, IP and semiconductor industry. I first started attended as an EDA vendor in 1987, and since 2004 as a freelance marketing professional. There’s a significant amount of preparation… Read More


Reliability Analysis for Mission-Critical IC design

Reliability Analysis for Mission-Critical IC design
by Daniel Payne on 09-13-2021 at 10:00 am

reliability analysis min

Mission-critical IC design for segments like automotive, aerospace, defense, medical and 5G have more stringent reliability analysis requirements than consumer electronics, and entails running special simulations for the following concerns:

  • Electromigration analysis
  • IR drop analysis
  • MOS aging
  • High-sigma Monte Carlo
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AMS IC Designers need Full Tool Flows

AMS IC Designers need Full Tool Flows
by Daniel Payne on 08-31-2021 at 10:00 am

AMS tool flow min

Digital IC design gets a lot of attention, because all of our modern devices primarily use digital logic, but in reality whenever you have a sensor like a camera,  accelerometer, gyroscope or any radio like Bluetooth, WiFi or NFC, then you’re really in the realm of analog, and that’s where mixed-signal  IC design comes… Read More


Using Machine Learning to Improve EDA Tool Flow Results

Using Machine Learning to Improve EDA Tool Flow Results
by Daniel Payne on 08-25-2021 at 10:00 am

gajski kuhn

Back in 2020 I first learned from Synopsys about how they had engineered a better way to do optimize layouts on digital designs by using machine learning techniques, instead of relying upon manual approaches. The product was named DSO.ai, standing for Design Space Optimization, and it produced a more optimal floor-plan in less… Read More


SoC Vulnerabilities

SoC Vulnerabilities
by Daniel Payne on 07-29-2021 at 6:00 am

side channel attack

As I read both the popular and technical press each week I often see articles about computer systems being hacked, and here’s just a few vulnerabilities from this week:

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Automotive Safety Island: Test, Safety, Security, ISO 26262

Automotive Safety Island: Test, Safety, Security, ISO 26262
by Daniel Payne on 07-12-2021 at 10:00 am

functional safety

I first fell in love with electric vehicles back in 1978 as an Electrical Engineering student, studying at the University of Minnesota. What caught my fancy was a small advertisement listed in the back of Popular Mechanics magazine to build your own electric vehicle by replacing the gas engine of a Honda with an electric motor, so… Read More


Webinar: Learn about NVMe conformance Testing

Webinar: Learn about NVMe conformance Testing
by Daniel Payne on 06-29-2021 at 6:00 am

QEMU min

Several years ago I recall upgrading my aging MacBook Pro laptop from using a Hard Disk Drive (HDD) to a Solid State Drive (SSD) that used Non-Volatile Memory (NVM). Oh what a speed improvement when pushing that On button each morning to start the work day, or clicking an App to see it launch without delay. Another epiphany for me in … Read More


Circuit Simulation Challenges to Design the Xilinx Versal ACAP

Circuit Simulation Challenges to Design the Xilinx Versal ACAP
by Daniel Payne on 06-24-2021 at 10:00 am

xilinx versal acap min

One of the most unique acronyms that I learned about this past year is ACAP from Xilinx, which stands for Adaptive Compute Acceleration Platform. At the recent Cadence LIVE event, I had the pleasure of watching Pei Yao, a Xilinx senior staff CAD engineer, as she talked about the challenges of getting all the analog and mixed-signals… Read More


EDA Design and Amazon Web Services (AWS)

EDA Design and Amazon Web Services (AWS)
by Daniel Payne on 06-21-2021 at 10:00 am

EC2 min

I first remember blogging about EDA in the cloud starting back in 2011, so what’s changed in the last 10 years you may ask? In 2011, it was basically a handful of EDA point tools running batch mode in the cloud, and you were on your own to integrate those into a coherent flow, so expect help from the CAD and IT departments for sure.… Read More