WP_Term Object
(
    [term_id] => 101
    [name] => Empyrean
    [slug] => empyrean
    [term_group] => 0
    [term_taxonomy_id] => 101
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 15
    [filter] => raw
    [cat_ID] => 101
    [category_count] => 15
    [category_description] => 
    [cat_name] => Empyrean
    [category_nicename] => empyrean
    [category_parent] => 157
)
            
Empyrean Logo SemiWiki
WP_Term Object
(
    [term_id] => 101
    [name] => Empyrean
    [slug] => empyrean
    [term_group] => 0
    [term_taxonomy_id] => 101
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 15
    [filter] => raw
    [cat_ID] => 101
    [category_count] => 15
    [category_description] => 
    [cat_name] => Empyrean
    [category_nicename] => empyrean
    [category_parent] => 157
)

Speed Up LEF Generation Times on Huge IC Designs

Speed Up LEF Generation Times on Huge IC Designs
by Daniel Payne on 06-03-2021 at 10:00 am

For IC designs there are many data formats used throughout the logical and physical design process, and one of those file formats is called LEF, an acronym for Library Exchange Format, created by Tangent, an early EDA company with Place and Route tools that was acquired by Cadence way back in March 1989. LEF generation times can become prohibitive to meeting schedules. Historic side note: I worked at Silicon Compilers in the 1980s and we considered acquiring Tangent, but our VP of Marketing decided against it.

The LEF format has details about cells used in IC design, like:

  • Cell name
  • Site name
  • Orientation
  • PR boundary
  • Pins
  • Antenna parameters
  • Layers
  • Metal tracks
  • Obstruction extraction for PR tools

The size of the LEF file is smaller than GDS II or OASIS formats, but the challenge comes when it’s time to generate a LEF file. For the largest SoC designs you may be waiting tens of hours for the LEF file just to be generated. Here’s a visual comparison of an inverter cell in both GDS II and LEF formats:

GDSII and LEF min

As process technology advances and use double, triple and quad patterning, then the LEF generation times continue to grow. The team at EDA vendor Empyrean is well-known for their Skipper tool, used in layout analysis and chip finishing tasks like LEF generation.

skipper min

I met with Shanshan Dong and Chen Zhao of Empyrean by Zoom this month to get up to speed on the LEF generation in Skipper. You can use the LEF generator in either GUI or batch mode, it depends on your preferences, and the tool extracts the pins and OBS from the layout automatically. One of the reliability issues with smaller process nodes is the antenna effect, so having a tool that calculate the antenna parameter for you is a real time saver, plus it ensures that your fabricated chip will yield better and not fail from ESD discharge.

A fully routed design is required for creating a LEF with the antenna parameters. To give you an idea of just how fast the LEF generation is with Skipper, take a look at three actual layouts using 5nm to 16nm processes:

 

Case Layout Size (G) Pin # Time (s)
5nm 4+ 9,000+ 1,800
7nm 4.5 2,630 8,600
7nm 2.1 1,380 3,704
16nm 0.5 521 40

 

In under 2.5 hours you can generate a LEF file with 2,603 pins, while other tools struggle or fail to finish at all. That’s fast and compelling.

Automatically extracting pins and OBS from layout is shown below:

pin OBS min

The LEF generator can quickly calculate all of the antenna parameters, like: Gate oxide, Oxide area, Metal CAR, etc. Four device stack types that correspond to different process nodes are supported as shown in this diagram:

four stacks min

The antenna parameter equations are:

antenna parametre min

The flow of using the LEF generator is pretty simple, just prepare your design data and user configuration files, then run in GUI or batch modes:

tool flow min

Conclusion

IC designs are getting much larger especially at 16nm, 7nm and smaller process nodes, so finding a way to save time when running a task like LEF generation will help optimize your design flow. The Skipper tool from Empyrean has been around for several years, and their LEF generator is able to generate LEF which could not be done with other tools.

Empyrean supports both FinFET and SOI process nodes, and Skipper will fit into your existing Automatic Place and Route (APR) tool flow.  Read more about Skipper online.

Related Blogs

Share this post via:

Comments

One Reply to “Speed Up LEF Generation Times on Huge IC Designs”

You must register or log in to view/post comments.