In today’s System-on-Chip (SOC), analog blocks are used in many places such as I/O cells for communication, PLLs for generating clocks, LDO’s for converting supply voltage to internal rail voltage, Sensors for qualifying external characteristics such as temperature, light, motion, etc. However new advanced designs now require analog sensing circuits that are turned inward to monitor their own health and operation. Analog sensing is now needed for monitoring circuit temperature, voltages, process variation and other operational aspects.
Mahesh Tirupattur from Analog Bits recently gave a presentation, which is available for viewing on demand, that talks about the challenges SOC designers face in dealing with large die sizes, power supply issues, process variation and more. The presentation titled “Sensing the Unknown: Modern Method to Designing Chips” reviews a large chip case study and how sensing made its operation possible. Analog Bits has been designing on-chip sensors for many years and has expanded their capabilities to address issues encountered in the most advanced designs.
Chip designers have to thread the needle with every chip to gain maximum performance, area and efficiency while dealing with PVT variation and power supply issues. This is nearly impossible to do now without the ability to dynamically adjust operation to compensate for these factors. Mahesh discusses how Cerebras used glitch detectors from Analog Bits to provide real-time information on the power supply health in their massive AI processor. This AI engine measures 215 x 215 mm and has 1.2 trillion transistors. With 400,000 cores spread over a large die, local phenomenon could easily occur that can cause disruption.
The solution, according to Mahesh, was the addition of 840 distributed glitch detectors. They are provided as a fully integrated analog macro with a digital interface. The glitch detectors are user programmable, so the trigger voltages, depth of glitch and glitch time span can be set as per the needs of the specific design. Using the data provided, instantaneous current spikes can be suppressed.
Analog Bits started early with innovation in their PVT sensors. They are extremely accurate and operate with low power and a small form factor. It later developed power-on reset sensors to ensure the stability of supply lines in the core and IOs. These can also assist with brown-out prevention. The conpany’s most recent product family includes the power supply glitch detectors mentioned above. These can be abutted and have their own integrated voltage reference.
Analog Bits is also addressing SOC clocking issues. Once again without feedback and dynamic operation, clocks can be difficult to manage across large designs. Mahesh talks about their “Package Pin-less” technology that frees PLLs from pin requirements and allows more flexible placement on the die. This will enormously reduce clock power distribution, save bill of materials eliminating filter components and reduce test times.
Analog bits has developed their analog IP for process nodes from 0.25 microns down to the most advanced FinFET processes, such as 12nm, 7nm, 5nm and 3nm at fabs such as GLOBALFOUNDRIES, Samsung and TSMC. In all they support over 200 process nodes. Because they develop a broad line of analog macros, they share common functional units to ensure higher quality and interoperability. Importantly, to make their business model easier for their customers, they do not use a royalty model.
The presentation, which is part of this year’s Simulation World event, provides good insight into Analog Bits and their offerings. If you want to view the video of the presentation it can be found at the Simulation World website.
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