Achronix Speedster7t Garners Best Practices Award for FPGA

Achronix Speedster7t Garners Best Practices Award for FPGA
by Tom Simon on 01-11-2021 at 10:00 am

Frost and Sullivan 2020 Award Achronix

FPGAs have played an important role in the growth of key markets, including networking, storage, mobile devices, etc. They offer a unique set of capabilities that ASICs, CPUs and GPUs find hard to match. FPGAs are wire-speed, programmable integrated circuits that accelerate data and applications.  The ability to reprogram … Read More


Sensor Fusion Brings Earbuds into the Modern Age

Sensor Fusion Brings Earbuds into the Modern Age
by Tom Simon on 12-18-2020 at 6:00 am

CEVA Sensor Fusion

Ten years ago, earbuds might have seemed like a mundane product area with little room for exciting developments. Truly Wireless Stereo (TWS) has coincided with an avalanche of innovations that have moved earbuds from a simple transducer for creating sound into being a sophisticated device capable of accepting user commands … Read More


Achronix Talks about FPGAs for Video Processing

Achronix Talks about FPGAs for Video Processing
by Tom Simon on 12-15-2020 at 10:00 am

Need for Video Editing

The internet keeps adding users and connected devices. According to the numbers in a white paper from Achronix, by 2022 there will be 4.8 billion internet users and 28.5 billion connected devices. Internet traffic will reach 275 exabytes per month. Of this a staggering 83 percent will be video traffic. Moving the data from creators… Read More


Configuration Environment is Make-or-Break for IC Verification

Configuration Environment is Make-or-Break for IC Verification
by Tom Simon on 12-10-2020 at 10:00 am

IC Verification Environment

All semiconductor design work today rests on the three-legged stool of Foundries, EDA Tools and Designers. Close collaboration between the three make possible the successful completion of ever more complex designs, especially those at advanced nodes. Perhaps one of the most critical intersections of all three is during physical… Read More


Verification IP proves essential for PCIe GEN5

Verification IP proves essential for PCIe GEN5
by Tom Simon on 12-08-2020 at 6:00 am

PCIe Verification IP

PCI Express (PCIe) has become an important communication element in a wide range of systems. It is used to connect networking, storage, FPGA and GPGPU boards to servers and desktop systems. It has progressed a long way from its initial parallel bus format. Its evolution to a serial point to point configuration has been accompanied… Read More


Sign Off Design Challenges at Cutting Edge Technologies

Sign Off Design Challenges at Cutting Edge Technologies
by Tom Simon on 12-03-2020 at 6:00 am

Power and Ground Design Challenges

As semiconductor designs for many popular products move into smaller process nodes, the need for effective and rapid design closure is increasing. The SOCs used for many consumer and industrial applications are moving to FinFET nodes from 16 to 7nm and with that comes greater challenges in obtaining design closure. einfochips,… Read More


Low Power SRAM Register Files for IoT, AI and Wearables

Low Power SRAM Register Files for IoT, AI and Wearables
by Tom Simon on 11-26-2020 at 10:00 am

SRAM register files

SRAM is the workhorse for on-chip memories, valued for its performance and easy integration with standard processes. The needs of wearable, IoT and AI SOCs have put a lot of pressure on the requirements for all on-chip memories. This is perhaps most evident in the area of power. AI chips that rely heavily on SRAM register files are… Read More


Webinar Replay on TileLink from Truechip

Webinar Replay on TileLink from Truechip
by Tom Simon on 11-24-2020 at 10:00 am

TileLink

The extremely popular RISC-V instruction set architecture (ISA) originally came from the Berkeley Architecture Research (BAR) group. BAR also developed several other key pieces of enabling technology that have helped RISC-V become so popular. Among these are Rocket Chip which serves as a RISC-V based SOC generator. It can … Read More


Mentor Offers Next Generation DFT with Streaming Scan Network

Mentor Offers Next Generation DFT with Streaming Scan Network
by Tom Simon on 11-12-2020 at 10:00 am

Streaming Scan Network

Design for test (DFT) requires a lot of up-front planning that can be difficult to alter if testing needs or performance differ from initial expectations. Hierarchical methodologies help in many ways including making it easier to reduce on chip resources such as the number of test signals. Also, hierarchical test allows for speed-ups… Read More


Aldec Adds Simulation Acceleration for Microchip FPGAs

Aldec Adds Simulation Acceleration for Microchip FPGAs
by Tom Simon on 11-10-2020 at 10:00 am

Simulation Acceleration

Despite the fact that FPGA based systems make it easy to add ‘hardware in the loop’ for verification, the benefits of HDL and gate level simulation are critical for finding and eliminating issues and bugs. The problem is that software simulators can require enormous amounts of time to run full simulations over sufficient time intervals… Read More