The reason people love FPGAs for networking and communications applications is because they offer state of the art high speed interfaces and impressive parallel processing power. The problem is that typically a lot of the FPGA fabric resources are used simply to move the data on or off and across the chip. Achronix has cleverly employed a two-dimensional (2D) Network on Chip (NoC) to offload this task from the FPGA fabric, freeing up significant area and offering better throughput and speed for all data transfers.
With claims like theirs it can be useful to see actual benchmark results that show the tangible benefits. First let’s start by describing their 2D NoC. In the Speedster7t FPGA, Achronix has implemented the NoC as 8 rows and 8 columns evenly spaced across the chip, each with two sets of unidirectional AXI compatible data paths that are 256 bits wide – all operating at 512 Gbps.
The 2D NoC can transfer data to and from the chip’s external interfaces, which include PCIe Gen5, GDDR6 DDR4/5 and Ethernet. The NoC not only supports a packet-based, master/slave transaction model, it also supports Ethernet data streams. In fact, the 2D NoC can move data from the Ethernet interface to the DDR memory without requiring any resources in the FPGA Fabric. This enables the Speedster7t with the 2D NoC to support 400 Gbps Ethernet with ease.
NoC vs FPGA Fabric Data Routing
To demonstrate several important aspects of the 2D NoC, Achronix has posted a video that goes through a stress test to see how the NoC performs in the real world. The test uses a data generator on one end of a NoC row/column and also has loopback logic on the other end. At the end of the loop there is a transaction checker. Each row and each column are fitted with this bi-directional configuration. The data generator, loopback logic and transaction checker are implemented in the FPGA fabric, which accesses the NoC through a Network Access Point (NAP).
The same set up was done for comparison using the FPGA fabric to route the data across the chip for each row and column. Without the NoC 40% more FPGA resources were needed to perform the routing across the chip. Even though the performance was equal at ~4.6 Tbps, the compile time for the design was 40% less for the NoC versus the FPGA data routing.
Visualizing FPGA Performance
The video highlights the two chips operating with monitoring attached to show data rates. Also, the loading of the entire NoC is shown visually in the Achronix tools. All the columns and rows showed green, meaning that they are well under full capacity in this particular test. The data rate in this test is determined by the data generator in each row/column.
Achronix has other examples in their latest white paper and 2021 webinar on their website of the efficiency and speed of using a NoC. For instance, in a case with internal congestion due to the addition of processing elements such as encryption/decryption, etc. a design with FPGA based routing may have to detour data routes around the congested areas. This can only add to timing closure headaches.
A high speed NoC offers a painless method of moving data at high speed, helping to fulfill the promise of FPGAs in data intensive applications. The 2D NoC on Achronix FPGAs offers high capacity and bandwidth combined with ease of implementation and rapid design closure. Seeing a heavily loaded stress test makes clear what is possible with the Achronix Speedster7t FPGA. The video is available on the Achronix website. Achronix also has several blogs that go into the specifics of their 2D NoC and how it can be used for 400 Gpbs Ethernet or other applications that perform compute intensive operations on data streams.
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