Silicon Creations at DAC 2026: Solutions for clocking, SerDes, and sensing in 2nm (and beyond)

Silicon Creations at DAC 2026: Solutions for clocking, SerDes, and sensing in 2nm (and beyond)
by Daniel Nenni on 07-21-2026 at 2:00 pm

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Silicon Creations provides world-class IP for precision and general-purpose timing (PLLs and oscillators), high-performance multi-protocol, latency optimized and protocol-specific SerDes, high-speed I/Os, and accurate VT sensors. Applications include high-performance computing for AI, smart phones, wearables,… Read More


CEO Interview with Mohit Gupta of TYLsemi

CEO Interview with Mohit Gupta of TYLsemi
by Daniel Nenni on 07-19-2026 at 4:00 pm

Mohit

Mohit Gupta founded TYLsemi to build chiplet-based intelligent power and connectivity solutions for AI infrastructure—an area where custom silicon has long been underserved. TYLsemi exists to provide the foundational chiplet platform that enables tailored custom silicon solutions for the evolving needs of AI infrastructure.… Read More


Consolidation and Competition: Who is Winning the $4.5 Billion Interface IP Race?

Consolidation and Competition: Who is Winning the $4.5 Billion Interface IP Race?
by Kalar Rajendiran on 07-09-2026 at 2:00 pm

2025 TSMC Revenue by Platform

The semiconductor landscape is currently undergoing a structural transformation as the “Data-Centric Shift” moves the industry’s center of gravity from smartphones toward High-Performance Computing (HPC) and AI infrastructure.

This transition is clearly validated by TSMC’s 2025 filings, which show… Read More


See Autonomous Chip Design in Action with ChipAgents at DAC 2026

See Autonomous Chip Design in Action with ChipAgents at DAC 2026
by Daniel Nenni on 07-07-2026 at 2:00 pm

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Making the AI wave at DAC 2026 in Long Beach

DAC comes to Long Beach for the first time in 2026, with artificial intelligence expected to be one of the central topics across the conference program and exhibition floor.

For semiconductor design and verification teams, the discussion has moved beyond whether AI can assist engineers.… Read More


Webinar: Scaling Compute Connectivity with PCIe and CXL: Chip-to-Chip and Emerging Architectures

Webinar: Scaling Compute Connectivity with PCIe and CXL: Chip-to-Chip and Emerging Architectures
by Admin on 06-29-2026 at 9:28 pm

Featured Speakers:

  • Richard Solomon, Senior Staff Technical Product Manager, Synopsys
  • Ron Lowman, Staff Product Manager, Synopsys

Heterogeneous compute platforms are driving new requirements for connectivity across increasingly complex system architectures. This webinar explores how PCIe and CXL can be used to provide… Read More


Webinar: How Data Rates Doubled, and Where Validation Reaches Its Limit

Webinar: How Data Rates Doubled, and Where Validation Reaches Its Limit
by Admin on 04-13-2026 at 11:27 pm

Data rates have doubled, but validation methods have not kept pace. As PCIe, DDR, and multi-terabit optical interconnects evolve, engineers are encountering signal integrity challenges much earlier in the design process.

Join Niels Fache, Senior Vice President and General Manager of Design Engineering Software at Keysight,… Read More


Keynote: On-Package Chiplet Innovations with UCIe

Keynote: On-Package Chiplet Innovations with UCIe
by Daniel Nenni on 03-08-2026 at 4:00 pm

Chiplet Summit Keynote UCIe 2026

In the rapidly evolving landscape of semiconductor technology, the Universal Chiplet Interconnect Express (UCIe) emerges as a groundbreaking open standard designed to revolutionize on-package chiplet integrations. Presented by Dr. Debendra Das Sharma, Chair of the UCIe Consortium and Intel Senior Fellow, at the ChipletRead More


How PCIe Multistream Architecture Enables AI Connectivity at 64 GT/s and 128 GT/s

How PCIe Multistream Architecture Enables AI Connectivity at 64 GT/s and 128 GT/s
by Kalar Rajendiran on 12-09-2025 at 8:00 am

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As AI and HPC systems scale to thousands of CPUs, GPUs, and accelerators, interconnect performance increasingly determines end-to-end efficiency. Training and inference pipelines rely on low-latency coordination, high-bandwidth memory transfers, and rapid communication across heterogeneous devices. With model sizes… Read More


Boosting SoC Design Productivity with IP-XACT

Boosting SoC Design Productivity with IP-XACT
by Daniel Payne on 11-17-2025 at 10:00 am

IP XACT min

IP-XACT, defined by IEEE 1685, is a standard that pulls together IP packaging, integration, and reuse. For anyone building modern SoCs (Systems on Chip), IP-XACT isn’t just another XML schema: it is a productivity multiplier and a risk-reduction tool that brings order to your electronic system design.

What is IP-XACT?

IP-XACT… Read More


WEBINAR: How PCIe Multistream Architecture is Enabling AI Connectivity

WEBINAR: How PCIe Multistream Architecture is Enabling AI Connectivity
by Daniel Nenni on 11-11-2025 at 8:00 am

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In the race to power ever-larger AI models, raw compute is only half the battle. The real challenge lies in moving massive datasets between processors, accelerators, and memory at speeds that keep up with trillion-parameter workloads. Synopsys tackles this head-on with its webinar, How PCIe Multistream Architecture is EnablingRead More