Verifying PCIe 5.0 with PLDA, Avery and Aldec

Verifying PCIe 5.0 with PLDA, Avery and Aldec
by Bernard Murphy on 11-03-2020 at 6:00 am

little fish big fish min

Mike Gianfagna, a fellow SemiWiki blogger and a one-time colleague at Atrenta shared a useful piece of marketing advice. If your company is not the biggest fish in the pond and you want to appear more significant, team up with other companies to put on an event, say a webinar. Pick your partners so that you can jointly offer a larger,… Read More


How to Build PCIe Speed Adapters for In-Circuit SoC Emulation

How to Build PCIe Speed Adapters for In-Circuit SoC Emulation
by Daniel Nenni on 10-22-2020 at 11:00 am

Abstract:

Hardware assisted verification became much more affordable due to the availability of high capacity FPGAs such as Xilinx Virtex UltraScale US440 and their adoption for emulation verification environments. One of the advantages of FPGA-based emulation systems is that it’s much more flexible than traditional processor-based… Read More


High-Performance PCIe 5.0 IP + VIP UVM Verification Environment (US)

High-Performance PCIe 5.0 IP + VIP UVM Verification Environment (US)
by Daniel Nenni on 10-15-2020 at 11:00 am

Abstract:

Together with Aldec, PLDA and Avery Design Systems, we will present and demo our newest PCIe 5.0 IP + VIP UVM simulation and debugging environment. PLDA’s PCIE 5.0 XpressRich includes internal datapath automatic scaling, configurable pipelining, Rx stream mode for custom credit management, L1 PM substates, dynamically… Read More


PCI Express in Depth – Physical Layer

PCI Express in Depth – Physical Layer
by Luigi Filho on 08-23-2020 at 10:00 am

PCI Express in Depth Physical Layer

In the last article, I wrote about the PCIe basic concepts. This article will reach the physical layer of the PCIe standard.

The lowest PCI Express architectural layer is the Physical Layer. This layer is responsible for actually sending and receiving all the data to be sent across the PCI Express link. The Physical Layer interacts… Read More


PCI Express in Depth

PCI Express in Depth
by Luigi Filho on 08-23-2020 at 8:00 am

PCI Express in Depth

This is another post that was requested by a user, and as always i’ll do my best to put in a few articles the basic information that you’ll need to understand how it works at depth level.

PCI Express (or PCIe) is a high-speed serial computer expansion bus designed to replace the older PCI, PCI-X and AGP standards.

The first… Read More


A VIP to Accelerate Verification for Hyperscalar Caching

A VIP to Accelerate Verification for Hyperscalar Caching
by Bernard Murphy on 12-18-2019 at 6:00 am

NVMe

Non-volatile memory (NVM) is finding new roles in datacenters, not currently so much in “cold storage” as a replacement for hard disk drives, but definitely in “warm storage”. Warm storage applications target an increasing number of functions requiring access to databases with much lower latency than is possible through paths… Read More


Synopsys is First IP Provider with a Complete CXL Implementation Available

Synopsys is First IP Provider with a Complete CXL Implementation Available
by Randy Smith on 09-11-2019 at 12:00 pm

Synopsys just announced the availability of their IP solution supporting CXL (Compute Express Link). This new protocol is going to be an important component for several applications expected to be shipping starting in 2021. CXL is an alternate protocol that runs on the same physical layer as PCI Express (PCIe). Among other usages,… Read More


Silvaco Samsung and Excitement at 56thDAC

Silvaco Samsung and Excitement at 56thDAC
by Daniel Nenni on 05-25-2019 at 8:00 am

There were quite a few announcements at the Samsung Foundry Forum but my favorite was the IP partnership between Samsung and Silvaco. IP is a critical part of the fabless ecosystem and one of the advantages an IDM foundry has over a pure-play is the vast amounts of internal IP that have been silicon proven over the years. With Samsung… Read More


PCIe 5.0 Jumps to the Fore in 2019

PCIe 5.0 Jumps to the Fore in 2019
by Tom Simon on 03-06-2019 at 12:00 pm

2019 will be a big year for PCIe. With the approval of version 0.9 of the Base Layer for PCIe 5.0, implementers have a solid foundation to begin working on designs. PCIe 4.0 was introduced in 2017, before that the previous PCIe 3.0 was introduced in 2010 – ages ago in this industry. In fact, 5.0 is so close on the heels of 4.0, many products… Read More


USB 3.x IP Revenue Have Grown by 31% in 2017 (IPnest)

USB 3.x IP Revenue Have Grown by 31% in 2017 (IPnest)
by Eric Esteve on 09-04-2018 at 12:00 pm

Despite the strong consolidation in the semiconductor industry, the Design IP market is going well, very well with YoY growth of 12%+ in 2017, according with the “Design IP Report” from IPnest. If we look at the Interface IP category (20% growth in 2017) and analyze the IP revenues by protocols, we can see that USB IP is amazingly healthy,… Read More