Optimization Tradeoffs in Power and Latency for PCIe/CXL in Datacenters

Optimization Tradeoffs in Power and Latency for PCIe/CXL in Datacenters
by Daniel Nenni on 02-13-2023 at 10:00 am

Power Latency Webinar min

PCI Express Power Bottleneck

Madhumita Sanyal, Sr. Technical Product Manager, and Gary Ruggles, Sr. Product Manager, discussed the tradeoffs between power and latency in PCIe/CXL data centers during a live SemiWiki webinar on January 26, 2023. The demands on PCIe continue to grow with the integration of multiple components… Read More


How to Efficiently and Effectively Secure SoC Interfaces for Data Protection

How to Efficiently and Effectively Secure SoC Interfaces for Data Protection
by Kalar Rajendiran on 01-04-2023 at 6:00 am

secure interfaces article fig1

Before the advent of the digitized society and computer chips, things that needed protection were mostly hard assets such as jewelry, coins, real estate, etc. Administering security was simple and depended on strong guards who provided security through physical means. Then came the safety box services offered by financial … Read More


Webinar: PCIe/CXL Latency and Power Considerations for HPC SoCs

Webinar: PCIe/CXL Latency and Power Considerations for HPC SoCs
by Admin on 12-15-2022 at 3:53 pm

*Company email required for registration*

If you are designing chips for high-performance computing (HPC) and data center applications, bandwidth is, of course, a key consideration. However, as data centers get bigger and the required compute power increases, keeping power consumption to a minimum becomes a priority. In

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High-End Interconnect IP Forecast 2022 to 2026

High-End Interconnect IP Forecast 2022 to 2026
by Eric Esteve on 12-04-2022 at 10:00 am

TSMC Revenue by Platform 1Q22 1

The Interface IP market has grown with 21% CAGR from 2017 to 2021 and we review the part of this market restricted to the high-end of PCIe, DDR, Ethernet and D2D IP made of PHY and controller targeting the most advanced technology nodes and latest protocol release. We will show that an IP vendor focusing investment on the high-end interconnect… Read More


Integrating High Speed IP at 5nm

Integrating High Speed IP at 5nm
by Pavan Patel on 11-10-2022 at 6:00 am

Figure 1

Introduction:

The advancements in deep submicron technology and adding multiple functionalities to reduce costs combined with scaling existing operations means that SoC designs become ever more complex. The biggest driving factors to go below the 16nm process node are the decrease in power and the increase in performance … Read More


UCIe Specification Streamlines Multi-Die System Design with Chiplets

UCIe Specification Streamlines Multi-Die System Design with Chiplets
by Dave Bursky on 09-26-2022 at 10:00 am

protocol stack 1

Over the last few years, the design of application-specific ICs as well as high-performance CPUs and other complex ICs has hit a proverbial wall. This wall is built from several issues: first, chip sizes have grown so large that they can fill the entire mask reticle and that could limit future growth. Second, the large chip size impacts… Read More


PCI-SIG Developers Conference Asia-Pacific 2022

PCI-SIG Developers Conference Asia-Pacific 2022
by Admin on 09-16-2022 at 2:40 pm

September 21, 2022
Westin Tokyo
Tokyo, Japan

September 26, 2022
Grand Hyatt Seoul
Seoul, South Korea

Overview

The PCI-SIG Developers Conferences are free events for our 900+ member companies that develop and bring to market new products utilizing PCI Express® technology. They are an opportunity to learn directly from the… Read More


Interface IP in 2021: $1.3B, 22% growth and $3B in 2026

Interface IP in 2021: $1.3B, 22% growth and $3B in 2026
by Eric Esteve on 07-10-2022 at 10:00 am

IP 2017 2026

If you want to remember the key points for Interface IP in 2021, just consider $1.3B, 22%, $3B. Interface IP category has generated $1 billion 300 million in 2021, or 22.7% year to year growth, thanks to high runner protocols PCIe, DDR memory controller and Ethernet/SerDes. Even more impressive is the forecast, as IPnest predict… Read More


CXL Verification. A Siemens EDA Perspective

CXL Verification. A Siemens EDA Perspective
by Bernard Murphy on 07-07-2022 at 6:00 am

CXL Verification

Amid the alphabet soup of inter-die/chip coherent access protocols, CXL is gaining a lot of traction. Originally proposed by Intel for cross-board and cross-backplane connectivity to accelerators of various types (GPU, AI, warm storage, etc.), a who’s who of systems and chip companies now sits on the board, joined by an equally… Read More


Verifying Inter-Chiplet Communication

Verifying Inter-Chiplet Communication
by Daniel Nenni on 07-04-2022 at 6:00 am

UCIe min

Chiplets are hot now as a way to extend Moore’s Law, dividing functionality across multiple die within a single package. It’s no longer practical to jam all functionality onto a single die in the very latest processes, exceeding reticle limits in some cases and in others straining cost/yield. This is not an academic concern. Already… Read More