SoC Application Usecase Capture For System Architecture Exploration

SoC Application Usecase Capture For System Architecture Exploration
by Sondrel on 04-19-2022 at 6:00 am

Fig 1

Sondrel is the trusted partner of choice for handling every stage of an IC’s creation. Its award-winning define and design ASIC consulting capability is fully complemented by its turnkey services to transform designs into tested, volume-packaged silicon chips. This single point of contact for the entire supply chain… Read More


Benefits of a 2D Network On Chip for FPGAs

Benefits of a 2D Network On Chip for FPGAs
by Tom Simon on 04-12-2022 at 10:00 am

Achronix FPGA 2D NoC

The reason people love FPGAs for networking and communications applications is because they offer state of the art high speed interfaces and impressive parallel processing power. The problem is that typically a lot of the FPGA fabric resources are used simply to move the data on or off and across the chip. Achronix has cleverly … Read More


Identity and Data Encryption for PCIe and CXL Security

Identity and Data Encryption for PCIe and CXL Security
by Tom Simon on 01-07-2022 at 6:00 am

Security for Cloud Applications

Privacy and security have always been a concern when it comes to computing. In prior decades for most people this meant protecting passwords and locking your computer. However, today more and more users are storing sensitive data in the cloud, where it needs to be protected at rest and while in motion. In a Synopsys webinar Dana Neustadter,… Read More


Low Power High Performance PCIe SerDes IP for Samsung Silicon

Low Power High Performance PCIe SerDes IP for Samsung Silicon
by Tom Simon on 12-02-2021 at 10:00 am

SerDes IP for PCIe

No matter how impressive the specifications are for an SoC, the power performance and area of the finished design all depend on the IP selected for the IO blocks. In particular, most SOCs designed for consumer and enterprise applications rely heavily on PCI Express. Because PCIe analog IP is critical to design success, Samsung … Read More


PCIe Gen5 Interface Demo Running on a Speedster7t FPGA

PCIe Gen5 Interface Demo Running on a Speedster7t FPGA
by Kalar Rajendiran on 11-24-2021 at 10:00 am

PCIe Gen5 Interface Demo Board

The major market drivers of today all have one thing in common and that is the efficient management of data. Whether it is 5G, hyperscale computing, artificial intelligence, autonomous vehicles or IoT, there is data creation, processing, transmission and storage. All of these aspects of data management need to happen very fast.… Read More


Defending the Cloud: PCIe and CXL Data Security for High-Performance Computing

Defending the Cloud: PCIe and CXL Data Security for High-Performance Computing
by Daniel Nenni on 10-19-2021 at 9:00 am

Cloud computing is going through a significant overhaul and continues to grow globally with increasing presence of hyperscale cloud providers for big data, high-performance computing (HPC), and analytics. In-house data centers are increasingly going off-premise, resulting in the co-location of data centers that manage… Read More


PCIe Gen 6 Verification IP Speeds Up Chip Development

PCIe Gen 6 Verification IP Speeds Up Chip Development
by Tom Simon on 07-08-2021 at 10:00 am

PCIe Gen 6 VIP

PCIe is a prevalent and popular interface standard that is used in just about every digital electronic system. It is used widely in SOCs and in devices that connect to them. Since it was first released in 2003, it has evolved to keep up with rapidly accelerating needs for high speed data transfers. Each version has doubled in throughput,… Read More


PCI Express 6.0 Design Considerations and IP Implementation

PCI Express 6.0 Design Considerations and IP Implementation
by Daniel Nenni on 06-24-2021 at 10:00 am

SoC designers, looking to get a jump start on their PCI Express (PCIe) 6.0 designs must be aware of several new considerations in addition to doubling of the data rate to 64 GT/s. Accessing a complete IP solution that offers optimized performance and seamless interoperability between the controller and PHY, achieving timing closure
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CEO Interview: Deepak Shankar of Mirabilis Design

CEO Interview: Deepak Shankar of Mirabilis Design
by Daniel Nenni on 06-11-2021 at 6:00 am

Deepak Shankar Mirabilis

The founder of Mirabilis Design, Mr. Shankar has over two decades of experience in management and marketing of system level design tools. Prior to establishing Mirabilis Design, he held the reins as Vice President, Business Development at MemCall, a fabless semiconductor company and SpinCircuit, a joint venture of industry… Read More


PCIe 6.0 Doubles Speed with New Modulation Technique

PCIe 6.0 Doubles Speed with New Modulation Technique
by Tom Simon on 04-26-2021 at 6:00 am

PCIe 6.0 Eye

PCI-SIG has held to doubling PCIe’s data rate with each revision of the specification. The consortium of 800 companies, with its board consisting of Agilent, AMD, Dell, HP, Intel, Synopsys, NVIDIA, and Qualcomm, is continuing this trend with the PCIe 6.0 specification which calls for a transfer rate of 64 GT/s. PCI-SIG released… Read More