All Things Semiconductor!
Synopsys just announced the availability of their IP solution supporting CXL (Compute Express Link). This new protocol is going to be an important component for several applications expected to be shipping starting in 2021. CXL is an alternate protocol that runs on the same physical layer as PCI Express (PCIe). Among other usages,… Read More
There were quite a few announcements at the Samsung Foundry Forum but my favorite was the IP partnership between Samsung and Silvaco. IP is a critical part of the fabless ecosystem and one of the advantages an IDM foundry has over a pure-play is the vast amounts of internal IP that have been silicon proven over the years. With Samsung… Read More
2019 will be a big year for PCIe. With the approval of version 0.9 of the Base Layer for PCIe 5.0, implementers have a solid foundation to begin working on designs. PCIe 4.0 was introduced in 2017, before that the previous PCIe 3.0 was introduced in 2010 – ages ago in this industry. In fact, 5.0 is so close on the heels of 4.0, many products… Read More
Despite the strong consolidation in the semiconductor industry, the Design IP market is going well, very well with YoY growth of 12%+ in 2017, according with the “Design IP Report” from IPnest. If we look at the Interface IP category (20% growth in 2017) and analyze the IP revenues by protocols, we can see that USB IP is amazingly healthy,… Read More
FPGA Prototyping started with the advent of FPGAs in the 1980s and today it is a fast growing market segment due to increasing chip and IP complexities up against tightening windows of opportunities. Getting your design verified quickly and allowing hardware and software engineers the opportunity to develop, test, and optimize… Read More
Due to the overwhelming response, here is the first part of the webinar that I did with S2C and a link to the replay. Richard Chang, Vice President of Engineering at S2C did the technical part of the webinar. Richard has a Masters degree in Electrical engineering from the University at Buffalo and more than 20 years experience designing… Read More
IPnest has released the 9[SUP]th[/SUP] version of the Interface IP Survey, ranking by protocol the IP vendors addressing the Interface segments: USB, PCI Express, (LP)DDRn, MIPI, Ethernet & SerDes, HDMI/DP and SATA. When the 1[SUP]st[/SUP] version has been issued in 2009, the IP segment was weighting $225 million and the… Read More
According with IPnest, the Interface IP market, including USB, PCI Express, (LP)DDRn, HDMI, MIPI and Ethernet IP segments, has reached $532 million in 2016, growing from $472 million in 2015. This is an impressive 13% Year-over-Year growth rate, and 12% CAGR since 2012!
Who integrate functions to interface a chip with others … Read More
The defining characteristic of In-Circuit-Emulation (ICE) has been that the emulator is connected to real circuitry – a storage device perhaps, and PCIe or Ethernet interfaces. The advantage is that you can test your emulated model against real traffic and responses, rather than an interface model which may not fully capture… Read More
IPnest is launching the “Interface IP Survey” since 2009, and we did it last September again. To build the survey as accurately as possible, I have followed the “divide and conquer” strategy. Interface protocols are varied, ranging from PCI Express, USB, or Ethernet, to memory controller (DDR3, DDR4, LPDDR3, LPDDR4 and more) … Read More
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Thermal-induced Reliability Challenges and Solutions for Advanced IC Design
Choose the Right ASIC Manufacturing Model for Your Business
REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation
REPLAY: Avoiding CDM (Charged Device Model) ESD Failures
REPLAY: eFPGA – "What a great idea! But I have no idea how I’d use it!"
REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification
REPLAY: Fabless: The Transformation of the Semiconductor Industry
REPLAY: The Brave New World of Customized Memory
REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning
REPLAY: VLSI Design Methodology Development
REPLAY: Lightspeed Data Sync - Design Workspace Problems Solved!
REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats?
REPLAY: How ASIC/SoC Prototyping Solutions Can Help You!
REPLAY: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®
REPLAY: Taiwan ESD Workshop Recording
REPLAY: Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction
REPLAY: Text: A Year of Breakfast Bytes by Paul McLellan (Free PDF Version)
REPLAY: Finding Your Way Through Verification
REPLAY: Concerned about IP security threats for your SoCs?
REPLAY: Achronix: Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip
REPLAY: PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior
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Thermal-induced Reliability Challenges and Solutions for Advanced IC Design
Choose the Right ASIC Manufacturing Model for Your Business
REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation
REPLAY: Avoiding CDM (Charged Device Model) ESD Failures
REPLAY: eFPGA – “What a great idea! But I have no idea how I’d use it!”
REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification
REPLAY: Fabless: The Transformation of the Semiconductor Industry
REPLAY: The Brave New World of Customized Memory
REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning
REPLAY: VLSI Design Methodology Development
REPLAY: Lightspeed Data Sync – Design Workspace Problems Solved!
REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats?
REPLAY: How ASIC/SoC Prototyping Solutions Can Help You!
REPLAY: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®
REPLAY: Taiwan ESD Workshop Recording
REPLAY: Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction
REPLAY: Text: A Year of Breakfast Bytes by Paul McLellan (Free PDF Version)
REPLAY: Finding Your Way Through Verification
REPLAY: Concerned about IP security threats for your SoCs?
REPLAY: Achronix: Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip
REPLAY: PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior
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[_cascadeSave:protected] => Array
(
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[_behaviors:protected] =>
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[Forum] => vw\vw\XF\Entity\Forum Object
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[rootClass:protected] => XF\Entity\Forum
[_useReplaceInto:protected] =>
[_newValues:protected] => Array
(
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[_values:protected] => Array
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[node_id] => 2
[discussion_count] => 2666
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[last_post_id] => 42225
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[last_post_username] => Arthur Hanson
[last_thread_id] => 12096
[last_thread_title] => China lags far behind in semiconductor battle
[last_thread_prefix_id] => 0
[moderate_threads] => 0
[moderate_replies] => 0
[allow_posting] => 1
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[count_messages] => 1
[find_new] => 1
[field_cache] => []
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[prompt_cache] => []
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[default_sort_order] => last_post_date
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[_relations:protected] => Array
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[Node] => XF\Entity\Node Object
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[rootClass:protected] => XF\Entity\Node
[_useReplaceInto:protected] =>
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[_values:protected] => Array
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[title] => SemiWiki Main Forum ( Ask the Experts! )
[description] => Post your questions to the experts here!
[node_name] =>
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[display_order] => 1
[display_in_list] => 1
[lft] => 2
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[breadcrumb_data] => {"1":{"node_id":1,"title":"Main Category","depth":0,"lft":1,"node_name":null,"node_type_id":"Category"}}
[navigation_id] =>
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[_relations:protected] => Array
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[_previousValues:protected] => Array
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(
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(
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[_behaviors:protected] =>
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[_cascadeSave:protected] => Array
(
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[_behaviors:protected] =>
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[_previousValues:protected] => Array
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[_cascadeSave:protected] => Array
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[_behaviors:protected] =>
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[populated:protected] => 1
)
better_recent_comments-2
Widget_Better_Recent_Comments Instance: 2Array
(
[title] => Recent Article Comments
[number] => 10
[avatar] =>
[date] => 1
[comment] => 1
[link] => 1
[display_widget_mobile] => 1
[rw_opt] => Array
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[widget_select] => 1
[others_front_page] => 1
[pageid_275979] => 1
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[rw_opt_exclude] => Array
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Widget_Better_Recent_Comments
Is the ASIC Business Dead?