Gate-level simulations (GLS) are a crucial step in the verification of an ASIC/FPGA. GLS is used for verifying power-up, reset operation, timing, multi-cycle paths, and power estimation. However, GLS can be a bottleneck in the project cycle due to its complexity. The nature of a GLS can cause simulations to run much longer than
The event will focus on “Security at System Level, and what security features we need in our FPGA to support this”.
If you are interested in speaking at this event please… Read More
This 4-hour workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, and embedded systems using the Vivado® Design Suite. The features and capabilities of the Vivado Integrated Logic Analyzer are
In the ever-evolving world of Conversational AI and Automatic Speech Recognition (ASR), an upcoming LinkedIn Live webinar is set to redefine the speech-to-text industry. Achronix Semiconductor Corporation is teaming up with Myrtle.ai to bring you a webinar on October 24, 2023, at 8:30am PST.
Moderated by EE Times’ Sr. Reporter,… Read More
Thursday, October 19, 2023 | 10 a.m. PDT
When designing any new system, safety and reliability are key factors in determining if a system is safe for real-world deployment and if there are sufficient contingency plans for worst case scenarios. This is no different for the designs targeted for FPGAs based deployments. Today, FPGA
Time: 11:00 AM – 12:00 PM (PDT)
Abstract
As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and… Read More
Time: 11:00 AM – 12:00 PM (PDT)
Abstract
As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and… Read More
Time: 11:00 AM – 12:00 PM (PDT)
Abstract
As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and… Read More
* Company Email is Required for this Webinar *
Andes Custom Extensions (ACE) is a enables designers to add custom extensions to the standard RISC-V ISA to accelerate compute bound algorithm operations. A FIR filter with 128 taps in C code consumes 1600 RISC V CPU cycles. A custom extension can cut this function to 128 cycles. ACE makes… Read More
– Component shortage challenges and solutions
– Edge AI
– Sensor technology
– IoT security
– FPGA technology
– Ultra-wideband
