Podcast EP98: How Menta is revolutionizing embedded FPGA deployment

Podcast EP98: How Menta is revolutionizing embedded FPGA deployment
by Daniel Nenni on 08-05-2022 at 10:00 am

Dan is joined by Dr. Yoan Dupret, the Managing Director and CTO of Menta – a leader in embedded FPGA IP cores for chips and smart sensors. Yoan explores the impact Menta’s embedded FPGAs are having on current designs. The reasons for Menta’s success and where the impact will be in the future are both discussed as well.… Read More


Time is of the Essence for High-Frequency Traders

Time is of the Essence for High-Frequency Traders
by Dave Bursky on 06-27-2022 at 10:00 am

Figure Simplified block diagram of Multiprotocol PMA from Silicon Creations

In the world of financial trading, nanoseconds count. The faster a trade can be accomplished, the more money a trader can make. Getting a trade in before a competitor also results in improved profits. What does this have to do with the partnership deal recently inked between Silicon Creations and Achronix? Plenty. The two companies… Read More


How to Cut Costs of Conversational AI by up to 90%

How to Cut Costs of Conversational AI by up to 90%
by Dave Bursky on 06-20-2022 at 10:00 am

20 Tbps 2D NoC

The burgeoning use of conversational artificial intelligence (CAI) in consumer and business applications places a heavy computational burden on both front-end and back-end systems that provide the natural language processing (NLP). NLP systems rely on deep learning (a subset of machine learning) to automate speech recognition,… Read More


Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM

Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
by Admin on 06-09-2022 at 11:00 am

LIVE WEBINAR: Better FPGA Verification with VHDL (Four Part Webinar Series)

Part 2: Faster than “Lite” Verification Component Development with OSVVM (US)

Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair

Thursday, June 9, 2022

11:00 AM – 12:00 PM (PDT)… Read More


Using EM/IR Analysis for Efinix FPGAs

Using EM/IR Analysis for Efinix FPGAs
by Daniel Payne on 05-30-2022 at 10:00 am

XLR min

I’ve been following the EM/IR (Electro-Migration, IR is current and resistance) analysis market for many years now, and recently attended a presentation from Steven Chin, Sr. Director IC Engineering of Efinix, at the User2User event organized by Siemens EDA. The Tuesday presentation was in the morning at the Marriott… Read More


LIVE WEBINAR: Better FPGA Verification with VHDL (Four Part Webinar Series)

LIVE WEBINAR: Better FPGA Verification with VHDL (Four Part Webinar Series)
by Admin on 05-26-2022 at 11:00 am

Part 1: OSVVM – Leading Edge Verification for the VHDL Community (US)

Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair

Thursday, May 26, 2022

11:00 AM – 12:00 PM (PDT)

Abstract:

OSVVM is an advanced verification methodology that defines a VHDL verification framework,

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LIVE WEBINAR: FPGA Design/Verification Best-Practices for Quality and Efficiency Part 4: Code, Functional and Specification Coverage (US)

LIVE WEBINAR: FPGA Design/Verification Best-Practices for Quality and Efficiency Part 4: Code, Functional and Specification Coverage (US)
by Admin on 05-19-2022 at 11:00 am

Espen Tallaksen, CEO of EmLogic

Thursday, May 19, 2022

11:00 AM – 12:00 PM (PDT)

Abstract:

Functional coverage is often mentioned together with constrained-random verification, and this is a great combination. However, functional coverage is also very useful even if you have no randomization at all. This is a great method

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