The emergence of chiplets as a technology is an inflection point in the semiconductor industry. The potential benefits of adopting a chiplets-based approach to implementing electronic systems are not a debate. Chiplets, which are smaller, pre-manufactured components can be combined to create larger systems, offering benefits such as increased flexibility, scalability, and cost-effectiveness in comparison to monolithic integrated circuits. However, chiplets also present new challenges in terms of design, integration, and testing. The technology is still in flux, and there are many unknowns that need to be addressed over the coming years. The success of chiplets will depend on factors such as manufacturing capabilities, design expertise, and the ability to integrate chiplets into existing systems.
While sophisticated packaging and interconnect technologies have been receiving a lot of press, there are many more aspects that are critical too. Designing chiplets-based systems requires a different mindset and skillset than traditional chip design. Many more things need to come together to enable a chiplet-based economy. This was the focus of a recently held webinar titled “The Rise of the Chiplet.” The webinar was moderated by Brian Bailey, Technology Editor/EDA from SemiEngineering.com. The panelists were Nick Ilyadis, Sr. Director of Product Planning, Achronix; Rich Wawrzyniak, Principal Analyst ASIC & SoC, Semico Research Corp; and Bapi Vinnakota, OCP ODSA Project Lead, Open Compute Project Foundation.
The composition of the panel allowed the audience to hear a market perspective, and product perspective as well as the collaborative community perspective for designing efficiency into solutions.
What is needed for chiplet adoption
For chiplet adoption, the industry needs to worry not just about the die-to-die interfaces and packaging technology but the whole chiplet economy.
For example, how to describe a chiplet before building it in order to achieve efficient modularity. On the physical description for a chiplet, the standard things to include are area, orientation, thermal map, power delivery, bump maps, etc., This physical part description is very important when integrating chiplets from multiple vendors. OCP is beginning work with JEDEC to create a standard JEP30 part model to physically describe a chiplet. Some of the other areas to get addressed include: How to address known-good-die (KGD) in business contracts. How to accomplish architecture exploration? How to handle business logistics?
Various workgroups within OCP are focusing on many of these areas and more and making available downloadable worksheets or templates for use by designers. For example, designers can download a worksheet that helps them compare a chiplet-based design to a monolithic design for design costs and manufacturing costs. When it comes to chiplet interfaces, Bunch of Wires (BoW) for example may be the choice for some applications and Universal Chiplet Interconnect Express (UCIe) may be the right one for some other applications. There are tools available for comparing various die-to-die interfaces available in the marketplace.
The following table shows the various areas that need to be addressed.
Another important thing that needs to be understood and addressed is whether all the chiplets to be included in a product need to be from the same process corner. Do chiplets need to be marketed under different speed grades like memories are? If some chiplets are from fast corners and others are from the slow corners, what kind of issues will arise during system simulation and when deployed in the field?
As chiplets technology continues to evolve, companies will be experimenting with different approaches to incorporating chiplets into their products.
Embedded FPGA (eFPGA) has been gaining a lot of traction within the monolithic ASIC world. An eFPGA-based chiplet can extend the eFPGA benefits to a full chiplet-based system. Achronix as a leader in the FPGA solutions space is offering eFPGA IP-based chiplets to deliver the following benefits. Unique production solution (different SKUs); support different process technologies in cases where the optimal process technology for the ASIC is not optimal for an embedded FPGA; Utilize the FPGA chiplet across multiple generations of products versus having it in just one monolithic device.
Chiplets offer a promising new direction for the semiconductor industry. The winning solutions will be determined over the coming years. How many years, that depends on whom you ask. To listen to the entire webinar, check here. The panelists fielded a number of audience questions as well that you may find of interest to you.