A recent live discussion between experts Scott Schweitzer, Director of SmartNIC Product Planning with Achronix, and Jon Sreekanth, CTO of Accolade Technology, looked at the idea behind the rise of the SmartNIC and ran an “ask us anything” session fielding audience questions about the technology and its use cases.
Three phases of network interface cards
The standards collectively known as Ethernet have made fantastic progress since the early days of “thick net” and vampire tap media attachment units. In those days, simple network interface cards translated packets between the network cable and a parallel bus interface inside a computer, maybe like ISA.
Speeds were not that fast in this first phase of network interface cards, but the simple act of adding Ethernet connectivity opened all kinds of possibilities. The now-famous catchphrase “the network is the computer” defined this era with the ability to move files and send messages easily. Incremental speed improvements continued with successive releases of the standard, a shift to Cat5 cable, more powerful networking chips, and faster bus interfaces up to PCIe.
At higher wire speeds, computers can begin to fall behind even with faster interfaces and chips. Packets can arrive more quickly than some hosts can process them. The second phase, with TCP/IP offload engines, added DMA capability and front-end packet processing like checksums, freeing host processor cycles for other needs. Most flows were raw, with stateless packets, and offload engines mostly offered fixed functions with limited programmability.
For advanced networks, stateful flows are critical to application performance and security. Each flow is set up with its attributes: IP addresses and ports, protocols and applications, user identities, and even content-specific information. Flow tables can be gigantic, with 16M entries or more. In this third phase, a SmartNIC rises to the challenge.
What makes a SmartNIC different?
A few observations about a SmartNICs:
- Packet processing is soft, fully programmable for any role in today’s network, and able to anticipate future requirements.
- CPU cores don’t scale well for the high-speed data plane. (The webinar presenters pick on Arm a bit in their discussion, but RISC-V or other CPU cores are at a similar disadvantage. They still play a role in control plane management.) A high-end FPGA can be configured for specific data plane roles and reconfigured on the fly if conditions are detected, such as a denial-of-service attack.
- Everything needed for stateful flows must run from memory, so FPGA memory performance and interconnect are critical. Technologies like HBM or GDDR6 keep data moving in the FPGA fabric.
Here’s a block diagram of a SmartNIC programmable accelerator based on the Achronix Speedster 7t1500 FPGA, a part combining four 400Gb (or sixteen 100Gb) Ethernet ports with a multi-fractural MAC array and a PCIe Gen 5 interface. Another key in the Speedster 7t architecture is the innovative 2D network on chip, or 2D NoC. The 2D NoC is a hardened data path which connects all of the FPGA’s external interfaces and memory to each other and deep within the FPGA fabric. Using the 2D NoC latency is reduced compared to using FPGA logic for data routing across the chip.
Like any workflow-optimized architecture, the theme is to run the Ethernet pipes at speed, keep as many banks of processing and memory as busy as possible, and work on multiple packets in the pipeline. At several points, the presenters mention this is not the high-frequency trading use case, a stateless flow where every nanosecond counts. A few nanoseconds of latency in a stateful flow make little difference at these wire speeds.
Some good questions … and answers
One welcome difference in this Rise of the SmartNIC webinar is that there isn’t much presentation material. After a short preamble with the agenda and some industry factoids, the image above is the only slide in the live stream. More time is spent on audience questions including these:
- Would a P4 engine run in a SmartNIC?
- Is “wormhole routing” still a thing, and would a SmartNIC help?
- Why should both the packet and flow engines be FPGA cores?
- How does timing closure in the FPGA affect packet processing determinism?
- What is the role of timestamping in multiple packets from different links?
The answers might surprise you, but you’ll have to watch to find out. This webinar is archived for viewing anytime – follow the link below to register and view the entire discussion.
Achronix Webinar: The Rise of the SmartNIC