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Choose the Right ASIC Manufacturing Model for Your Business

REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation

REPLAY: Avoiding CDM (Charged Device Model) ESD Failures

REPLAY: eFPGA – "What a great idea! But I have no idea how I’d use it!"

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October 31, 2019October 30, 2019

BittWare PCIe server card employs high throughput AI/ML optimized 7nm FPGA

BittWare PCIe server card employs high throughput AI/ML optimized 7nm FPGA
by Tom Simon on 10-31-2019 at 6:00 am
Categories: Achronix, AI, eFPGA

Back in May I wrote an article on the new Speedster7t from Achronix. This chip brings together Network on Chip (NoC) interconnect, high speed Ethernet and memory connections, and processing elements optimized for AI/ML. Speedster7t is a very exciting new FPGA that can be used effectively to accelerate a wide range of processing… Read More

October 14, 2019October 12, 2019

Free webinar – Accelerating data processing with FPGA fabrics and NoCs

Free webinar – Accelerating data processing with FPGA fabrics and NoCs
by Tom Simon on 10-14-2019 at 10:00 am
Categories: Achronix, eFPGA, IP

FPGAs have always been a great way to add performance to a system. They are capable of parallel processing and have the added bonus of reprogramability. Achronix has helped boost their utility by offering on-chip embedded FPGA fabric for integration into SoCs. This has had the effect of boosting data rates through these systems… Read More

September 17, 2019September 19, 2019

Learn About Implementing SmartNICs, an Achronix White Paper

Learn About Implementing SmartNICs, an Achronix White Paper
by Randy Smith on 09-17-2019 at 10:00 am
Categories: Achronix, eFPGA

We have all seen the announcements to provide ever-increasing network capabilities within the data centers. Enabling these advances are improvements in connectivity including SerDes, PAM4, optical solutions, and many others. It seems 40G is old news now, and the current push is for 400G – things are changing very quickly.… Read More

August 10, 2019August 19, 2019

Webinar – Fabless: The Transformation of the Semiconductor Industry 2019 Update!

Webinar – Fabless: The Transformation of the Semiconductor Industry 2019 Update!
by Daniel Nenni on 08-10-2019 at 6:00 am
Categories: Events

Image RemovedAs more than 343 people (and counting) know, we will be releasing the 2019 updated PDF version of our first book “Fabless: The Transformation of the Semiconductor Industry” via handout at a live webinar. The response has been overwhelming and I want to personally thank you. The webinar will be a brief overview of the… Read More

May 24, 2019May 23, 2019

An evolution in FPGAs

An evolution in FPGAs
by Tom Simon on 05-24-2019 at 5:00 am
Categories: Achronix, FPGA, TSMC

Why does it seem like current FPGA devices work very much like the original telephone systems with exchanges where workers connected calls using cords and plugs? Achronix thinks it is now time to jettison Switch Blocks and adopt a new approach. Their motivation is to improve the suitability of FPGAs to machine learning applications,… Read More

May 7, 2019November 13, 2019

Design IP in 2018: Synopsys and Cadence Increase Market Share…

Design IP in 2018: Synopsys and Cadence Increase Market Share…
by Eric Esteve on 05-07-2019 at 7:00 am
Categories: IP, IPnest

…but ARM, Imagination, MIPS or Ceva have declined and lose market share. Semiconductor design IP market is still doing good in 2018, with 6% growth year over year. It’s half the growth rate seen in 2017, 2016 and 2015 and the growth decline is imputable to bad results from ARM, the market leader, but also from Imagination (#4), MIPS… Read More

April 25, 2019October 3, 2019

Deep Learning, Reshaping the Industry or Holding to the Status Quo

Deep Learning, Reshaping the Industry or Holding to the Status Quo
by Daniel Payne on 04-25-2019 at 12:00 pm
Categories: EDA, Mentor, a Siemens Business

AI, Machine Learning, Deep Learning and neural networks are all hot industry topics in 2019, but you probably want to know if these concepts are changing how we actually design or verify an SoC. To answer that question what better place to get an answer than from a panel of industry experts who recently gathered at DVcon with moderator… Read More

April 1, 2019

FPGA Landscape Update 2019

FPGA Landscape Update 2019
by Daniel Nenni on 04-01-2019 at 7:00 am
Categories: Achronix, FPGA, Xilinx
8 Comments

Image RemovedIn 2015 Intel acquired Altera for $16.7B changing one of the most heated rivalries (Xilinx vs Altera) the fabless semiconductor ecosystem has ever seen. Prior to the acquisition the FPGA market was fairly evenly split between Xilinx and Altera with Lattice and Actel playing to market niches in the shadows. There … Read More

February 7, 2019

Building Better ADAS SOCs

Building Better ADAS SOCs
by Tom Simon on 02-07-2019 at 12:00 pm
Categories: Achronix, Automotive, FPGA

Ever since we replaced horses in our personal transportation system, folks have been pining for cars that offer some relief from the constant need for supervision, control and management. Indeed, despite their obvious downsides, horses could be counted on to help with steering and obstacle avoidance. There are even cases when… Read More

December 14, 2018

Embeddable FPGA Fabric on TSMC 7nm

Embeddable FPGA Fabric on TSMC 7nm
by Tom Simon on 12-14-2018 at 7:00 am
Categories: Achronix, AI, FPGA

With their current line-up of embeddable and discrete FPGA products, Achronix has made a big impact on their markets. They started with their Speedster FPGA standard products, and then essentially created a brand-new market for embeddable FPGA IP cores. They have just announced a new generation of their Speedcore embeddable… Read More

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Recent Article Comments

A No-Fudge ML Architecture for Arm
Yes Kevin. Aligns with Arm embedded emphasis elsewhere. Would be a big departure for them to take on training, at…

— Bernard Murphy on November 15, 2019
Is the ASIC Business Dead?
It is not a bad exit per se. The acquisition agreement is up of the sec.gov website, and the financing…

— MarkK on November 14, 2019
A No-Fudge ML Architecture for Arm
You didn't stipulate, but assuming that Ethos is targeted at inference ?

— KevinK on November 14, 2019
ReRAM Revisited
Arthur - in reply to this accidentally misplaced question: Is this why TSM is concentrating on Crossbar to provide…

— Bernard Murphy on November 13, 2019
A No-Fudge ML Architecture for Arm
Arthur - I think you intended this comment for the ReRAM thread. I'll reply there

— Bernard Murphy on November 13, 2019
Is the ASIC Business Dead?
To Bernard: a model based on ASSP seems to see attraction. A Fabless who has already designed an ASSP…

— Eric Esteve on November 13, 2019
A No-Fudge ML Architecture for Arm
Is this why TSM is concentrating on Crossbar to provide on chip sophisticated memory? Will this advance if they…

— Arthur Hanson on November 13, 2019
Is the ASIC Business Dead?
Here is the Nirvana AI chip that eSilicon did: https://www.businesswire.com/news/home/20191112005277/en/Intel-Speeds-AI-Development-Deployment-Performance-New eSilicon did it for…

— Daniel Nenni on November 12, 2019
Is the ASIC Business Dead?
Talking about ASIC, we must split between "ASIC business" and "ASIC Technology". We know for long that…

— Eric Esteve on November 12, 2019
Is the ASIC Business Dead?
Ian has a good point on viability being in vertical integration. I wonder then who's handling all the systems silicon…

— Bernard Murphy on November 12, 2019

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Choose the Right ASIC Manufacturing Model for Your Business REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation REPLAY: Avoiding CDM (Charged Device Model) ESD Failures REPLAY: eFPGA – "What a great idea! But I have no idea how I’d use it!" REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification REPLAY: Fabless: The Transformation of the Semiconductor Industry REPLAY: The Brave New World of Customized Memory REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning REPLAY: VLSI Design Methodology Development REPLAY: Lightspeed Data Sync - Design Workspace Problems Solved! REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats? REPLAY: How ASIC/SoC Prototyping Solutions Can Help You! REPLAY: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso® REPLAY: Taiwan ESD Workshop Recording REPLAY: Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction REPLAY: Text: A Year of Breakfast Bytes by Paul McLellan (Free PDF Version) REPLAY: Finding Your Way Through Verification REPLAY: Concerned about IP security threats for your SoCs? REPLAY: Achronix: Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip REPLAY: PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior REPLAY: Thermal-induced Reliability Challenges and Solutions for Advanced IC Design [filter] => 1 [visual] => 1 [rw_opt] => Array ( [widget_select] => 1 [others_front_page] => 1 [cpt_page] => 1 [others_blog_page] => 1 ) [display_widget_mobile] => 1 )

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Tag: achronix

BittWare PCIe server card employs high throughput AI/ML optimized 7nm FPGA

Free webinar – Accelerating data processing with FPGA fabrics and NoCs

Learn About Implementing SmartNICs, an Achronix White Paper

Webinar – Fabless: The Transformation of the Semiconductor Industry 2019 Update!

An evolution in FPGAs

Design IP in 2018: Synopsys and Cadence Increase Market Share…

Deep Learning, Reshaping the Industry or Holding to the Status Quo

FPGA Landscape Update 2019

Building Better ADAS SOCs

Embeddable FPGA Fabric on TSMC 7nm

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Recent achronix Press

Achronix and BittWare launch VectorPath accelerator card with Speedster7t FPGAs

Achronix Exhibits High-Performance FPGA and eFPGA IP Solutions at Arm TechCon

Achronix Joins TSMC IP Alliance Program

Achronix Introduces Ground-Breaking FPGA Family, Delivering New Levels of Performance with Adaptability for High-Bandwidth Data Acceleration Applicati

Achronix Demonstrates Silicon Validation Device with 112 Gbps SerDes

Achronix Announces Partner Program for Speedster, Speedchip, and Speedcore Ecosystem

EDN Names Achronix’s Speedcore Gen4 eFPGA to its Hot 100 Products of 2018

Recent Article Comments

A No-Fudge ML Architecture for Arm

Is the ASIC Business Dead?

A No-Fudge ML Architecture for Arm

ReRAM Revisited

A No-Fudge ML Architecture for Arm

Is the ASIC Business Dead?

A No-Fudge ML Architecture for Arm

Is the ASIC Business Dead?

Is the ASIC Business Dead?

Is the ASIC Business Dead?