Chiplet ecosystems enable multi-vendor designs

Chiplet ecosystems enable multi-vendor designs
by Don Dingee on 02-20-2024 at 6:00 am

Chiplet Product Use Cases

Chiplets dominate semiconductor industry conversations right now – and after the recent Chiplet Summit, we expect the intensity to go up a couple of notches. One company name often heard is Blue Cheetah, and we had the opportunity to sit down with them recently to discuss their views and their just-announced design win at Tenstorrent.… Read More


Moderating Our Open Chiplet Enthusiasm. A NoC Perspective

Moderating Our Open Chiplet Enthusiasm. A NoC Perspective
by Bernard Murphy on 02-14-2024 at 6:00 am

Moderating Open Chiplet Enthusiasm

I recently talked with Frank Schirrmeister (Solutions & Business Development, Arteris) on the state of progress to the open chiplet ideal. You know – where a multi-die system in package can be assembled with UCIe (or other) connections seamlessly connecting data flows between dies. If artificial general intelligence and… Read More


Chiplets Open Pandora’s Box

Chiplets Open Pandora’s Box
by Daniel Nenni on 01-31-2024 at 6:00 am

Chiplet

Chiplets have simplified one area of design but opened pandora’s box on another front. The simulation complexity of each chiplet is lower but now the chiplet-to-chiplet interconnect has become complex. Folks are experimenting with different interconnect protocols, variations of UCIe, modifying UCIe settings, interface… Read More


Webinar: Addressing UCIe 1.1 IP and System Level Verification Challenges

Webinar: Addressing UCIe 1.1 IP and System Level Verification Challenges
by Admin on 01-08-2024 at 1:39 pm

Thursday, February 8, 2024 | 9-10 a.m. PT

The Universal Chiplet Interconnect Express (UCIe) v1.0 standard was introduced in March of 2022 and v1.1 was published in July 2023. There is a huge demand for an open chiplet ecosystem that will unleash innovation across the compute continuum which in turn increases the demand for power

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Alphawave Semiconductor Powering Progress

Alphawave Semiconductor Powering Progress
by Daniel Nenni on 01-03-2024 at 6:00 am

Alphawave Semiconductor Chiplets

Do you know who had another great year? Alphawave Semi did. Despite being relatively young in the industry (founded in 2017), the company has quickly gained recognition for its advancements in high-speed connectivity solutions.

They specialize in developing high-speed connectivity solutions for Data centre, AI, 5G wireless… Read More


Will Chiplet Adoption Mimic IP Adoption?

Will Chiplet Adoption Mimic IP Adoption?
by Eric Esteve on 12-28-2023 at 6:00 am

Adoption theory

If we look at the semiconductor industry expansion during the last 25 years, adoption of design IP in every application appears to be one of the major factors of success, with silicon technology incredible development by a x100 factor, from 250nm in 2018 to 3nm (if not 2nm) in 2023. We foresee the move to chiplet-based architecture… Read More


Unleashing the 1.6T Ecosystem: Alphawave Semi’s 200G Interconnect Technologies for Powering AI Data Infrastructure

Unleashing the 1.6T Ecosystem: Alphawave Semi’s 200G Interconnect Technologies for Powering AI Data Infrastructure
by Kalar Rajendiran on 12-19-2023 at 6:00 am

Alphawave Semi 224G SerDes 1st TestChip

In the rapidly evolving landscape of artificial intelligence (AI) and data-intensive applications, the demand for high-performance interconnect technologies has never been more critical. Even the 100G Interconnect is already not fast enough for infrastructure applications. AI applications, with their massive datasets… Read More


UCIe InterOp Testchip Unleashes Growth of Open Chiplet Ecosystem

UCIe InterOp Testchip Unleashes Growth of Open Chiplet Ecosystem
by Kalar Rajendiran on 12-11-2023 at 6:00 am

Pike Creek UCIe Test chip

Intel recently made headlines when CEO Pat Gelsinger unveiled the world’s first UCIe interoperability test chip demo at Innovation 2023. The test chip built using advanced packaging technology is codenamed Pike Creek and is used to demonstrate interoperability across chiplets designed by Intel and Synopsys. More details … Read More


Webinar: Multi-Die System Verification with Siemens Avery UCIe VIP

Webinar: Multi-Die System Verification with Siemens Avery UCIe VIP
by Admin on 11-28-2023 at 4:42 pm

Summary

Conventional monolithic SoCs are becoming a bottleneck for power, performance, and area (PPA), creating limitations for Data-intensive applications like high-performance computing (HPC), machine learning (ML) and artificial intelligence (AI), and for hyperscale data centers. These bottlenecks are challenging

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