Webinar: Multi-Die System Verification with Siemens Avery UCIe VIP

Webinar: Multi-Die System Verification with Siemens Avery UCIe VIP
by Admin on 11-28-2023 at 4:42 pm

Summary

Conventional monolithic SoCs are becoming a bottleneck for power, performance, and area (PPA), creating limitations for Data-intensive applications like high-performance computing (HPC), machine learning (ML) and artificial intelligence (AI), and for hyperscale data centers. These bottlenecks are challenging

Read More

Keysight EDA 2024 Delivers Shift Left for Chiplet and PDK Workflows

Keysight EDA 2024 Delivers Shift Left for Chiplet and PDK Workflows
by Don Dingee on 09-28-2023 at 8:00 am

Chiplet PHY Designer

Much of the recent Keysight EDA 2024 announcement focuses on high-speed digital (HSD) and RF EDA features for Advanced Design System (ADS) and SystemVue users, including RF System Explorer, DPD Explorer (for digital pre-distortion), and design elements for 5G NTN, DVB-S2X, and satcom phased array applications. Two important… Read More


Webinar: The UCIe™ 1.1 Specification: Future Applications of Chiplets

Webinar: The UCIe™ 1.1 Specification: Future Applications of Chiplets
by Admin on 09-25-2023 at 3:05 pm

The UCIe™ 1.1 Specification: Future Applications of Chiplets
Thursday, October 12, 2023 
10 AM PT / 1 PM ET

Presenter: Dr. Debendra Das Sharma, UCIe Consortium Chairman and Intel Senior Fellow, Chief Architect of I/O Technology and Standards at Intel 

The UCIe™ (Universal Chiplet Interconnect Express™) 1.1 Specification

Read More

Webinar: UCIe-Based Chiplet Verification – from IP to SoC

Webinar: UCIe-Based Chiplet Verification – from IP to SoC
by Admin on 09-15-2023 at 12:15 pm

About

Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine chiplets with different functionality… Read More


Webinar: UCIe-Based Chiplet Verification – from IP to SoC

Webinar: UCIe-Based Chiplet Verification – from IP to SoC
by Admin on 08-21-2023 at 1:34 pm

Date: Wednesday, August 30, 2023

Time: 11:00am PDT | 1:00pm CDT | 2:00pm EDT

Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express… Read More


Webinar: Step-by-Step Guide for Your UCIe Design Verification

Webinar: Step-by-Step Guide for Your UCIe Design Verification
by Admin on 08-07-2023 at 5:01 pm

Synopsys Webinar | Thursday, August 10, 2023 | 9-10 a.m. Pacific

As traditional Moore’s law scaling approaches its physical limits, the industry is moving towards multi-die solutions for higher electronics system densities. Multi-die designs present one way for engineers to pack more functionality into silicon chips and

Read More

Alphawave Semi Visit at #60DAC

Alphawave Semi Visit at #60DAC
by Daniel Payne on 08-03-2023 at 10:00 am

Alphawavesemi, DAC 2023 3nm eye diagram

On Wednesday at #60DAC I met Sudhir Mallya, Sr. VP Corporate Marketing at Alphawave Semi to get an update about what’s been happening at their IP company and with industry trends. The tagline for their company is: Accelerating the Connected World; and they have IP for connectivity, offer chiplet solutions, and even provide… Read More


Webinar: UCIe: On-Package Chiplet Innovation Opportunities

Webinar: UCIe: On-Package Chiplet Innovation Opportunities
by Admin on 07-31-2023 at 2:17 pm

Synopsys Webinar | Tuesday, August 15, 2023 | 10:00 -11:00 a.m. PDT

High-performance workloads demand on-package integration of heterogeneous processing units, on-package memory, and communication infrastructure to meet the demands of today’s data centers, autonomous vehicles, etc. On-package interconnects are a critical

Read More

Synopsys Expands Agreement with Samsung Foundry to Increase IP Footprint

Synopsys Expands Agreement with Samsung Foundry to Increase IP Footprint
by Kalar Rajendiran on 06-20-2023 at 6:00 am

Synopsys Samsung silicon wafer

Many credible market analysis firms are predicting the semiconductor market to reach the trillion dollar mark over the next six years or so. Just compare this to the more than six decades it took for the market to cross the $500 billion mark. The projected growth rate is incredible indeed and is driven by fast growing market segments… Read More