RISC-V continued to be a significant force at #61DAC. There were many events that focused on its application in a wide variety of markets. As anyone who has used an embedded processor knows, the trick is how to be competitive. Using the same core as everyone else and differentiating in software is a strategy that tends to run out of … Read More
Codasip at the 2024 Design Automation Conference
Codasip will be demonstrating its new L110 core alongside Codasip Studio Fusion at #61DAC. Codasip L110 delivers up to 50% improvements in performance per watt and 20% smaller code size compared to similar cores in the market. The core offers extensive configurability, allowing different area/performance trade-off levels,… Read More
Webinar – CHERI: Fine-Grained Memory Protection to Prevent Cyber Attacks
Cyber attacks are top of mind for just about everyone these days. As massive AI data sets become more prevalent (and more valuable), data security is no longer “nice to have”. Rather, it becomes critical for continued online operation and success. The AI discussion is a double-edged sword as well. While AI enables many new and life-changing… Read More
An open letter regarding Cyber Resilience of the UK’s Critical National Infrastructure
Codasip announced a commercially available RISC-V processor with CHERI for license in October of 2023 and is demonstrating technology for IP provenance.
Dear Members of the Science, Innovation and Technology Committee,
Let me start by applauding your hearing on 24 April 2024, and in particular the evidence of Professor John… Read More
Webinar: Fine-grained Memory Protection to Prevent RISC-V Cyber Attacks
Most organizations are aware of cybercrime attempts such as phishing, installing malware from dodgy websites or ransomware attacks and undertake countermeasures. However, relatively little attention has been given to memory safety vulnerabilities such as buffer overflows or over-reads. For decades, the industry has created… Read More
How Codasip Unleashed CHERI and Created a Paradigm Shift for Secured Innovation
At the recent RISC-V Summit, Dr. Ron Black, CEO of Codasip unveiled a significant new capability to create a more secure environment for innovation. Rather than re-writing trillions of lines of code to solve the security problem, Ron described a much more practical approach. One that brought a research topic into mainstream deployment.… Read More
RISC-V Summit Buzz – Ron Black Unveils Codasip’s Paradigm Shift for Secured Innovation
Codasip is a processor solutions company with an expanding footprint. It is Europe’s leading RISC-V organization with a global presence. Codasip reports billions of chips already use its technology. You can learn more about Codasip here, The company has made some announcements recently that expand its offerings in terms … Read More
Extending RISC-V for accelerating FIR and median filters
RISC-V presents a unique opportunity for designers to extend the microarchitecture with custom instructions. One possible application is digital signal filtering using finite impulse response (FIR) or median filters, potential algorithms for carrier demodulation schemes in communications systems like 5G. Codasip application… Read More
Formal-based RISC-V processor verification gets deeper than simulation
The flexibility of RISC-V processor IP allows much freedom to meet specific requirements – but it also opens the potential for many bugs created during the design process. Advanced processor features are especially prone to errors, increasing the difficulty and time needed for thorough verification. Born out of necessity, … Read More
CEO Interview: Ron Black of Codasip
Dr. Black has over 30 years of industry experience. Before joining Codasip, he has been President and CEO at Imagination Technologies and previously CEO at Rambus, MobiWire (SAGEM Handsets), UPEK, and Wavecom. He holds a BS and MS in Engineering and a Ph.D. in Materials science from Cornell University. A consistent thread of his… Read More