Codasip is a processor solutions company with an expanding footprint. It is Europe’s leading RISC-V organization with a global presence. Codasip reports billions of chips already use its technology. You can learn more about Codasip here, The company has made some announcements recently that expand its offerings in terms of application areas and processor options. Dr. Ron Black has been the CEO at Codasip for almost three years. Previously, he was president and CEO at Imagination Technologies, CEO at Rambus, MobiWire, UPEK, and Wavecom. At his RISC-V Summit keynote, Ron discussed some major challenges for data security and an innovative approach to address those challenges. His presentation definitely got some attention. Read on to understand how Ron Black unveils Codasip’s paradigm shift for secured innovation.
Leading Up to the Summit – Expanding Footprint
In mid-October, Codasip announced the 700 RISC-V processor family, expanding its offering beyond embedded processor IP to stand-alone application processors. In its own words, “bringing the world of Custom Compute to everyone.” The 700 family is a configurable and customizable set of RISC-V baseline processors. It is intended to complement Codasip’s embedded cores by offering a different starting point to accommodate the need for higher performance.
Codasip Studio delivers a streamlined design process that unleashes the potential of the 700 family. Examples of the power of Codasip Studio include:
Enabling different levels of processor optimization for each use case:
- Through profiling
- Giving predictable results
- Improving time-to-market with a proven, highly automated approach
Automating processor design and custom SDK & HDK generation:
- Better results achieved in a more efficient way
- Accelerated exploration, investigation, and configuration
- Allowing maximal optimization
Fostering collaboration between hardware and software teams:
- To improve system efficiency
- Allowing teams to analyze and suggest changes to the hardware team
- Delivering differentiation and time-to-market in a highly competitive environment
The first core in the 700 family was also introduced. Codasip A730 is a 64-bit RISC-V application core that is being provided to early-access customers. It supports single-core or multi-core configurations and is Linux capable (MMU) with up to 2x the performance of the previous core. It employs a faster, tightly coupled cache coherent memory system as well. The core has broad market application from edge IoT to AI and sensor fusions. As you will see, the 700 family is also relevant to Codasip’s paradigm shift for secured innovation.
Ron’s Keynote at the Summit – Addressing the Elephant in the Room
Data security is a huge and growing problem. The specter of a data breach and the subsequent havoc associated with identity and monetary theft is on everyone’s mind. The headlines below illustrate the scope of the problem.
The problem at times can seem insurmountable. Huge amounts of money are lost each year from data breaches. There are so many “attack surfaces” and loopholes to worry about. Ron provided a rather startling insight about the problem at his keynote. It turns out a very large part of the problem is due to illegal memory access – 70 percent or more of the problem has this root cause. And more interesting, it’s been that way for a very long time. The graphic below drives home the point.
Ron then explored the dimensions of the problem – how big is it and what, if anything can be done to reduce the risk and financial loss. It turns out there is a substantial amount of legacy C/C++ code that is vulnerable. In-house, third-party, and open-source streams all contribute to the problem. And the incidence of data breaches is growing exponentially, as shown below.
So, what can be done to plug this rather large security hole? Ron outlined the options.
One could deploy tools to identify and fix all leaks and potential leaks in existing code. This would entail re-writing trillions of lines of code, perhaps with a memory safe approach like Rust. A direct, but intractable solution.
But what if you could use a specialized security processor to catch vulnerabilities natively? Something that could integrate with existing applications. This is a much better way, but does such an option actually exist?
Ron announced the news – both good and bad. The good news is that such a system does indeed exist. Capability Hardware Enhanced RISC Instructions (CHERI) is a specification developed by the University of Cambridge. It’s an architecture extension introducing hardware technology that mitigates software security vulnerabilities. It extends conventional hardware ISAs with memory protection and scalable compartmentalization. Something like this holds great promise since it can be integrated into existing systems with minor work vs. a major re-write.
There are several research projects underway for CHERI from the University of Cambridge and Microsoft, among others. And there is the bad news. It’s a research effort, not a production implementation. Until now.
Ron announced that Codasip is taking CHERI from a research topic to a commercial product thanks to RISC-V, CHERI, and the Codasip Custom Compute methodology. He explained that RISC-V is modular and allows customization. The company has taken its new Codasip 700 baseline processor design and enhanced it for security with CHERI technology using Codasip Studio.
This approach includes built-in, fine-grained memory protection by extending the RISC-V ISA with CHERI-based custom instructions. To enable the use of these instructions, Codasip is also delivering the software environment to take advantage of CHERI technology, bringing a full software development flow to add memory protection. Thanks to these developments, the world can now be a safer place with regard to data protection. Ron announced that Codasip was demonstrating this new core at the RISC-V Summit and lead customers would get early access to core with CHERI in the second half of 2024.
Comments From Ron
I got a chance to speak with Ron after his keynote. He likened data security to automobile insurance. No one really wants to pay for it, but you definitely want it just before you’re involved in an accident. Data breaches are like those automobile accidents. You need insurance in place at all times to truly be protected. With the introduction of a commercialized version of CHERI, that insurance is now available at a more reasonable cost, when compared with re-writing a massive code base.
Ron pointed out that CHERI is a cross-platform technology. Its benefits are not specific to RISC-V, but the open architecture of RISC-V make the implementation of CHERI more accessible. Will this new capability for improved data security find widespread use in the RISC-V community and will other architectures follow with commercial CHERI capabilities? Time will tell, but this innovation from Codasip could be the start of something big. And that’s how Ron Black unveils Codasip’s paradigm shift for secured innovation.Share this post via: