Sondrel Redefines the AI Chip Design Process

Sondrel Redefines the AI Chip Design Process
by Mike Gianfagna on 10-01-2024 at 6:00 am

Sondrel Redefines the AI Chip Design Process

Designing custom silicon for AI applications is a particularly vexing problem. These chips process enormous amounts of data with a complex architecture that typically contains a diverse complement of heterogeneous processors, memory systems and various IO strategies. Each of the many subsystems in this class of chip will … Read More


PQShield Builds the First-Ever Post-Quantum Cryptography Chip

PQShield Builds the First-Ever Post-Quantum Cryptography Chip
by Mike Gianfagna on 09-23-2024 at 6:00 am

PQShield Builds the First Ever Post Quantum Cryptography Chip

Quantum computing promises to deliver vast increases in processing power. The technology exploits the properties of quantum mechanics to create revolutionary increases in performance. Medical and material science research are examples of fields that will see dramatic improvement when production-worthy quantum computers… Read More


Siemens EDA Offers a Comprehensive Guide to PCIe® Transport Security

Siemens EDA Offers a Comprehensive Guide to PCIe® Transport Security
by Mike Gianfagna on 09-17-2024 at 6:00 am

Siemens EDA Offers a Comprehensive Guide to PCIe Transport Security

It is well-known that there is more data being generated all the time. The need to store and process that data with less power and higher throughput dominates design considerations for virtually all systems. There is another dimension to the problem – ensuring the data is secure as all this movement and processing occurs. Within… Read More


Samtec Demystifies Signal Integrity for Everyone

Samtec Demystifies Signal Integrity for Everyone
by Mike Gianfagna on 09-10-2024 at 6:00 am

Samtec Demystifies Signal Integrity for Everyone

As clock speeds go up, voltages go down and data volumes explode the need for fast, reliable and low latency data channels becomes critical in all kinds of applications. Balancing the requirements of low power and high performance requires the mastery of many skills. At the top of many lists is the need for superior signal integrity,… Read More


Calibre DesignEnhancer Improves Power Management Faster and Earlier

Calibre DesignEnhancer Improves Power Management Faster and Earlier
by Mike Gianfagna on 09-05-2024 at 6:00 am

Calibre DesignEnhancer Improves Power Management Faster and Earlier

Anyone who has attempted to implement a custom design in an advanced process node knows that effective power management can be quite challenging. Effects such as voltage (IR) drop and electromigration (EM) can present significant headaches for both design teams and foundries. Optimizing layouts for these kinds of issues is … Read More


Intel and Cadence Collaborate to Advance the All-Important UCIe Standard

Intel and Cadence Collaborate to Advance the All-Important UCIe Standard
by Mike Gianfagna on 09-02-2024 at 10:00 am

Intel and Cadence Collaborate to Advance the All Important UCIe Standard

The Universal Chiplet Interconnect Express™ (UCIe™) 1.0 specification was announced in early 2022 and a UCIe 1.1 update was released on August 8, 2023. This open standard facilitates the heterogeneous integration of die-to-die link interconnects within the same package. This is a fancy way of saying the standard opens the door… Read More


Analog Bits Momentum and a Look to the Future

Analog Bits Momentum and a Look to the Future
by Mike Gianfagna on 08-27-2024 at 6:00 am

Analog Bits Momentum and a Look to the Future

Analog Bits is aggressively moving to advanced nodes. On SemiWiki, Dan Nenni covered new IP in 3nm at DAC here. I covered the new Analog Bits 3nm IP presented at the TSMC Technology Symposium here. And now, there’s buzz about 2nm IP to be announced at the upcoming TSMC OIP event in September.  I was able to get a briefing from the master… Read More


A Closer Look at Conquering Clock Jitter with Infinisim

A Closer Look at Conquering Clock Jitter with Infinisim
by Mike Gianfagna on 08-26-2024 at 6:00 am

A Closer Look at Conquering Clock Jitter with Infinisim

As voltages go down and frequencies increase, the challenges in chip design become increasingly complex and unforgiving. Issues that once seemed manageable now escalate, while new obstacles emerge, demanding our attention. Among these challenges, clock jitter stands out as a formidable threat. At its core, clock jitter is… Read More


CAST Advances Lossless Data Compression Speed with a New IP Core

CAST Advances Lossless Data Compression Speed with a New IP Core
by Mike Gianfagna on 08-22-2024 at 6:00 am

CAST Advances Lossless Data Compression Speed with a New IP Core

Data compression is a critical element of many systems. Thanks to trends such as AI and highly connected systems there is more data to be stored and processed every day.  Data growth is staggering. Statista recently estimated that 90% of the world’s data was generated in the last two years. Storing and processing all that … Read More


Weebit Nano is at the Epicenter of the ReRAM Revolution

Weebit Nano is at the Epicenter of the ReRAM Revolution
by Mike Gianfagna on 08-20-2024 at 6:00 am

Weebit Nano is at the Epicenter of the ReRAM Revolution

It’s well known that flash is the embedded non-volatile memory (NVM) incumbent technology. As with many technologies, flash is bumping into limits such as power consumption, speed, endurance and cost. It is also not scalable below 28nm. This presents problems for applications such as AI inference engines that require embedded… Read More