The TSMC Open Innovation Platform (OIP) Ecosystem Forum has become the industry benchmark when it comes to showcasing industry-wide collaboration. The extreme design, integration and packaging demands presented by multi-die, chiplet-based design have raised the bar in terms of required collaboration across the entire … Read More
Author: Mike Gianfagna
Analog Bits Builds a Road to the Future at TSMC OIP
The Perils of Aging, From a Semiconductor Device Perspective
We‘re all aware of the challenges aging brings. I find the older I get, the more in touch I feel with those challenges. I still find it to be true that aging beats the alternative. I think most would agree. Human factors aside, I’d like to discuss the aging process as applied to the realm of semiconductor device physics. Here, as with… Read More
Sondrel Redefines the AI Chip Design Process
Designing custom silicon for AI applications is a particularly vexing problem. These chips process enormous amounts of data with a complex architecture that typically contains a diverse complement of heterogeneous processors, memory systems and various IO strategies. Each of the many subsystems in this class of chip will … Read More
PQShield Builds the First-Ever Post-Quantum Cryptography Chip
Quantum computing promises to deliver vast increases in processing power. The technology exploits the properties of quantum mechanics to create revolutionary increases in performance. Medical and material science research are examples of fields that will see dramatic improvement when production-worthy quantum computers… Read More
Siemens EDA Offers a Comprehensive Guide to PCIe® Transport Security
It is well-known that there is more data being generated all the time. The need to store and process that data with less power and higher throughput dominates design considerations for virtually all systems. There is another dimension to the problem – ensuring the data is secure as all this movement and processing occurs. Within… Read More
Samtec Demystifies Signal Integrity for Everyone
As clock speeds go up, voltages go down and data volumes explode the need for fast, reliable and low latency data channels becomes critical in all kinds of applications. Balancing the requirements of low power and high performance requires the mastery of many skills. At the top of many lists is the need for superior signal integrity,… Read More
Calibre DesignEnhancer Improves Power Management Faster and Earlier
Anyone who has attempted to implement a custom design in an advanced process node knows that effective power management can be quite challenging. Effects such as voltage (IR) drop and electromigration (EM) can present significant headaches for both design teams and foundries. Optimizing layouts for these kinds of issues is … Read More
Intel and Cadence Collaborate to Advance the All-Important UCIe Standard
The Universal Chiplet Interconnect Express™ (UCIe™) 1.0 specification was announced in early 2022 and a UCIe 1.1 update was released on August 8, 2023. This open standard facilitates the heterogeneous integration of die-to-die link interconnects within the same package. This is a fancy way of saying the standard opens the door… Read More
Analog Bits Momentum and a Look to the Future
Analog Bits is aggressively moving to advanced nodes. On SemiWiki, Dan Nenni covered new IP in 3nm at DAC here. I covered the new Analog Bits 3nm IP presented at the TSMC Technology Symposium here. And now, there’s buzz about 2nm IP to be announced at the upcoming TSMC OIP event in September. I was able to get a briefing from the master… Read More
A Closer Look at Conquering Clock Jitter with Infinisim
As voltages go down and frequencies increase, the challenges in chip design become increasingly complex and unforgiving. Issues that once seemed manageable now escalate, while new obstacles emerge, demanding our attention. Among these challenges, clock jitter stands out as a formidable threat. At its core, clock jitter is… Read More
Alchip Technologies Sets Another Record