Synopsys Enhances PPA with Backside Routing

Synopsys Enhances PPA with Backside Routing
by Mike Gianfagna on 03-19-2024 at 6:00 am

Comparison of frontside and backside PDNs (Source IMEC)

Complexity and density conspire to make power delivery very difficult for advanced SoCs. Signal integrity, power integrity, reliability and heat can seem to present unsolvable problems when it comes to efficient power management. There is just not enough room to get it all done with the routing layers available on the top side… Read More


Can Correlation Between Simulation and Measurement be Achieved for Advanced Designs?

Can Correlation Between Simulation and Measurement be Achieved for Advanced Designs?
by Mike Gianfagna on 03-18-2024 at 6:00 am

Can Correlation Between Simulation and Measurement be Achieved for Advanced Designs?

“What you simulate is what you get.” This is the holy grail of many forms of system design. Achieving a high level of accuracy between predicted and actual performance can cut design time way down, resulting in better cost margins, time to market and overall success rates. Achieving a high degree of confidence in predicted performance… Read More


Arteris is Unleashing Innovation by Breaking Down the Memory Wall

Arteris is Unleashing Innovation by Breaking Down the Memory Wall
by Mike Gianfagna on 03-14-2024 at 6:00 am

Arteris is Unleashing Innovation by Breaking Down the Memory Wall

There is a lot of discussion about removing barriers to innovation these days. Semiconductor systems are at the heart of unlocking many forms of technical innovation, if only we could address issues such as the slowing of Moore’s Law, reduction of power consumption, enhancement of security and reliability and so on. But there … Read More


How Sarcina Technology Makes Advanced Semiconductor Package Design Easier

How Sarcina Technology Makes Advanced Semiconductor Package Design Easier
by Mike Gianfagna on 03-11-2024 at 6:00 am

How Sarcina Technology Makes Advanced Semiconductor Package Design Easier

For a long time, package engineering was part of the cleanup crew for chip design. The glory was all around the design of advance monolithic chips on the latest technology node. Once the design was done, the package/test team would take the design over the finish line, adding the required I/O specs, lead frame, load board and test … Read More


How MZ Technologies is Making Multi-Die Design a Reality

How MZ Technologies is Making Multi-Die Design a Reality
by Mike Gianfagna on 03-04-2024 at 6:00 am

How MZ Technologies is Making Multi Die Design a Reality

The next design revolution is clearly upon us. Traditional Moore’s Law is slowing, but the exponential demand for innovation and form factor density is not. When you can no longer get it done with a single monolithic chip, moving to a multi-die approach is the answer. This emerging design methodology has many challenges – supply… Read More


Photonic Computing – Now or Science Fiction?

Photonic Computing – Now or Science Fiction?
by Mike Gianfagna on 02-26-2024 at 6:00 am

Photonic Computing – Now or Science Fiction?

Cadence recently held an event to dig into the emerging world of photonic computing. Called The Rise of Photonic Computing, it was a two-day event held in San Jose on February 7th and 8th. The first day of the event was also accessible virtually. I attended a panel discussion on the topic – more to come on that. The day delivered a rich… Read More


Achieving Extreme Low Power with Synopsys Foundation IP Memory Compilers and Logic Libraries

Achieving Extreme Low Power with Synopsys Foundation IP Memory Compilers and Logic Libraries
by Mike Gianfagna on 02-22-2024 at 10:00 am

Achieving Extreme Low Power with Synopsys Foundation IP Memory Compilers and Logic Libraries

The relentless demand for lower power SoCs is evident across many markets.  Examples include cutting-edge mobile, IoT, and wearable devices along with the high compute demands for AI and 5G/6G communications. Drivers for low power include battery life, thermal management and, for high compute applications, the overall cost… Read More


Synopsys and Alchip Accelerate IO & Memory Chiplet Design for Multi-Die Systems

Synopsys and Alchip Accelerate IO & Memory Chiplet Design for Multi-Die Systems
by Mike Gianfagna on 02-15-2024 at 6:00 am

Synopsys and Alchip Accelerate IO & Memory Chiplet Design for Multi Die Systems

Multi-die system design is clearly gaining momentum. Part of this momentum focuses on chiplets and a chiplet ecosystem. A “building block” approach for design will work better if there is a way to get verified, quality building blocks in the form of chiplets. The recent Chiplet Summit became an epicenter for this topic. The conference… Read More


proteanTecs Addresses Growing Power Consumption Challenge with New Power Reduction Solution

proteanTecs Addresses Growing Power Consumption Challenge with New Power Reduction Solution
by Mike Gianfagna on 02-06-2024 at 6:00 am

proteanTecs Addresses Growing Power Consumption Challenge with New Power Reduction Solution

proteanTecs is a unique company, delivering electronics visibility from within. Its core mission is to enable the electronics industry to continue to scale. The company achieves this goal by first embedding on-chip monitors, called Agents, during the design process to generate deep data on the chip’s profiling, health, and… Read More


A Rare Offer from The SHD Group – A Complimentary Look at the RISC-V Market

A Rare Offer from The SHD Group – A Complimentary Look at the RISC-V Market
by Mike Gianfagna on 01-30-2024 at 10:00 am

A Rare Offer from The SHD Group – A Complimentary Look at the RISC V Market

The web is a wonderful place to find information on almost any topic. While top-level information is easy to find, a deep dive often requires the services of a market research firm. These organizations specialize in “going deep” on many technology topics, offering insights not available with a Google search. And these services… Read More