The Hidden Cost of Using Claude for Documentation

The Hidden Cost of Using Claude for Documentation
by Mike Gianfagna on 05-29-2026 at 8:00 am

Why Generic LLMs Fall Short for Critical Engineering Documentation

Engineering documentation has always been difficult to produce, maintain, and scale. But with the rise of generative AI, many organizations are asking a reasonable question: can a general-purpose large language model (LLM) like Claude automate the work? At first glance, the answer appears to be yes.

Modern LLMs can generate… Read More


WEBINAR: Caspia’s AI Makes You a Security Verification Expert

WEBINAR: Caspia’s AI Makes You a Security Verification Expert
by Mike Gianfagna on 05-28-2026 at 10:00 am

Caspia 400 X 400 (2)

Let’s face it, powerful, highly trained AI is making it easier to find security flaws in many systems. When the attack surface becomes the underlying hardware, the risks grow exponentially. Unlike software, hardware can’t easily be “patched”. Early, advanced security verification is the way to mitigate these risks, but doing… Read More


How to Overcome the Advanced Node Physical Verification Bottleneck

How to Overcome the Advanced Node Physical Verification Bottleneck
by Mike Gianfagna on 04-22-2026 at 6:00 am

How to Overcome the Advanced Node Physical Verification Bottleneck

It is well-known that advanced semiconductor process technology presents substantial challenges across the full design flow and global supply chain. In this piece, we will focus on a particularly difficult problem – physical verification. This design step is the final gate to manufacturing. Producing a final tape‑out GDS … Read More


proteanTecs at Chiplet Summit – Changing the Game for Health & Performance Monitoring of Chiplets

proteanTecs at Chiplet Summit – Changing the Game for Health & Performance Monitoring of Chiplets
by Mike Gianfagna on 04-21-2026 at 6:00 am

proteanTecs at Chiplet Summit – Changing the Game for Health & Performance Monitoring of Chiplets

The recent Chiplet Summit 2026 was a great place to learn about new chiplet designs, emerging standards, and a growing array of support technologies to help design and manufacture chiplet-based systems. In my travels at the show, I found a lot of technology that fit these descriptions. But there were also companies at the show that… Read More


Analog Bits Demos Real-Time On-Chip Power Sensing and Delivery on N2P at the TSMC 2026 Technology Symposium

Analog Bits Demos Real-Time On-Chip Power Sensing and Delivery on N2P at the TSMC 2026 Technology Symposium
by Mike Gianfagna on 04-20-2026 at 6:00 am

Analog Bits Demos Real Time On Chip Power Sensing and Delivery on N2P at the TSMC 2026 Technology Symposium

Analog Bits has a way of stealing the show at every event they attend. The formula is actually quite straight-forward – come to the show with the most relevant, highest impact IP running on the most advanced process. The company will be applying this strategy again at the upcoming TSMC 2026 Technology Symposium with an array of real-time… Read More


Exploring the Hidden Complexity of Modern Power Electronics Design – A Siemens White Paper

Exploring the Hidden Complexity of Modern Power Electronics Design – A Siemens White Paper
by Mike Gianfagna on 04-15-2026 at 10:00 am

Exploring the Hidden Complexity of Modern Power Electronics Design – A Siemens White Paper

Review the specifications of any state-of-the-art microcontroller and you will discover the high dynamic current the device can consume. Examining the high clock rates and low tolerable voltage drop will lead you to the all-important power delivery network, or PDN. Components here include power planes, layer stack-up, decoupling… Read More


yieldHUB Expands Its Impact with New Technology and a New Website

yieldHUB Expands Its Impact with New Technology and a New Website
by Mike Gianfagna on 04-09-2026 at 10:00 am

yieldHUB Expands Its Impact with New Technology and a New Website

yieldHUB is a unique company that focuses on yield optimization for the semiconductor industry. The company aims to bring engineering teams together with a platform that allows sharing of data analytics and knowledge about products to improve yield. This goal is certainly fueled by unifying data from multiple steps in the manufacturing… Read More


yieldWerx Delivers a Master Class in Co-Packaged Photonics Implementation

yieldWerx Delivers a Master Class in Co-Packaged Photonics Implementation
by Mike Gianfagna on 04-06-2026 at 10:00 am

yieldWerx Delivers a Master Class in Co Packaged Photonics Implementation

We all know the semiconductor industry is seeing a new era of data intensity. The industry’s response includes advanced semiconductor design strategies, the adoption of chiplets, and the integration of optical I/O and photonics to enable higher performance, faster AI computation, and increased modularity. Co-packaged photonics… Read More


Samtec’s Strong Presence at embedded world 2026

Samtec’s Strong Presence at embedded world 2026
by Mike Gianfagna on 04-03-2026 at 6:00 am

Samtec’s Strong Presence at embedded world 2026

The embedded world Exhibition & Conference recently concluded. The event is held annually in Nuremberg, Germany and has become one of the most influential gatherings for the global embedded systems community. Since its inception in 2003, the event has grown from a modest technical meeting into a large-scale international… Read More


Webinar – How to Reclaim Margin in Advanced Nodes

Webinar – How to Reclaim Margin in Advanced Nodes
by Mike Gianfagna on 04-02-2026 at 6:00 am

Webinar – How to Reclaim Margin in Advanced Nodes

This informative webinar discusses a significant issue that is cropping up for sub-5nm designs. As the graphic above shows, modeling uncertainty at advanced nodes results in excessive guard banding. These guard bands result in reduced performance and profit. A loss of 25 – 35% in PPA is discussed, along with the lost profit associated… Read More