3D-IC design can be both exciting and frustrating. It’s exciting because it opens a new world of innovation possibilities – opportunities that aren’t constrained by the rules of monolithic chip scaling. It can be frustrating because of the large array of complex technical challenges that must be overcome to make this new paradigm… Read More
Author: Mike Gianfagna
MZ Technologies is Breaking Down 3D-IC Design Barriers with GENIO
One Thousand Production Licenses Means Silicon Creations PLL IP is Everywhere
If you sell sneakers, 1,000 pair is called a humble beginning. On the other hand, selling 1,000 licenses for specialized analog IP is a home run. Silicon Creations celebrated a home run for a critical piece of analog IP that finds its way into a diverse array of applications. Succeeding in so many markets is noteworthy, and I want … Read More
Silicon Creations is Fueling Next Generation Chips
Next generation semiconductor design puts new stress on traditionally low-key parts of the design process. One example is packaging, which used to be the clean-up spot at the end of the design. Thanks to chiplet-based design, package engineers are now rock stars. Analog design is another one of those disciplines.
Not long ago,… Read More
Alchip is Paving the Way to Future 3D Design Innovation
At the recent TSMC OIP Ecosystem Forum in Santa Clara, there was an important presentation that laid the groundwork for a great deal of future innovation. Alchip and its IP and EDA partner Synopsys presented Efficient 3D Chiplet Stacking Using TSMC SoIC. The concept of 3D, chiplet-based design certainly isn’t new. SemiWiki maintains… Read More
Samtec Paves the Way to Scalable Architectures at the AI Hardware & Edge AI Summit
AI is exploding everywhere. We’ve all seen the evidence. The same thing is happening with AI conferences. The conference I will discuss here began in 2018 as the AI Hardware Summit. The initial venue was the Computer History Museum in Mountain View, CA. Like most things AI, this conference has grown substantially in a relatively… Read More
My Conversation with Infinisim – Why Good Enough Isn’t Enough
My recent post on a high-profile chip performance issue got me thinking. The root cause of the problem discussed there had to do with a clock tree circuit that was particularly vulnerable to reliability aging under elevated voltage and temperature. Chip aging effects have always got my attention. I’ve lived through a few of them… Read More
PQShield Demystifies Post-Quantum Cryptography with Leadership Lounge
Post-Quantum Cryptography, or PQC provides a technical approach to protect encrypted data and connections when quantum computers can cost-effectively defeat current approaches. Exactly when this will occur is open to much discussion, but the fact is this day is coming, some say in ten years. One of the imperatives is to deploy… Read More
How to Update Your FPGA Devices with Questa
It’s a fact of life that technology marches on. Older process nodes get replaced by newer ones. As a result, ASSPs and FPGAs are obsoleted, leaving behind large system design investments that need to re-done. Since many of these obsolete designs are performing well in the target application, this re-do task can be particularly … Read More
Sarcina Democratizes 2.5D Package Design with Bump Pitch Transformers
2.5D package design is rapidly finding its stride in a wide variety of applications, including AI. While there are still many challenges to its widespread adoption, the chiplet approach is becoming more popular compared to monolithic design. However, the required market to create a chiplet ecosystem is still under development.… Read More
Analog Bits Builds a Road to the Future at TSMC OIP
The TSMC Open Innovation Platform (OIP) Ecosystem Forum has become the industry benchmark when it comes to showcasing industry-wide collaboration. The extreme design, integration and packaging demands presented by multi-die, chiplet-based design have raised the bar in terms of required collaboration across the entire … Read More
TSMC 2025 Technical Symposium Briefing