The growth of complexity for silicon test as it relates to test data volume and test times is driven by multiple concurrent factors. One dimension is simply the increase in silicon complexity. However, other factors are playing a role as well. These include higher reliability requirements for new applications such as automotive,… Read More
Author: Tom Simon
Use Existing High Speed Interfaces for Silicon Test
5G Requires Rethinking Deployment Strategies
5G’s Departure from Its Predecessors
In each move from 1G to 4G people became accustomed to seeing the new generation as primarily offering increased bandwidth and efficiency. It would be a mistake to view the transition to 5G along these same lines. 5G takes Radio Area Networks (RANs) from a use model primarily for cell phone communications… Read More
Non Volatile Memory IP is Invaluable for PMICs
Power Management ICs are a vitally important part of system design. Evidence of this is cited by a Synopsys white paper that mentions how Apple acquired a portion of PMIC developer Dialog Semiconductor that was previously their exclusive PMIC supplier. Clearly Apple had decided that PMIC design was a strategic differentiating… Read More
The Clash Between 5G and Airline Safety
For 5G to really deliver on its promise of high bandwidth and good coverage, it needs to use an RF band known as C-Band (3.7 to 4.4 GHz). This band is ideal because its frequency is high enough to offer 100MHz wide channels and also low enough that signal attenuation, especially in urban areas, is minimal. In 2020 the FCC auctioned off… Read More
SIP Modules Solve Numerous Scaling Problems – But Introduce New Issues
Multi-chip modules are now more important than ever, even though the basic concept has been around for decades. With The effects of Moore’s Law and other factors such as yield, power, and process choices, reasons for dividing what once would have been a single SOC into multiple die and integrating them in a single module have become… Read More
MBIST Power Creates Lurking Danger for SOCs
The old phrase that the cure is worse than the disease is apropos when discussing MBIST for large SOCs where running many MBIST tests in parallel can exceed power distribution network (PDN) capabilities. Memory Built-In Self-Test (MBIST) usually runs automatically during power on events. Due to the desire to speed up test and … Read More
It’s Now Time for Smart Clock Networks
By now most SoC designers are pretty familiar and comfortable with the use of Network on Chip (NOC) IP for interconnecting functional blocks. Looking at the underlying change that NOCs represent, we see the use of IP to supplant the use of tools for implementing a critical part of the design. The idea that ‘smart’ things are better… Read More
Identity and Data Encryption for PCIe and CXL Security
Privacy and security have always been a concern when it comes to computing. In prior decades for most people this meant protecting passwords and locking your computer. However, today more and more users are storing sensitive data in the cloud, where it needs to be protected at rest and while in motion. In a Synopsys webinar Dana Neustadter,… Read More
Demand for High Speed Drives 200G Modulation Standards
Right now, the most prevalent generation of Ethernet for data centers is 400 Gbps, with the shift to 800 Gbps coming rapidly. It is expected that by 2025 there will be 25 million units of 800 Gbps shipped. Line speeds of 100G are used predominantly for 400 Gbps Ethernet – requiring 4 lanes each. Initially 800 Gbps will simply … Read More
White Paper: A Closer Look at Aging on Clock Networks
We all know that designers work hard to reach design closure on SOC designs. However, what gets less attention from consumers is the effort that goes into ensuring that these chips will be fully operational and meeting timing specs over their projected lifetime. Of course, this is less important for chips used in devices with projected… Read More
The Data Crisis is Unfolding – Are We Ready?